summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | * | | clk: baikal-t1: Fix invalid xGMAC PTP clock dividerSerge Semin2022-09-301-1/+1
| | * | | clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODSerge Semin2022-09-301-1/+1
| | |/ /
| | | |
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| *-----. \ \ Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' int...Stephen Boyd2022-10-049-55/+2331
| |\ \ \ \ \ \
| | | | | * | | clk: davinci: cfgchip: Use dev_err_probe() helperYang Yingliang2022-09-301-2/+1
| | | | | * | | clk: davinci: pll: fix spelling typo in commentJiangshan Yi2022-09-301-1/+1
| | | | | |/ /
| | | | * | | clk: pxa: add a check for the return value of kzalloc()Xiaoke Wang2022-10-031-0/+2
| | | | * | | clk: mmp: pxa168: control shared SDH bits with separate clockDoug Brown2022-09-301-4/+7
| | | | * | | clk: mmp: pxa168: add clocks for SDH2 and SDH3Doug Brown2022-09-301-0/+6
| | | | * | | clk: mmp: pxa168: fix GPIO clock enable bitsDoug Brown2022-09-301-1/+1
| | | | * | | clk: mmp: pxa168: add muxes for more peripheralsDoug Brown2022-09-301-10/+32
| | | | * | | clk: mmp: pxa168: fix incorrect parent clocksDoug Brown2022-09-301-6/+6
| | | | * | | clk: mmp: pxa168: fix const-correctnessDoug Brown2022-09-301-7/+7
| | | | * | | clk: mmp: pxa168: add new clocks for peripheralsDoug Brown2022-09-301-0/+3
| | | | * | | clk: mmp: pxa168: fix incorrect dividersDoug Brown2022-09-301-2/+2
| | | | * | | clk: mmp: pxa168: add additional register definesDoug Brown2022-09-301-7/+24
| | | | |/ /
| | | * / / clk: sprd: Add clocks support for UMS512Cixi Geng2022-09-303-0/+2209
| | | |/ /
| | * | | clk: fixed-rate: add devm_clk_hw_register_fixed_rateDmitry Baryshkov2022-09-291-4/+24
| | * | | clk: asm9260: use parent index to link the reference clockDmitry Baryshkov2022-09-291-17/+12
| | |/ /
| | | |
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| *-------. \ \ Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner...Stephen Boyd2022-10-0425-255/+2163
| |\ \ \ \ \ \ \
| | | | | | * | | clk: imx: scu: fix memleak on platform_device_add() failsLin Yujun2022-09-301-1/+5
| | | | | | * | | clk: imx93: add SAI IPG clkPeng Fan2022-09-191-3/+9
| | | | | | * | | clk: imx93: add MU1/2 clockPeng Fan2022-09-191-2/+6
| | | | | | * | | clk: imx93: switch to use new clk gate APIPeng Fan2022-09-191-4/+4
| | | | | | * | | clk: imx: add i.MX93 clk gatePeng Fan2022-09-193-0/+204
| | | | | | * | | clk: imx: clk-composite-93: check white_listPeng Fan2022-09-193-5/+10
| | | | | | * | | clk: imx: clk-composite-93: check slice busyPeng Fan2022-09-191-3/+160
| | | | | | * | | clk: imx8mp: tune the order of enet_qos_root_clkPeng Fan2022-09-021-1/+1
| | | | | | |/ /
| | | | | * | | clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helperYang Yingliang2022-09-081-6/+3
| | | | | * | | clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helperYang Yingliang2022-09-081-13/+6
| | | | | * | | clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helperYang Yingliang2022-09-081-19/+9
| | | | | * | | clk: sunxi-ng: d1: Limit PLL rates to stable rangesSamuel Holland2022-08-251-0/+8
| | | | | |/ /
| | | | * | | clk: at91: sama5d2: Add Generic Clocks for UART/USARTSergiu Moga2022-09-151-0/+10
| | | | * | | clk: microchip: add PolarFire SoC fabric clock supportConor Dooley2022-09-142-0/+291
| | | | * | | clk: microchip: mpfs: update module authorship & licencingConor Dooley2022-09-141-3/+7
| | | | * | | clk: microchip: mpfs: convert periph_clk to clk_gateConor Dooley2022-09-141-66/+6
| | | | * | | clk: microchip: mpfs: convert cfg_clk to clk_dividerConor Dooley2022-09-141-68/+8
| | | | * | | clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()Conor Dooley2022-09-141-27/+6
| | | | * | | clk: microchip: mpfs: simplify control reg accessConor Dooley2022-09-141-25/+17
| | | | * | | clk: microchip: mpfs: move id & offset out of clock structsConor Dooley2022-09-141-15/+15
| | | | * | | clk: microchip: mpfs: add MSS pll's set & round rateConor Dooley2022-09-141-0/+54
| | | | * | | clk: microchip: mpfs: add reset controllerConor Dooley2022-09-142-12/+99
| | | * | | | clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven2022-09-181-0/+3
| | | * | | | clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven2022-09-181-0/+4
| | | * | | | clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven2022-09-181-0/+6
| | | * | | | clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven2022-09-181-0/+1
| | | * | | | clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang2022-08-291-0/+4
| | | * | | | clk: renesas: r9a09g011: Add IIC clock and reset entriesPhil Edworthy2022-08-291-0/+4
| | | * | | | clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_infoBiju Das2022-08-221-0/+2
| | | * | | | clk: renesas: r8a779f0: Add TMU and parent SASYNC clocksWolfram Sang2022-08-221-0/+10
| | | * | | | clk: renesas: r8a779f0: Add CMT clocksWolfram Sang2022-08-151-0/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-10 14:16:03 +0000