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| | | | * | clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor2020-05-261-5/+5
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| | | * | clk: versatile: remove redundant assignment to pointer clkColin Ian King2020-05-261-1/+1
| | | * | clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET2020-05-051-1/+1
| | | * | clk: Remove unused inline function clk_debug_reparentYueHaibing2020-05-051-4/+0
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| | * | clk: sprd: add mipi_csi_xx gate clocksChunyan Zhang2020-05-261-0/+32
| | * | clk: sprd: check its parent status before reading gate clockChunyan Zhang2020-05-262-0/+16
| | * | clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang2020-05-261-1/+1
| | * | clk: sprd: mark the local clock symbols staticChunyan Zhang2020-05-261-16/+16
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| *---------. \ Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' ...Stephen Boyd2020-06-0152-346/+1805
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| | | | | | | * | clk: ti: dra7: remove two unused symbolsJason Yan2020-05-261-9/+0
| | | | | | | * | clk: ti: dra7xx: fix RNG clock parentTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: dra7xx: mark MCAN clock as DRA76x onlyTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: dra7xx: fix gpu clkctrl parentTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: omap5: Add proper parent clocks for l4-secure clocksTero Kristo2020-05-141-7/+7
| | | | | | | * | clk: ti: omap4: Add proper parent clocks for l4-secure clocksTero Kristo2020-05-141-7/+7
| | | | | | | * | clk: ti: composite: fix memory leakTero Kristo2020-05-141-0/+1
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| | | | | | * | clk: at91: allow setting all PMC clock parents via DTMichał Mirosław2020-05-2610-10/+38
| | | | | | * | clk: at91: allow setting PCKx parent via DTMichał Mirosław2020-05-2612-13/+45
| | | | | | * | clk: at91: optimize pmc data allocationMichał Mirosław2020-05-2612-37/+20
| | | | | | * | clk: at91: pmc: decrement node's refcountClaudiu Beznea2020-05-261-0/+1
| | | | | | * | clk: at91: pmc: do not continue if compatible not locatedClaudiu Beznea2020-05-261-0/+2
| | | | | | * | clk: at91: Add peripheral clock for PTCCodrin Ciubotariu2020-05-261-0/+1
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| | | | | * | clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen2020-05-265-1/+528
| | | | | * | clk: socfpga: add const to _ops data structuresDinh Nguyen2020-05-263-4/+4
| | | | | * | clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen2020-05-263-6/+0
| | | | | * | clk: socfpga: stratix10: use new parent data schemeDinh Nguyen2020-05-265-41/+146
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| | | | * | clk: zynqmp: Make zynqmp_clk_get_max_divisor staticYueHaibing2020-05-261-1/+1
| | | | * | clk: zynqmp: Update fraction clock check from custom type flagsTejas Patel2020-05-261-2/+4
| | | | * | clk: zynqmp: Add support for custom type flagsRajan Vaja2020-05-262-0/+5
| | | | * | clk: zynqmp: fix memory leak in zynqmp_register_clocksQuanyang Wang2020-05-261-6/+9
| | | | * | clk: zynqmp: Fix invalid clock name queriesRajan Vaja2020-05-261-0/+5
| | | | * | clk: zynqmp: Fix divider2 calculationTejas Patel2020-05-261-5/+12
| | | | * | clk: zynqmp: Limit bestdiv with maxdivRajan Vaja2020-05-261-0/+2
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| | | * | clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slicePeng Fan2020-05-214-39/+39
| | | * | clk: imx: add imx8m_clk_hw_composite_busPeng Fan2020-05-212-0/+12
| | | * | clk: imx: add mux ops for i.MX8M composite clkPeng Fan2020-05-211-1/+50
| | | * | clk: imx8m: migrate A53 clk root to use composite corePeng Fan2020-05-203-9/+9
| | | * | clk: imx8mp: use imx8m_clk_hw_composite_core to simplify codePeng Fan2020-05-201-31/+16
| | | * | clk: imx8mp: Define gates for pll1/2 fixed dividersPeng Fan2020-05-201-18/+36
| | | * | clk: imx: imx8mp: fix pll mux bitPeng Fan2020-05-201-10/+10
| | | * | clk: imx8m: drop clk_hw_set_parent for A53Peng Fan2020-05-204-12/+0
| | | * | clk: imx: Add helpers for passing the device as argumentAbel Vesa2020-04-291-0/+29
| | | * | clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa2020-04-292-7/+14
| | | * | clk: imx: gate2: Allow single bit gating clockAbel Vesa2020-04-292-8/+36
| | | * | clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock waitAnson Huang2020-04-201-11/+5
| | | * | clk: imx: clk-sscg-pll: Remove unnecessary blank linesAnson Huang2020-04-201-10/+0
| | | * | clk: imx: drop the dependency on ARM64 for i.MX8MPeng Fan2020-04-141-4/+4
| | | * | clk: imx7ulp: make it easy to change ARM core clkPeng Fan2020-04-141-2/+4
| | | * | clk: imx: imx6ul: change flexcan clock to support CiA bitratesWaibel Georg2020-04-131-1/+1
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| | * | clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni2020-05-121-0/+7
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-04 17:18:31 +0000