summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-02-25201-6092/+18873
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have one small patch to the clk core this time around. It fixes a corner case with the CLK_OPS_PARENT_ENABLE flag combined with clk_core_is_enabled() where it hangs the system. We'll simply assume the clk is disabled if the parent is disabled and the flag is set. Trying to turn on the parent to check the enable state of the clk runs into system hangs at boot. We let this bake in -next for a couple weeks to make sure there aren't any more issues because the last attempt to fix this ran into hangs and had to be reverted. Note: There were some more patches to the core framework around sync_state and disabling unused clks, but I asked for that to be reverted from the qcom PR because it isn't ready and we're still discussing the best solution on the list. Outside of the core clk framework, we have the usual collection of clk driver updates and support for new SoCs (which seems to never stop). The dirstat is dominated by Qualcomm because they added support for quite a few SoCs this time around and also migrated quite a few of their drivers to clk_parent_data. The other big diff is in the Mediatek clk drivers that saw a significant rework this cycle to similarly modernize the code, and we'll see that work continue in the next cycle as well. Nothing really jumps out as scary here, except that the significant churn in parent data descriptions can have typos that go unnoticed. More details below. Core: - Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() New Drivers: - Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref clocks - Support for Mediatek MT7891 SoC clks - Support for many Qualcomm clk controllers: - QDU1000/QRU1000 global clock controller - SA8775P global clock controller - SM8550 TCSR and display clock controller - SM6350 clock controller - MSM8996 CBF and APCS clock controllers Updates: - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Versa 5P49V60 clks - Disable R-Car H3 ES1.*, as it was only available to an internal development group and needed a lot of quirks and workarounds - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and resets on Renesas RZ/V2M - Add display clocks on Renesas R-Car V4H - Add Camera Receiving Unit (CRU) clocks and resets on Renesas RZ/G2L - Free the imx_uart_clocks even if imx_register_uart_clocks returns early - Get the stdout clocks count from device tree on i.MX - Drop the clock count argument from imx_register_uart_clocks() - Keep the uart clocks on i.MX93 for when earlycon is used - Fix SPDX comment in i.MX6SLL clocks bindings header - Drop some unnecessary spaces from i.MX8ULP clocks bindings header - Add imx_obtain_fixed_of_clock() for allowing to add a clock that is not configured via devicetree - Fix the ENET1 gate configuration for i.MX6UL according to the reference manual - Add ENET refclock mux support for i.MX6UL - Add support for USB host/device configuration on Renesas RZ/N1 - Add PLL2 programming support, and CAN-FD clocks on Renesas R-Car V4H - Add D1 CAN bus gates and resets for Allwinner - Mark D1 CPUX clock as critical on Allwinner - Reuse D1 driver for Allwinner R528/T113 - Cleanup sunxi-ng Kconfig - Fix sunxi-ng kernel-doc issues - Model Allwinner H3/H5 DRAM clock as fixed clock - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll, sclk-div and cpu-dyn-div amlogic clock drivers - DDR clocks were marked as critical in the proper clock driver for each AT91 SoC such that drivers/memory/atmel-sdramc.c to be deleted in the next releases as it only does clock enablement - Patch to avoid compiling dt-compat.o for all AT91 SoCs as only some of them may use it - Support synchronous power_off requests in the qcom GDSC driver for proper GPU power collapse - Drop test clocks from various Qualcomm clk drivers - Update parent references to use clk_parent_data/clk_hw in various Qualcomm clk drivers - Fixes for the Qualcomm MSM8996 CPU clock controller - Transition Qualcomm MSM8974 GCC off the externally defined sleep_clk - Add GDSCs in the global clock controller for Qualcomm QCS404 - The SDCC core clocks on Qualcomm SM6115 are moved to floor_ops - Programming of clk_dis_wait for GPU CX GDSC on Qualcomm SC7180 and SDM845 are moved to use the recently introduced properties in the GDSC struct - Qualcomm's RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock is added on a variety of platforms - De-duplicate identical clks in Qualcomm SMD RPM clk driver - Add a few missing clocks across msm8998, msm8992, msm8916, qcs404 to Qualcomm SDM RPM clk driver - Various Qualcomm clk drivers use devm_pm_runtime_enable() to simplify" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (228 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused clk: imx: pll14xx: fix recalc_rate for negative kdiv clk: rs9: Drop unused pin_xin field MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function clk: mediatek: clk-mtk: Remove unneeded semicolon dt-bindings: clock: remove stih416 bindings dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file clk: imx: fix compile testing imxrt1050 clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include ...
| *-. Merge branches 'clk-loongson' and 'clk-qcom' into clk-nextStephen Boyd2023-02-2352-3504/+15041
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-loongson: dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file * clk-qcom: (143 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include clk: qcom: gcc-sa8775p: remove unused variables clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform clk: qcom: add msm8996 Core Bus Framework (CBF) support dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller clk: qcom: add the driver for the MSM8996 APCS clocks clk: qcom: gcc-qcs404: fix duplicate initializer warning clk: qcom: cpu-8996: change setup sequence to follow vendor kernel clk: qcom: cpu-8996: fix PLL clock ops clk: qcom: cpu-8996: fix ACD initialization clk: qcom: cpu-8996: fix PLL configuration sequence clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call clk: qcom: cpu-8996: setup PLLs before registering clocks clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb ...
| | | * clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREPStephen Boyd2023-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise some configurations fail. Fixes: 027726365906 ("clk: qcom: add the driver for the MSM8996 APCS clocks") Link: https://lore.kernel.org/r/20230223013847.1218900-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * clk: qcom: Revert sync_state based clk_disable_unusedBjorn Andersson2023-02-227-52/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert the postponement of clk_disable_unused() for clock providers that implement sync_state, and the change to drivers implementing this, until agreement on the implementation has been reached. This reverts: 29e31415e14e ("clk: qcom: Remove need for clk_ignore_unused on sc8280xp") 99c0f7d35c4b ("clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callback") 26b36df75166 ("clk: Add generic sync_state callback for disabling unused clocks") Requested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | | * clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov2023-02-081-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov2023-02-081-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-1-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: add missing cputype includeKrzysztof Kozlowski2023-02-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include asm/cputype.h to fix ARMv7 compile test error: drivers/clk/qcom/clk-cpu-8996.c: In function ‘qcom_cpu_clk_msm8996_acd_init’: drivers/clk/qcom/clk-cpu-8996.c:468:16: error: implicit declaration of function ‘read_cpuid_mpidr’ [-Werror=implicit-function-declaration] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved asm-include after linux/, per Stephen's request] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123201812.1230039-1-krzysztof.kozlowski@linaro.org
| | | * clk: qcom: gcc-sa8775p: remove unused variablesBartosz Golaszewski2023-02-081-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are four struct definitions in the driver that aren't used so remove them. Reported-by: kernel test robot <lkp@intel.com> Fixes: ed432b1ed00a ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123103338.230320-1-brgl@bgdev.pl
| | | * clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platformDmitry Baryshkov2023-02-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the list of RPM clocks provided on MSM8996 platform to also include RPM_SMD_XO_CLK_SRC and RPM_SMD_XO_A_CLK_SRC. Fixes: 7066fdd0d742 ("clk: qcom: clk-smd-rpm: add msm8996 rpmclks") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-6-dmitry.baryshkov@linaro.org
| | | * clk: qcom: add msm8996 Core Bus Framework (CBF) supportDmitry Baryshkov2023-02-082-1/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly based on AngeloGioacchino del Regno's work at [1]. The CBF is an interconnect between two CPU clusters, setting it up properly is required for booting the MSM8996 with all four cores enabled. [1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Dropped partially uninitialized variable "ret" from cbf_clk_notifier_cb()] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-4-dmitry.baryshkov@linaro.org
| | | * clk: qcom: add the driver for the MSM8996 APCS clocksDmitry Baryshkov2023-02-082-1/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple driver handling the APCS clocks on MSM8996. For now it supports just a single aux clock, linking GPLL0 to CPU and CBF clocks. Note, there is little sense in registering sys_apcs_aux as a child of gpll0. The PLL is always-on. And listing the gpll0 as a property of the apcs would delay its probing until the GCC has been probed (while we would like for the apcs to be probed as early as possible). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Fixed spelling of register, per Stephen's feedback] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230126230319.3977109-8-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-qcs404: fix duplicate initializer warningArnd Bergmann2023-01-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In one of the clocks, a redundant initialization for .num_parents got left behind by a recent patch: drivers/clk/qcom/gcc-qcs404.c:63:32: error: initialized field overwritten [-Werror=override-init] 63 | .num_parents = 1, | ^ Fixes: 2ce81afa0c7c ("clk: qcom: gcc-qcs404: sort out the cxo clock") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130135555.3268172-1-arnd@kernel.org
| | | * clk: qcom: cpu-8996: change setup sequence to follow vendor kernelDmitry Baryshkov2023-01-181-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing register writes to CPU clocks setup procedure. This makes it follow the setup procedure used in msm-3.18 kernel. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-14-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: fix PLL clock opsDmitry Baryshkov2023-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit better. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-13-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: fix ACD initializationDmitry Baryshkov2023-01-181-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vendor kernel applies different order while programming SSSCTL and L2ACDCR registers on power and performance clusters. However it was demonstrated that doing this upstream results in the board reset. Make both clusters use the same sequence, which fixes the reset. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-12-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: fix PLL configuration sequenceDmitry Baryshkov2023-01-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) before PLL configuration. Switch them to the ACD afterwards. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init callDmitry Baryshkov2023-01-181-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize ACD configuration from qcom_cpu_clk_msm8996_register_clks(), before registering all clocks. This way we can be sure that the clock is fully configured before letting CCF touch it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-10-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: setup PLLs before registering clocksDmitry Baryshkov2023-01-181-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup all PLLs before registering clocks in the common clock framework. This ensures that the clocks are not accessed before being setup in the known way and that the CCF is in sync with the actual HW programming. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-9-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cbDmitry Baryshkov2023-01-181-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Do not use the Alt PLL completely. Switch to smux when necessary to prevent overvolting - Restore the parent in case the rate change aborts for some reason - Do not duplicate resetting the parent in set_parent operation. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-8-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: skip ACD init if the setup is validDmitry Baryshkov2023-01-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether L2 registers contain correct values and skip programming if they are valid. This follows the code present downstream. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-7-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: support using GPLL0 as SMUX inputDmitry Baryshkov2023-01-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: fix the init clock rateDmitry Baryshkov2023-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current multiplier (60) results in CPU getting the rate which is unlisted in the CPU frequency tables (60 * 19.2 = 1152 MHz). This results in warnings from the cpufreq during startup. Change PLL programming (l = 54) to init CPU clocks to start with the frequency of 54 * 19.2 = 1036.8 MHz which is supported by both power and performance clusters from all speed bins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-5-dmitry.baryshkov@linaro.org
| | | * clk: qcom: cpu-8996: correct PLL programmingDmitry Baryshkov2023-01-181-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change PLL programming to follow the downstream setup. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-4-dmitry.baryshkov@linaro.org
| | | * clk: qcom: clk-alpha-pll: program PLL_TEST/PLL_TEST_U if requiredDmitry Baryshkov2023-01-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Program PLL_TEST and PLL_TEST_U registers if required by the pll configuration. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-3-dmitry.baryshkov@linaro.org
| | | * clk: qcom: Add QDU1000 and QRU1000 GCC supportTaniya Das2023-01-183-0/+2662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Made gcc_pcie_0_pipe_clk_src use clk_regmap_phy_mux_ops] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112204446.30236-3-quic_molvera@quicinc.com
| | | * clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov2023-01-181-313/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-12-dmitry.baryshkov@linaro.org
| | | * clk: qcom: mmcc-apq8084: remove spdm clocksDmitry Baryshkov2023-01-181-271/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPDM is used for debug/profiling and does not have any other functionality. These clocks can safely be removed. Suggested-by: Stephen Boyd <sboyd@kernel.org> Suggested-by: Georgi Djakov <djakov@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
| | | * clk: qcom: mmcc-apq8084: move clock parent tables downDmitry Baryshkov2023-01-181-100/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-10-dmitry.baryshkov@linaro.org
| | | * clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov2023-01-181-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-9-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRCDmitry Baryshkov2023-01-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-8-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov2023-01-181-359/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-7-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-apq8084: move PLL clocks upDmitry Baryshkov2023-01-181-81/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov2023-01-181-68/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-5-dmitry.baryshkov@linaro.org
| | | * clk: qcom: ipq8074: populate fw_name for usb3phy-sRobert Marko2023-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for usb3phy clocks in parent_data as they were missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents"). Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230108130440.670181-1-robimarko@gmail.com
| | | * clk: qcom: add the GCC driver for sa8775pShazad Hussain2023-01-183-0/+4815
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Global Clock Controller found in the QTI SA8775P platforms. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved to core_initcall(), per request of Konrad] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
| | | * clk: qcom: smd-rpm: msm8936: Add PMIC gated RPM_SMD_XO_*Bryan O'Donoghue2023-01-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XO crystal input is buffered through the PMIC and controlled by RPM. Create the relevant clock gate representation in the RPM clock definitions. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117024846.1367794-5-bryan.odonoghue@linaro.org
| | | * clk: qcom: rpmh: remove duplicate IPA clock referenceArnd Bergmann2023-01-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the ones that were recently added was already there: drivers/clk/qcom/clk-rpmh.c:578:35: error: initialized field overwritten [-Werror=override-init] 578 | [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, Fixes: aa055bf158cd ("clk: qcom: rpmh: define IPA clocks where required") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117170217.2462320-1-arnd@kernel.org
| | | * clk: qcom: Remove need for clk_ignore_unused on sc8280xpBjorn Andersson2023-01-162-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the transition of disabling unused clocks at sync_state, rather than late_initcall() it's now possible to drop clk_ignore_unused and unused clock disabled once client drivers have probed. Do this on SC8280XP. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113041038.4188995-1-quic_bjorande@quicinc.com
| | | * clk: qcom: rpmh: define IPA clocks where requiredDmitry Baryshkov2023-01-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the example of sc7180 and sdx55 and implement IP0 resource as clocks rather than interconnects. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109002935.244320-11-dmitry.baryshkov@linaro.org
| | | * clk: qcom: camcc-sm6350: Make camcc_sm6350_hws staticKonrad Dybcio2023-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no reason for it not to be static, and some compilers don't like not it being that way. Make it so. Reported-by: kernel test robot <lkp@intel.com> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230107120434.1902666-1-konrad.dybcio@linaro.org
| | | * clk: qcom: gcc-msm8974: switch from sleep_clk_src to sleep_clkDmitry Baryshkov2023-01-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc-msm8974 uses the registered sleep_clk_src clock, which is just a 1:1 fixed factor clock register on top of the board's sleep_clk. Switch the driver to use the board sleep_clk directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228203725.3131237-1-dmitry.baryshkov@linaro.org
| | | * clk: qcom: mmcc-msm8998: get rid of test clockDmitry Baryshkov2023-01-101-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-16-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-sdx55: get rid of test clockDmitry Baryshkov2023-01-101-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-13-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-sdx55: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov2023-01-101-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-12-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-sc7180: get rid of test clockDmitry Baryshkov2023-01-101-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-11-dmitry.baryshkov@linaro.org
| | | * clk: qcom: gcc-msm8998: get rid of test clockDmitry Baryshkov2023-01-101-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-10-dmitry.baryshkov@linaro.org
| | | * clk: qcom: dispcc-qcm2290: get rid of test clockDmitry Baryshkov2023-01-101-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-9-dmitry.baryshkov@linaro.org
| | | * clk: gcc-sm8350: drop PLL test clockKrzysztof Kozlowski2023-01-101-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no user of core_bi_pll_test_se test clock so drop it. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228140917.118861-3-krzysztof.kozlowski@linaro.org
| | | * clk: gcc-sm8150: drop PLL test clockKrzysztof Kozlowski2023-01-101-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no user of core_bi_pll_test_se test clock so drop it. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228140917.118861-2-krzysztof.kozlowski@linaro.org
| | | * clk: qcom: clk-spmi-pmic-div: convert to use parent_dataDmitry Baryshkov2023-01-101-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk-spmi-pmic-div driver gets the parent name from the first (and the only) clock parent. So, use parent data, index 0 to setup the clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221210191013.453040-1-dmitry.baryshkov@linaro.org
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-21 15:06:06 +0000