summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | | | | | * | clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo2018-07-081-1/+1
| | | | | | * | clk: rockchip: add clock controller for px30Elaine Zhang2018-07-063-1/+1080
| | | | | | * | clk: rockchip: add support for half dividerElaine Zhang2018-07-064-0/+323
| | | | | | |/
| | | | | * | clk: imx6sx: remove clks_init_on arrayAnson Huang2018-06-291-26/+14
| | | | | * | clk: imx6sl: remove clks_init_on arrayAnson Huang2018-06-291-12/+0
| | | | | * | clk: imx6q: remove clks_init_on arrayAnson Huang2018-06-291-12/+2
| | | | | |/
| | | | * / clk: imx7d: add IMX7D_MU_ROOT_CLKOleksij Rempel2018-07-091-0/+1
| | | | |/
| | | * | clk: meson: add gen_clkJerome Brunet2018-07-094-3/+135
| | | * | clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet2018-07-091-1/+0
| | | * | clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-092-1/+150
| | | * | clk: meson: remove unused clk-audio-divider driverJerome Brunet2018-07-093-119/+1
| | | * | clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
| | | * | clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-094-0/+982
| | | * | clk: meson: add axg audio sclk divider driverJerome Brunet2018-07-093-1/+252
| | | * | Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/driversJerome Brunet2018-07-091-5/+194
| | | |\ \
| | | * | | clk: meson: add triple phase clock driverJerome Brunet2018-07-094-0/+94
| | | * | | clk: meson: add clk-phase clock driverJerome Brunet2018-07-093-0/+72
| | | * | | clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5
| | | * | | clk: meson: remove obsolete register accessJerome Brunet2018-07-092-69/+4
| | * | | | clk: mvebu: armada-37xx-periph: switch to SPDX license identifierGregory CLEMENT2018-07-091-4/+1
| | | |_|/ | | |/| |
| | | | |
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| *-------. \ \ \ Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd2018-08-145-36/+30
| |\ \ \ \ \ \ \ \
| | | | | | * | | | clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko2018-07-081-1/+1
| | | | | | |/ / /
| | | | | * / / / clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko2018-07-081-2/+3
| | | | | |/ / /
| | | | * | | | clk: tegra: Make vde a child of pll_c3Thierry Reding2018-07-081-1/+1
| | | | * | | | clk: tegra: Make vic03 a child of pll_c3Thierry Reding2018-07-081-0/+1
| | | | |/ / /
| | | * / / / clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen2018-07-081-3/+9
| | | |/ / /
| | * | | | clk: imx51-imx53: Include sizes.h to silence compile errorsStephen Boyd2018-07-061-0/+1
| | * | | | clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICALFabio Estevam2018-07-061-29/+14
| | |/ / /
| | | | |
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| *-------. \ \ \ Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-as...Stephen Boyd2018-08-149-11/+415
| |\ \ \ \ \ \ \ \
| | | | | | * | | | clk: imx6sll: add GPIO LPCGsAnson Huang2018-07-061-0/+6
| | | | | | |/ / /
| | | | | * / / / clk: aspeed: Fix SDCLK nameLei YU2018-07-061-1/+1
| | | | | |/ / /
| | | | * / / / clk: pxa: export 32kHz PLLRobert Jarzmik2018-07-063-8/+12
| | | | |/ / /
| | | * / / / clk: Add driver for MAX9485Daniel Mack2018-07-063-0/+394
| | | |/ / /
| | * | | | clk: ingenic: Add missing flag for UDC clockPaul Cercueil2018-07-061-1/+1
| | * | | | clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil2018-07-061-1/+1
| | |/ / /
| | | | |
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| *-------. \ \ \ Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-ren...Stephen Boyd2018-08-149-7/+1066
| |\ \ \ \ \ \ \ \
| | | | | | * | | | clk: at91: add I2S clock mux driverCodrin Ciubotariu2018-07-062-0/+117
| | | | | | |/ / /
| | | | | * | | | clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen2018-07-061-1/+1
| | | | | * | | | clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen2018-07-061-1/+6
| | | | | |/ / /
| | | | * | | | clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-253-0/+900
| | | | * | | | clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef2018-06-191-0/+1
| | | | * | | | clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven2018-06-191-0/+1
| | | | |/ / /
| | | * / / / clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal2018-07-031-4/+39
| | | |/ / /
| | * / / / clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SELPhilipp Puschmann2018-06-291-1/+1
| | |/ / /
| | | | |
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| | \ \ \
| *-----. \ \ \ Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', 'clk-core-...Stephen Boyd2018-08-144-27/+292
| |\ \ \ \ \ \ \ | | | | |_|_|_|/ | | | |/| | | |
| | | | | * | | clk: imx6ul: remove clks_init_on arrayAnson Huang2018-06-291-17/+6
| | | | | * | | clk: imx6ul: add GPIO clock gatesAnson Huang2018-06-291-0/+5
| | | | | |/ /
| | | | * / / clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operationsMike Looijmans2018-06-292-2/+74
| | | | |/ /
| | * | / / clk: fix CLK_SET_RATE_GATE with clock rate protectionJerome Brunet2018-06-191-3/+13
| | | |/ / | | |/| |
| * / | | clk: qcom: drop CLK_SET_RATE_GATE from sdc clocksJerome Brunet2018-06-194-15/+0
| |/ / /
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 10:17:41 +0000