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path: root/drivers/cxl/acpi.c
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* Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-101-1/+2
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| * cxl/dax: Create dax devices for CXL RAM regionsDan Williams2023-02-101-1/+2
* | Merge branch 'for-6.3/cxl' into cxl/nextDan Williams2023-02-071-1/+1
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| * | cxl: fix spelling mistakesRandy Dunlap2023-01-261-1/+1
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* / cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams2023-01-251-1/+0
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* cxl: update names for interleave ways conversion macrosDave Jiang2022-12-051-3/+3
* cxl: update names for interleave granularity conversion macrosDave Jiang2022-12-051-2/+2
* cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter2022-12-051-1/+2
* cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield2022-12-051-0/+5
* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-3/+134
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| * cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield2022-12-031-3/+134
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-5/+46
* | cxl/ACPI: Register CXL host ports by bridge deviceRobert Richter2022-12-021-18/+20
* | tools/testing/cxl: Make mock CEDT parsing more robustDan Williams2022-12-021-0/+4
* | cxl/acpi: Move rescan to the workqueueDan Williams2022-12-021-2/+15
* | cxl/acpi: Simplify cxl_nvdimm_bridge probingDan Williams2022-12-011-0/+1
* | cxl/acpi: Improve debug messages in cxl_acpi_probe()Robert Richter2022-11-141-4/+8
* | cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter2022-11-141-5/+2
* | cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter2022-11-141-2/+0
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* cxl/acpi: Minimize granularity for x1 interleavesDan Williams2022-08-011-0/+6
* cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams2022-08-011-0/+7
* cxl/port: Record parent dport when adding portsDan Williams2022-07-211-2/+1
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-4/+36
* cxl/acpi: Track CXL resources in iomem_resourceDan Williams2022-07-211-3/+141
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-1/+3
* cxl: Introduce cxl_to_{ways,granularity}Dan Williams2022-07-091-15/+19
* cxl/core: Drop ->platform_res attribute for root decodersDan Williams2022-07-091-7/+10
* cxl/acpi: Add root device lockdep validationDan Williams2022-04-281-0/+13
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-081-1/+2
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-16/+1
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-081-1/+1
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-25/+1
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-28/+15
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-081-59/+8
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-0/+2
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-5/+9
* cxl: Prove CXL lockingDan Williams2022-02-081-5/+5
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-081-5/+0
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-2/+2
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-14/+8
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-2/+11
* ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield2021-11-151-1/+2
* cxl/test: Mock acpi_table_parse_cedt()Dan Williams2021-11-151-0/+2
* cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams2021-11-151-147/+87
* cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBSAlison Schofield2021-10-081-4/+6
* cxl/core: Split decoder setup into alloc + addDan Williams2021-09-211-24/+60
* cxl/bus: Populate the target list at decoder createDan Williams2021-09-211-1/+12
* tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams2021-09-211-15/+21
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