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path: root/drivers/cxl
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* cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams2023-11-281-15/+19
* cxl/region: Fix x1 root-decoder granularity calculationsJim Harris2023-11-281-1/+8
* cxl/region: Do not try to cleanup after cxl_region_setup_targets() failsJim Harris2023-11-281-7/+7
* cxl/hdm: Remove broken error pathDan Williams2023-11-202-17/+10
* cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams2023-11-201-12/+31
* cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter2023-11-205-20/+20
* cxl/region: Fix cxl_region_rwsem lock held when returning to user spaceLi Zhijian2023-11-201-1/+1
* cxl/region: Use cxl_calc_interleave_pos() for auto-discoveryAlison Schofield2023-11-201-112/+15
* cxl/region: Calculate a target position in a region interleaveAlison Schofield2023-11-201-0/+127
* cxl/region: Prepare the decoder match range helper for reuseAlison Schofield2023-11-201-6/+11
* cxl/mem: Fix shutdown orderDan Williams2023-11-201-1/+1
* cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams2023-11-208-49/+90
* cxl/pci: Fix sanitize notifier setupDan Williams2023-11-203-42/+50
* cxl/pci: Clarify devm host for memdev relative setupDan Williams2023-11-203-12/+13
* cxl/pci: Remove inconsistent usage of dev_err_probe()Dan Williams2023-11-201-11/+2
* cxl/pci: Cleanup 'sanitize' to always pollDan Williams2023-11-203-39/+26
* cxl/pci: Remove unnecessary device reference management in sanitize workDan Williams2023-11-201-5/+0
* cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook2023-09-221-2/+2
* cxl/port: Fix cxl_test register enumeration regressionDan Williams2023-09-221-4/+9
* cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield2023-09-141-9/+8
* cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield2023-09-141-1/+23
* cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny2023-09-141-11/+12
* cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli2023-09-111-2/+1
* cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli2023-09-111-3/+3
* cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso2023-07-283-1/+78
* cxl/memdev: Document security state in kern-docDavidlohr Bueso2023-07-281-0/+1
* cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao2023-07-181-1/+1
* cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao2023-07-181-2/+1
* cxl/mem: Fix a double shift bugDan Carpenter2023-07-141-1/+1
* cxl: fix CONFIG_FW_LOADER dependencyArnd Bergmann2023-07-141-1/+2
* cxl: Fix one kernel-doc commentYang Li2023-06-291-1/+1
* cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso2023-06-271-1/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-2512-291/+443
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-252-0/+13
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-252-0/+29
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-254-18/+57
| * cxl/mem: Prepare for early RCH dport component register setupRobert Richter2023-06-251-5/+4
| * cxl/regs: Remove early capability checks in Component Register setupRobert Richter2023-06-253-9/+6
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-252-3/+0
| * cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter2023-06-251-28/+63
| * cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter2023-06-251-45/+45
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-253-74/+83
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-254-24/+31
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-257-63/+71
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-253-14/+14
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-254-7/+15
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-256-50/+61
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-2510-7/+224
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| * | perf: CXL Performance Monitoring Unit driverJonathan Cameron2023-06-251-0/+13
| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-309-1/+155
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