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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-051-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* dmaengine: mv_xor: Add support for scatter-gather DMA modeStefan Roese2016-11-251-0/+1
| | | | | | | | | | | | | This patch adds memory to memory scatter-gather support to the Marvell mv_or DMA driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: Add support for IO (PCIe) src/dst areasStefan Roese2016-09-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | To enable the access to a specific area, the MVEBU XOR controllers needs to have this area enabled / mapped via an address window. Right now, only the DRAM memory area is enabled via such memory windows. So using this driver to DMA to / from a e.g. PCIe memory region is currently not supported. This patch now adds support for such PCIe / IO regions by checking if the src / dst address is located in an IO memory area in contrast to being located in DRAM. This is done by using the newly introduced MBus function mvebu_mbus_get_io_win_info(). If the src / dst address is located in such an IO area, a new address window is created in the XOR DMA controller. Enabling the controller to access this area. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: use SoC type instead of directly the operation modeGregory CLEMENT2016-05-031-0/+1
| | | | | | | | | | | | Currently the main difference between legacy XOR engine and newer one, is the way the engine modes are setup (either in the descriptor or through the controller registers). In order to be able to take into account new generation of the XOR engine for the ARM64 SoC, we need to identify them by type, and then depending to the type the engine setup will be selected. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: add suspend/resume supportThomas Petazzoni2016-01-061-0/+1
| | | | | | | | | | | | | | This commit adds suspend/resume support to the mv_xor driver. The config and interrupt mask registers must be saved and restored, and upon resume, the MBus windows configuration must also be done again. Tested on Armada 388 GP, with a RAID 5 array, accessed before and after a suspend to RAM cycle. Based on work from Ofer Heifetz and Lior Amsalem. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: remove mv_xor_chan->current_type fieldThomas Petazzoni2016-01-061-1/+0
| | | | | | | | | Since commit 3e4f52e2da9f6 ("dma: mv_xor: Simplify the DMA_MEMCPY operation"), this field is no longer used, so get rid of it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: improve descriptors list handling and reduce lockingLior Amsalem2015-06-101-11/+6
| | | | | | | | | | | | | | This patch change the way free descriptors are marked. Instead of having a field for descriptor in use, all the descriptors in the all_slots list are free for use. This simplify the allocation method and reduce the locking needed. Signed-off-by: Lior Amsalem <alior@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: Enlarge descriptor pool sizeLior Amsalem2015-06-101-1/+1
| | | | | | | | | | | | | | | | Now that we have 2 channels assigned to 2 CPUs and all requests are chained on same channels, we need much more descriptors available to satisfy async_tx workload. 3072 descriptors was found in our lab as the number of descriptors which allow the async_tx stack to work without waiting for free descriptors on submission of new requests. Signed-off-by: Lior Amsalem <alior@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: add support for a38x command in descriptor modeLior Amsalem2015-06-101-0/+7
| | | | | | | | | | | | | | | | | | The Marvell Armada 38x SoC introduce new features to the XOR engine, especially the fact that the engine mode (MEMCPY/XOR/PQ/etc) can be part of the descriptor and not set through the controller registers. This new feature allows mixing of different commands (even PQ) on the same channel/chain without the need to stop the engine to reconfigure the engine mode. Refactor the driver to be able to use that new feature on the Armada 38x, while keeping the old behaviour on the older SoCs. Signed-off-by: Lior Amsalem <alior@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mv_xor: bug fix for racing condition in descriptors cleanupLior Amsalem2015-06-101-0/+1
| | | | | | | | | | | | | | | | This patch fixes a bug in the XOR driver where the cleanup function can be called and free descriptors that never been processed by the engine (which result in data errors). The cleanup function will free descriptors based on the ownership bit in the descriptors. Fixes: ff7b04796d98 ("dmaengine: DMA engine driver for Marvell XOR engine") Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Cc: stable@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: Remove FSF mailing addressesJarkko Nikula2015-03-161-4/+0
| | | | | | | | | Free Software Foundation mailing address has been moved in the past and some of the addresses here are outdated. Remove them from file headers since the COPYING file in the kernel sources includes it. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Add support for DMA_INTERRUPTLior Amsalem2014-09-231-5/+6
| | | | | | | | | | The driver is capable of supporting DMA_INTERRUPT by issuing a dummy 128-byte transfer. This helps removing a poll in the async_tx stack, replacing it with a completion interrupt. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Remove dead codeEzequiel Garcia2014-09-231-20/+0
| | | | | | | | | | | | | The driver currently defines the USE_TIMER macro, but the timer-feature is never used in the code. The XOR and CRC32 results are never used. The 'unmap_xxx' fields are no longer needed, they were made obsolete in commit: 54f8d501e842 dmaengine: remove DMA unmap from drivers. Let's remove all this dead code. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Reduce interrupts by enabling EOD only when neededLior Amsalem2014-09-231-1/+1
| | | | | | | | | | | | | This commit unmasks the end-of-chain interrupt and removes the end-of-descriptor command setting on all transactions, except those explicitly flagged with DMA_PREP_INTERRUPT. This allows to raise an interrupt only on chain completion, instead of on each descriptor completion, which reduces interrupt count. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Remove all interrupt magic numbersEzequiel Garcia2014-09-231-1/+21
| | | | | | | | | | | This commit replaces the current magic numbers in the interrupt handling with proper macros, which makes more readable and self-documenting. While here replace the BUG() with a noisy WARN_ON(). There's no reason to tear down the entire system for an DMA IRQ error. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Remove multi-slot supportLior Amsalem2014-09-231-7/+2
| | | | | | | | | | Although the driver supported multiple-slot allocation, only one slot was ever allocated for each transaction. So, given we have no users of the multi-slot support, we can remove it and greatly simplify the code. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mv_xor: Fix mis-usage of mmio 'base' and 'high_base' registersEzequiel Garcia2013-11-141-12/+13
| | | | | | | | | | | | | | | | Despite requesting two memory resources, called 'base' and 'high_base', the driver uses explicitly only the former. The latter is being used implicitly by addressing at offset +0x200, which in practice accesses high_base. In other words, the current driver breaks if the second memory resource is ever place at an offset different from +0x200. This patch fixes the above by defining the registers with the offset from high_base, and use high_base explicitly where appropriate. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* mv_xor: support big endian systems using descriptor swap featureThomas Petazzoni2013-08-221-1/+27
| | | | | | | | | | | | | | | The mv_xor driver had never been used in a big-endian context, and therefore was not using the hardware features to support such an execution environment. The hardware provides a "descriptor swap" bit that automatically swaps the bytes of the DMA descriptors, within blocks of 8 bytes. This requires a different DMA descriptor layout on big-endian systems, as well as enabling this "descriptor swap" bit. This mechanism is exactly identical to the one already used in the mv643xx_eth network driver and the mvneta network driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Williams <djbw@fb.com>
* drivers/dma: remove unused support for MEMSET operationsBartlomiej Zolnierkiewicz2013-07-031-1/+0
| | | | | | | | | | | | | | | | | | | | There have never been any real users of MEMSET operations since they have been introduced in January 2007 by commit 7405f74badf4 ("dmaengine: refactor dmaengine around dma_async_tx_descriptor"). Therefore remove support for them for now, it can be always brought back when needed. [sebastian.hesselbarth@gmail.com: fix drivers/dma/mv_xor] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Vinod Koul <vinod.koul@intel.com> Acked-by: Dan Williams <djbw@fb.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Olof Johansson <olof@lixom.net> Cc: Kevin Hilman <khilman@linaro.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* dma: mv_xor: clear the window override control registersThomas Petazzoni2012-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | The XOR channels on Marvell SoCs have a Window Override Control register that allow to do some fancy things with addresses. Those features are not used by the driver, but some U-Boot versions anyway modify those registers. For some reason, the U-Boot on OpenBlocks AX3-4 was setting an invalid value in those registers when the addition 2 GB DRAM chip was plugged into the board, causing the XOR driver to fail in using the XOR engines. By setting those registers to 0 during the driver initialization, we ensure that the registers are configured according with the driver operation model. Thanks to Lior Amsalem <alior@marvell.com> for his help in debugging this problem. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: add missing free_irq() callThomas Petazzoni2012-11-201-0/+1
| | | | | | | Even though the driver cannot be unloaded at the moment, it is still good to properly free the IRQ handlers in the channel removal function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: remove the pool_size from platform_dataThomas Petazzoni2012-11-201-0/+1
| | | | | | | | | The pool_size is always PAGE_SIZE, and since it is a software configuration paramter (and not a hardware description parameter), we cannot make it part of the Device Tree binding, so we'd better remove it from the platform_data as well. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: remove useless backpointer from mv_xor_chan to mv_xor_deviceThomas Petazzoni2012-11-201-1/+0
| | | | | | | The backpointer from mv_xor_chan to mv_xor_device is now useless, get rid of it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: rename mv_xor_private to mv_xor_deviceThomas Petazzoni2012-11-201-2/+2
| | | | | | | | | | | | | Now that mv_xor_device is no longer used to designate the per-channel DMA devices, use it know to designate the XOR engine themselves (currently composed of two XOR channels). So, now we have the nice organization where: - mv_xor_device represents each XOR engine in the system - mv_xor_chan represents each XOR channel of a given XOR engine Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: merge mv_xor_device and mv_xor_chanThomas Petazzoni2012-11-201-19/+6
| | | | | | | | | | | | | | | | | | | Even though the DMA engine infrastructure has support for multiple channels per device, the mv_xor driver registers one DMA engine device for each channel, because the mv_xor channels inside the same XOR engine have different capabilities, and the DMA engine infrastructure only allows to express capabilities at the DMA engine device level. The mv_xor driver has therefore been registering one DMA engine device and one DMA engine channel for each XOR channel since its introduction in the kernel. However, it kept two separate internal structures, mv_xor_device and mv_xor_channel, which didn't make a lot of sense since there was a 1:1 mapping between those structures. This patch gets rid of this duplication, and merges everything into the mv_xor_chan structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: in mv_xor_device, rename 'common' to 'dmadev'Thomas Petazzoni2012-11-201-1/+1
| | | | | | | | | The mv_xor_device structure embeds a 'struct dma_device', which is named 'common', a not very meaningful name. Rename it to 'dmadev', which will help avoid confusions later as we merge the mv_xor_device and mv_xor_chan structures together. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: in mv_xor_chan, rename 'common' to 'dmachan'Thomas Petazzoni2012-11-201-1/+1
| | | | | | | | | The mv_xor_chan structure embeds a 'struct dma_chan', which is named 'common', a not very meaningful name. Rename it to 'dmachan', which will help avoid confusions later as we merge the mv_xor_device and mv_xor_chan structures together. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: get rid of the pdev pointer in mv_xor_deviceThomas Petazzoni2012-11-201-1/+0
| | | | | | | It was only used in places where we could get the 'struct device *' pointer through a different way. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: remove unused id field in mv_xor_device structureThomas Petazzoni2012-11-201-1/+0
| | | | Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: rename many symbols to remove the 'shared' wordThomas Petazzoni2012-11-201-2/+2
| | | | | | | The 'shared' word no longer makes sense in a number of places as we renamed the 'mv_xor_shared' driver to 'mv_xor'. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: allow channels to be registered directly from the main deviceThomas Petazzoni2012-11-201-3/+5
| | | | | | | | | | | Extend the XOR engine driver (currently called "mv_xor_shared") so that XOR channels can be passed in the platform_data structure, and be registered from there. This will allow the users of the driver to be converted to the single platform_driver variant of the mv_xor driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* dma: mv_xor: do not use pool_size from platform_data within the driverThomas Petazzoni2012-11-201-0/+1
| | | | | | | | | | | The driver currently pokes into the platform_data structure during its normal operation to get the pool_size value. Poking into the platform_data structure is not nice when moving to the Device Tree, so this commit adds a new pool_size field in the mv_xor_device structure, which gets initialized at ->probe() time. The driver then uses this field instead of the platform_data. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* ARM: Orion: XOR: Add support for clkAndrew Lunn2012-05-081-0/+1
| | | | | | | | | Some orion platforms can gate the XOR driver clock. If the clock exisits, unable/disable it as appropriate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* dmaengine: move last completed cookie into generic dma_chan structureRussell King - ARM Linux2012-03-131-2/+0
| | | | | | | | | | | | | | | Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: mv_xor: remove write-only is_complete_cookieRussell King - ARM Linux2012-03-131-1/+0
| | | | | | | | | | | | | mv_xor's is_complete_cookie is only ever written to, but never read. This is silly, remove the write-only structure member. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* mv_xor: implement a private tx_listDan Williams2009-09-081-2/+2
| | | | | | | | | Drop mv_xor's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* dmaengine: DMA engine driver for Marvell XOR engineSaeed Bishara2008-07-081-0/+183
The XOR engine found in Marvell's SoCs and system controllers provides XOR and DMA operation, iSCSI CRC32C calculation, memory initialization, and memory ECC error cleanup operation support. This driver implements the DMA engine API and supports the following capabilities: - memcpy - xor - memset The XOR engine can be used by DMA engine clients implemented in the kernel, one of those clients is the RAID module. In that case, I observed 20% improvement in the raid5 write throughput, and 40% decrease in the CPU utilization when doing array construction, those results obtained on an 5182 running at 500Mhz. When enabling the NET DMA client, the performance decreased, so meanwhile it is recommended to keep this client off. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 01:20:41 +0000