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* Merge tag 'arm-drivers-5.13' of ↵Linus Torvalds2021-04-261-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Updates for SoC specific drivers include a few subsystems that have their own maintainers but send them through the soc tree: TEE/OP-TEE: - Add tracepoints around calls to secure world Memory controller drivers: - Minor fixes for Renesas, Exynos, Mediatek and Tegra platforms - Add debug statistics to Tegra20 memory controller - Update Tegra bindings and convert to dtschema ARM SCMI Firmware: - Support for modular SCMI protocols and vendor specific extensions - New SCMI IIO driver - Per-cpu DVFS The other driver changes are all from the platform maintainers directly and reflect the drivers that don't fit into any other subsystem as well as treewide changes for a particular platform. SoCFPGA: - Various cleanups contributed by Krzysztof Kozlowski Mediatek: - add MT8183 support to mutex driver - MMSYS: use per SoC array to describe the possible routing - add MMSYS support for MT8183 and MT8167 - add support for PMIC wrapper with integrated arbiter - add support for MT8192/MT6873 Tegra: - Bug fixes to PMC and clock drivers NXP/i.MX: - Update SCU power domain driver to keep console domain power on. - Add missing ADC1 power domain to SCU power domain driver. - Update comments for single global power domain in SCU power domain driver. - Add i.MX51/i.MX53 unique id support to i.MX SoC driver. NXP/FSL SoC driver updates for v5.13 - Add ACPI support for RCPM driver - Use generic io{read,write} for QE drivers after performance optimized for PowerPC - Fix QBMAN probe to cleanup HW states correctly for kexec - Various cleanup and style fix for QBMAN/QE/GUTS drivers OMAP: - Preparation to use devicetree for genpd - ti-sysc needs iorange check improved when the interconnect target module has no control registers listed - ti-sysc needs to probe l4_wkup and l4_cfg interconnects first to avoid issues with missing resources and unnecessary deferred probe - ti-sysc debug option can now detect more devices - ti-sysc now warns if an old incomplete devicetree data is found as we now rely on it being complete for am3 and 4 - soc init code needs to check for prcm and prm nodes for omap4/5 and dra7 - omap-prm driver needs to enable autoidle retention support for omap4 - omap5 clocks are missing gpmc and ocmc clock registers - pci-dra7xx now needs to use builtin_platform_driver instead of using builtin_platform_driver_probe for deferred probe to work Raspberry Pi: - Fix-up all RPi firmware drivers so as for unbind to happen in an orderly fashion - Support for RPi's PoE hat PWM bus Qualcomm - Improved detection for SCM calling conventions - Support for OEM specific wifi firmware path - Added drivers for SC7280/SM8350: RPMH, LLCC< AOSS QMP" * tag 'arm-drivers-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) soc: aspeed: fix a ternary sign expansion bug memory: mtk-smi: Add device-link between smi-larb and smi-common memory: samsung: exynos5422-dmc: handle clk_set_parent() failure memory: renesas-rpc-if: fix possible NULL pointer dereference of resource clk: socfpga: fix iomem pointer cast on 64-bit soc: aspeed: Adapt to new LPC device tree layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout ipmi: kcs: aspeed: Adapt to new LPC DTS layout ARM: dts: Remove LPC BMC and Host partitions dt-bindings: aspeed-lpc: Remove LPC partitioning soc: fsl: enable acpi support in RCPM driver soc: qcom: mdt_loader: Detect truncated read of segments soc: qcom: mdt_loader: Validate that p_filesz < p_memsz soc: qcom: pdr: Fix error return code in pdr_register_listener firmware: qcom_scm: Fix kernel-doc function names to match firmware: qcom_scm: Suppress sysfs bind attributes firmware: qcom_scm: Workaround lack of "is available" call on SC7180 firmware: qcom_scm: Reduce locking section for __get_convention() firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers" ...
| * dmaengine: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCsKrzysztof Kozlowski2021-03-231-1/+1
| | | | | | | | | | | | | | | | | | ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the 32-bit ARM drivers to rely on new symbol. Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | dmaengine: idxd: fix wq cleanup of WQCFG registersDave Jiang2021-04-123-18/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | A pre-release silicon erratum workaround where wq reset does not clear WQCFG registers was leaked into upstream code. Use wq reset command instead of blasting the MMIO region. This also address an issue where we clobber registers in future devices. Fixes: da32b28c95a7 ("dmaengine: idxd: cleanup workqueue config after disabling") Reported-by: Shreenivaas Devarajan <shreenivaas.devarajan@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161824330020.881560.16375921906426627033.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: idxd: clear MSIX permission entry on shutdownDave Jiang2021-04-123-9/+34
| | | | | | | | | | | | | | | | | | | | | | Add disabling/clearing of MSIX permission entries on device shutdown to mirror the enabling of the MSIX entries on probe. Current code left the MSIX enabled and the pasid entries still programmed at device shutdown. Fixes: 8e50d392652f ("dmaengine: idxd: Add shared workqueue support") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161824457969.882533.6020239898682672311.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: plx_dma: add a missing put_device() on error pathDan Carpenter2021-04-121-7/+11
| | | | | | | | | | | | | | | | | | | | | | Add a missing put_device(&pdev->dev) if the call to dma_async_device_register(dma); fails. Fixes: 905ca51e63be ("dmaengine: plx-dma: Introduce PLX DMA engine PCI driver skeleton") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/YFnq/0IQzixtAbC1@mwanda Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: tegra20: Fix runtime PM imbalance on errorDinghao Liu2021-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | pm_runtime_get_sync() will increase the runtime PM counter even it returns an error. Thus a pairing decrement is needed to prevent refcount leak. Fix this by replacing this API with pm_runtime_resume_and_get(), which will not change the runtime PM counter on error. Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210409082805.23643-1-dinghao.liu@zju.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: Fix a double free in dma_async_device_registerLv Yunlong2021-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the first list_for_each_entry() macro of dma_async_device_register, it gets the chan from list and calls __dma_async_device_channel_register (..,chan). We can see that chan->local is allocated by alloc_percpu() and it is freed chan->local by free_percpu(chan->local) when __dma_async_device_channel_register() failed. But after __dma_async_device_channel_register() failed, the caller will goto err_out and freed the chan->local in the second time by free_percpu(). The cause of this problem is forget to set chan->local to NULL when chan->local was freed in __dma_async_device_channel_register(). My patch sets chan->local to NULL when the callee failed to avoid double free. Fixes: d2fb0a0438384 ("dmaengine: break out channel registration") Signed-off-by: Lv Yunlong <lyl2019@mail.ustc.edu.cn> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20210331014458.3944-1-lyl2019@mail.ustc.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: dw: Make it dependent to HAS_IOMEMAndy Shevchenko2021-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Some architectures do not provide devm_*() APIs. Hence make the driver dependent on HAVE_IOMEM. Fixes: dbde5c2934d1 ("dw_dmac: use devm_* functions to simplify code") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20210324141757.24710-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: idxd: fix wq size store permission stateDave Jiang2021-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | WQ size can only be changed when the device is disabled. Current code allows change when device is enabled but wq is disabled. Change the check to detect device state. Fixes: c52ca478233c ("dmaengine: idxd: add configuration component of driver") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161782558755.107710.18138252584838406025.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: idxd: fix opcap sysfs attribute outputDave Jiang2021-04-121-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | The operation capability register is 256bits. The current output only prints out the first 64bits. Fix to output the entire 256bits. The current code omits operation caps from IAX devices. Fixes: c52ca478233c ("dmaengine: idxd: add configuration component of driver") Reported-by: Lucas Van <lucas.van@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161645624963.2003736.829798666998490151.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: idxd: Fix clobbering of SWERR overflow bit on writebackDave Jiang2021-04-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Current code blindly writes over the SWERR and the OVERFLOW bits. Write back the bits actually read instead so the driver avoids clobbering the OVERFLOW bit that comes after the register is read. Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161352082229.3511254.1002151220537623503.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx: dpdma: Fix race condition in done IRQLaurent Pinchart2021-03-161-1/+2
| | | | | | | | | | | | | | | | | | | | The active descriptor pointer is accessed from different contexts, including different interrupt handlers, and its access must be protected by the channel's lock. This wasn't done in the done IRQ handler. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210307040629.29308-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx: dpdma: Fix descriptor issuing on video groupLaurent Pinchart2021-03-161-11/+17
|/ | | | | | | | | | | When multiple channels are part of a video group, the transfer is triggered only when all channels in the group are ready. The logic to do so is incorrect, as it causes the descriptors for all channels but the last one in a group to not being pushed to the hardware. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210307040629.29308-2-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'dmaengine-5.12-rc1' of ↵Linus Torvalds2021-02-2328-5627/+2707
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "We have couple of drivers removed a new driver and bunch of new device support and few updates to drivers for this round. New drivers/devices: - Intel LGM SoC DMA driver - Actions Semi S500 DMA controller - Renesas r8a779a0 dma controller - Ingenic JZ4760(B) dma controller - Intel KeemBay AxiDMA controller Removed: - Coh901318 dma driver - Zte zx dma driver - Sirfsoc dma driver Updates: - mmp_pdma, mmp_tdma gained module support - imx-sdma become modern and dropped platform data support - dw-axi driver gained slave and cyclic dma support" * tag 'dmaengine-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (58 commits) dmaengine: dw-axi-dmac: remove redundant null check on desc dmaengine: xilinx_dma: Alloc tx descriptors GFP_NOWAIT dmaengine: dw-axi-dmac: Virtually split the linked-list dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMAC dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Support burst residue granularity dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: simplify descriptor management dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: ti: k3-psil: optimize struct psil_endpoint_config for size ...
| * dmaengine: dw-axi-dmac: remove redundant null check on descColin Ian King2021-02-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pointer desc is being null checked twice, the second null check is redundant because desc has not been re-assigned between the checks. Remove the redundant second null check on desc. Fixes: ef6fb2d6f1ab ("dmaengine: dw-axi-dmac: simplify descriptor management") Signed-off-by: Colin Ian King <colin.king@canonical.com> Tested-by: Sia Jee Heng <jee.heng.sia@intel.com> Reviewed-by: Sia Jee Heng <jee.heng.sia@intel.com> Addresses-Coverity: ("Logically dead code") Link: https://lore.kernel.org/r/20210203134652.22618-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: Alloc tx descriptors GFP_NOWAITRichard Fitzgerald2021-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | Use GFP_NOWAIT allocation in xilinx_dma_alloc_tx_descriptor(). This is necessary for compatibility with ALSA, which calls dmaengine_prep_dma_cyclic() from an atomic context. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210129170800.31857-1-rf@opensource.cirrus.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Virtually split the linked-listSia Jee Heng2021-02-012-20/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE. It shall helps the DMA clients to create size-optimized linked-list for the controller. However, there are certain situations where DMA client might not be abled to benefit from the dma_get_max_seg_size() if the segment size can't meet the nature of the DMA client's operation. In the case of ALSA operation, ALSA application and driver expecting to run in a period of larger than 10ms regardless of the bit depth. With this large period, there is a strong request to split the linked-list in the AxiDMA driver. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-18-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Set constraint to the Max segment sizeSia Jee Heng2021-02-012-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can handle the AxiDMA limitation. Without supporting DMA constraint the default Max segment size reported by dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-17-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registersSia Jee Heng2021-02-011-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers programming. Intel KeemBay AxiDMA supports data transfer between device to memory and memory to device operations. This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO size of 8bits and 16bits to perform memory to device data transfer operation. 0-padding functionality is provided to avoid pre-processing of data on CPU. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-16-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshakeSia Jee Heng2021-02-011-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Intel KeemBay AxiDMA device handshake programming. Device handshake number passed in to the AxiDMA shall be written to the Intel KeemBay AxiDMA hardware handshake registers before DMA operations are started. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-15-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA supportSia Jee Heng2021-02-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Intel KeemBay AxiDMA to the .compatible field. The AxiDMA Apb region will be accessible if the compatible string matches the "intel,kmb-axi-dma". Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-14-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMACSia Jee Heng2021-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | If HAS_IOMEM is not defined and DW_AXI_DMAC is enabled under COMPILE_TEST, the build fails with the following error: dw-axi-dmac-platform.c:(.text+0xc4): undefined reference to `devm_ioremap_resource' Link: https://www.spinics.net/lists/dmaengine/msg25188.html Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Link: https://lore.kernel.org/r/20210125013255.25799-13-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fieldsSia Jee Heng2021-02-011-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Intel KeemBay DMA registers. These registers are required to run data transfer between device to memory and memory to device on Intel KeemBay SoC. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-12-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Support burst residue granularitySia Jee Heng2021-02-012-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report DMA residue. Existing AxiDMA driver only support data transfer between memory to memory operation, therefore reporting DMA residue to the DMA clients is not supported. Reporting DMA residue to the DMA clients is important as DMA clients shall invoke dmaengine_tx_status() to understand the number of bytes been transferred so that the buffer pointer can be updated accordingly. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-10-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Support of_dma_controller_register()Sia Jee Heng2021-02-012-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for of_dma_controller_register() so that DMA clients can pass in device handshake number to the AxiDMA driver. DMA clients shall code the device handshake number in the Device tree. When DMA activities are needed, DMA clients shall invoke OF helper function to pass in the device handshake number to the AxiDMA. Without register to the of_dma_controller_register(), data transfer between memory to device and device to memory operations would failed. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-9-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()Sia Jee Heng2021-02-012-7/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for device_prep_dma_cyclic() callback function to benefit DMA cyclic client, for example ALSA. Existing AxiDMA driver only support data transfer between memory to memory. Data transfer between device to memory and memory to device in cyclic mode would failed if this interface is not supported by the AxiDMA driver. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-8-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Support device_prep_slave_sgSia Jee Heng2021-02-012-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV and DMA_DEV_TO_MEM operations in single mode can be supported. Existing AxiDMA driver only support data transfer between memory to memory. Data transfer between device to memory and memory to device in single mode would failed if this interface is not supported by the AxiDMA driver. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-7-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add device_config operationSia Jee Heng2021-02-012-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device_config() callback function so that the device address can be passed to the dma driver. DMA clients use this interface to pass in the device address to the AxiDMA. Without this interface, data transfer between device to memory and memory to device would failed. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-6-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Add device_synchronize() callbackSia Jee Heng2021-02-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add support for device_synchronize() callback function to sync with dmaengine_terminate_sync(). Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-5-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()Sia Jee Heng2021-02-012-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA memory block is created at driver load time and exist for device lifetime. Move the dma_pool_create() to the ->chan_resource() callback function allowing the DMA memory blocks to be created as needed and destroyed when the channel is freed. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-4-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: simplify descriptor managementSia Jee Heng2021-02-012-71/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify and refactor the descriptor management by removing the redundant Linked List Item (LLI) queue control logic from the AxiDMA driver. The descriptor is split into virtual descriptor and hardware LLI so that only hardware LLI memories are allocated from the DMA memory pool. Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16 descriptors in previous version. This solves the problem where an ALSA driver expects more than 16 DMA descriptors to run. Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lore.kernel.org/r/20210125013255.25799-3-jee.heng.sia@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: INTEL_LDMA should depend on X86Geert Uytterhoeven2021-02-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Lightning Mountain (LGM) DMA controller is only present on Intel Lightning Mountain SoCs. Hence add a dependency on X86, to prevent asking the user about this driver when configuring a kernel without Intel Lightning Mountain platform support. While at it, fix a misspelling of "Intel". Fixes: 32d31c79a1a4fbc4 ("dmaengine: Add Intel LGM SoC DMA support.") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210129131702.2656060-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: rcar-dmac: Add support for R-Car V3UGeert Uytterhoeven2021-02-011-23/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs: 1. The per-channel registers are located in a second register block. Add support for mapping the second block, using the appropriate offsets and stride. 2. The common Channel Clear Register (DMACHCLR) was replaced by a per-channel register. Update rcar_dmac_chan_clear{,_all}() to handle this. As rcar_dmac_init() needs to clear the status before the individual channels are probed, channel index and base address initialization are moved forward. Inspired by a patch in the BSP by Phong Hoang <phong.hoang.wz@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210128084455.2237256-5-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: rcar-dmac: Add helpers for clearing DMA channel statusGeert Uytterhoeven2021-02-011-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the code to clear the status of one or all channels into their own helpers, to prepare for the different handling of the R-Car V3U SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210128084455.2237256-4-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: rcar-dmac: Add for_each_rcar_dmac_chan() helperGeert Uytterhoeven2021-02-011-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper macro for iterating over all DMAC channels, taking into account the channel mask. Use it where appropriate, to simplify code. Restore "reverse Christmas tree" order of local variables while adding a new variable. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210128084455.2237256-3-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: stedma40: fix 'physical' typoBjorn Helgaas2021-01-271-1/+1
| | | | | | | | | | | | | | | | Fix misspelling of "physical". Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20210126205906.2918099-1-helgaas@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: qcom: bam_dma: Manage clocks when controlled_remotely is setThara Gopinath2021-01-271-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When bam dma is "controlled remotely", thus far clocks were not controlled from the Linux. In this scenario, Linux was disabling runtime pm in bam dma driver and not doing any clock management in suspend/resume hooks. With introduction of crypto engine bam dma, the clock is a rpmh resource that can be controlled from both Linux and TZ/remote side. Now bam dma clock is getting enabled during probe even though the bam dma can be "controlled remotely". But due to clocks not being handled properly, bam_suspend generates a unbalanced clk_unprepare warning during system suspend. To fix the above issue and to enable proper clock-management, this patch enables runtim-pm and handles bam dma clocks in suspend/resume hooks if the clock node is present irrespective of controlled_remotely property. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210126211859.790892-1-thara.gopinath@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: idxd: add module parameter to force disable of SVADave Jiang2021-01-261-1/+7
| | | | | | | | | | | | | | | | | | | | | | Add a module parameter that overrides the SVA feature enabling. This keeps the driver in legacy mode even when intel_iommu=sm_on is set. In this mode, the descriptor fields must be programmed with dma_addr_t from the Linux DMA API for source, destination, and completion descriptors. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161134110457.4005461.13171197785259115852.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: mmp_tdma: Allow building as a moduleLubomir Rintel2021-01-261-1/+1
| | | | | | | | | | | | | | | | | | There is no reason the Marvell MMP two-channel audio DMA driver would have to be built-in. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20210121110356.1768635-4-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: mmp_pdma: Allow building as a moduleLubomir Rintel2021-01-261-1/+1
| | | | | | | | | | | | | | | | | | There is no reason the Marvell MMP peripheral DMA driver would have to be built-in. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20210121110356.1768635-3-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: mmp_pdma: Remove mmp_pdma_filter_fn()Lubomir Rintel2021-01-261-14/+0
| | | | | | | | | | | | | | | | It's not used anywhere -- drop it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20210121110356.1768635-2-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: remove coh901318 driverArnd Bergmann2021-01-265-3270/+0
| | | | | | | | | | | | | | | | | | | | | | The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210120131859.2056308-4-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: remove zte zx driverArnd Bergmann2021-01-263-951/+0
| | | | | | | | | | | | | | | | | | | | | | The zte zx platform is getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20210120131859.2056308-3-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: remove sirfsoc driverArnd Bergmann2021-01-263-1178/+0
| | | | | | | | | | | | | | | | | | | | | | The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Cc: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120131859.2056308-2-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: jz4780: Add support for the JZ4760(B)Paul Cercueil2021-01-261-0/+14
| | | | | | | | | | | | | | | | | | | | | | Add support for the JZ4760 and JZ4760B SoCs. Both SoCs have only 5 DMA channels per chip. The JZ4760B introduced the DCKES/DCKEC registers. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120105322.16116-2-paul@crapouillou.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: imx-sdma: Use of_device_get_match_data()Fabio Estevam2021-01-261-10/+1
| | | | | | | | | | | | | | | | Use of_device_get_match_data() to make the code simpler. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210118121549.1625217-2-festevam@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: imx-sdma: Remove platform data supportFabio Estevam2021-01-261-25/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Since 5.10-rc1, i.MX has been converted to a devicetree-only platform. The platform data support in this driver was only used for non-DT platforms. Remove the platform data support as it has no more users. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210118121549.1625217-1-festevam@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: idxd: set DMA channel to be privateDave Jiang2021-01-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DMA_PRIVATE attribute flag to idxd DMA channels. The dedicated WQs are expected to be used by a single client and not shared. While doing NTB testing this mistake was discovered, which prevented ntb_transport from requesting DSA wqs as DMA channels via dma_request_channel(). Reported-by: Srinijia Kambham <srinija.kambham@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Srinijia Kambham <srinija.kambham@intel.com> Fixes: 8f47d1a5e545 ("dmaengine: idxd: connect idxd to dmaengine subsystem") Link: https://lore.kernel.org/r/161074758743.2184057.3388557138816350980.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: qcom: gpi: Remove unneeded semicolonXu Wang2021-01-171-1/+1
| | | | | | | | | | | | | | | | | | fix semicolon.cocci warning: drivers/dma/qcom/gpi.c:1703:2-3: Unneeded semicolon Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20210115100040.33364-1-vulab@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: hsu: disable spurious interruptFerry Toth2021-01-131-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Intel Tangier B0 and Anniedale the interrupt line, disregarding to have different numbers, is shared between HSU DMA and UART IPs. Thus on such SoCs we are expecting that IRQ handler is called in UART driver only. hsu_pci_irq was handling the spurious interrupt from HSU DMA by returning immediately. This wastes CPU time and since HSU DMA and HSU UART interrupt occur simultaneously they race to be handled causing delay to the HSU UART interrupt handling. Fix this by disabling the interrupt entirely. Fixes: 4831e0d9054c ("serial: 8250_mid: handle interrupt correctly in DMA case") Signed-off-by: Ferry Toth <ftoth@exalondelft.nl> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210112223749.97036-1-ftoth@exalondelft.nl Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-18 05:03:56 +0000