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* Merge tag 'dmaengine-6.3-rc1' of ↵Linus Torvalds2023-02-2448-187/+1703
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "A new driver, couple of device support and binding conversion along with bunch of driver updates are the main features of this. New hardware support: - TI AM62Ax controller support - Xilinx xdma driver - Qualcomm SM6125, SM8550, QDU1000/QRU1000 GPI controller Updates: - Runtime pm support for at_xdmac driver - IMX sdma binding conversion to yaml and HDMI audio support - IMX mxs binding conversion to yaml" * tag 'dmaengine-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits) dmaengine: idma64: Update bytes_transferred field dmaengine: imx-sdma: Set DMA channel to be private dmaengine: dw: Move check for paused channel to dwc_get_residue() dmaengine: ptdma: check for null desc before calling pt_cmd_callback dmaengine: dw-axi-dmac: Do not dereference NULL structure dmaengine: idxd: Fix default allowed read buffers value in group dmaengine: sf-pdma: pdma_desc memory leak fix dmaengine: Simplify dmaenginem_async_device_register() function dmaengine: use sysfs_emit() to instead of scnprintf() dmaengine: Make an order in struct dma_device definition dt-bindings: dma: cleanup examples - indentation, lowercase hex dt-bindings: dma: drop unneeded quotes dmaengine: xilinx: xdma: Add user logic interrupt support dmaengine: xilinx: xdma: Add xilinx xdma driver dmaengine: drivers: Use devm_platform_ioremap_resource() dmaengine: at_xdmac: remove empty line dmaengine: at_xdmac: add runtime pm support dmaengine: at_xdmac: align properly function members dmaengine: ppc4xx: Convert to use sysfs_emit()/sysfs_emit_at() APIs dmaengine: sun6i: Set the maximum segment size ...
| * dmaengine: idma64: Update bytes_transferred fieldAman Kumar2023-02-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when 8250 data transfer is done, bytes_tranferred always returns 0 at /sys/devices/pci0000\:\:**.*/dma/dma*chan*/bytes_transferred. In many cases it gives false impression that data is not being trasferred via DMA. So, updating the bytes_transferred field to count the bytes whenever there is data transfer using idma64. Co-developed-by: Srikanth Thokala <srikanth.thokala@intel.com> Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com> Signed-off-by: Aman Kumar <aman.kumar@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230203121702.15725-1-aman.kumar@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: imx-sdma: Set DMA channel to be privateKai-Heng Feng2023-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | If async-tx is loaded before device drivers that requires imx-sdma, the dmaengine_get() routine from async-tx grabs all non-private channels, so devices that require DMA fail to work. So mark imx-sdma with DMA_PRIVATE to avoid such situation. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Link: https://lore.kernel.org/r/20230207045745.1029959-1-kai.heng.feng@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw: Move check for paused channel to dwc_get_residue()Andy Shevchenko2023-02-161-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | Move check for paused channel to dwc_get_residue() and rename the latter to dwc_get_residue_and_status(). This improves data integrity as residue and DMA channel status are set in the same function under the same conditions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230130151747.20704-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ptdma: check for null desc before calling pt_cmd_callbackEric Pilmore2023-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resolves a panic that can occur on AMD systems, typically during host shutdown, after the PTDMA driver had been exercised. The issue was the pt_issue_pending() function is mistakenly assuming that there will be at least one descriptor in the Submitted queue when the function is called. However, it is possible that both the Submitted and Issued queues could be empty, which could result in pt_cmd_callback() being mistakenly called with a NULL pointer. Ref: Bugzilla Bug 216856. Fixes: 6fa7e0e836e2 ("dmaengine: ptdma: fix concurrency issue with multiple dma transfer") Signed-off-by: Eric Pilmore <epilmore@gigaio.com> Link: https://lore.kernel.org/r/20230210075142.58253-1-epilmore@gigaio.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: dw-axi-dmac: Do not dereference NULL structureKees Cook2023-02-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If "vdesc" is NULL, it cannot be used with vd_to_axi_desc(). Leave "bytes" unchanged at 0. Seen under GCC 13 with -Warray-bounds: ../drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: In function 'dma_chan_tx_status': ../drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:329:46: warning: array subscript 0 is outside array bounds of 'struct virt_dma_desc[46116860184273879]' [-Warray-bounds=] 329 | bytes = vd_to_axi_desc(vdesc)->length; | ^~ Fixes: 8e55444da65c ("dmaengine: dw-axi-dmac: Support burst residue granularity") Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230127223623.never.507-kees@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: idxd: Fix default allowed read buffers value in groupFenghua Yu2023-02-162-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently default read buffers that is allowed in a group is 0. grpcfg will be configured to max read buffers that IDXD can support if the group's allowed read buffers value is 0. But 0 is an invalid read buffers value and user may get confused when seeing the invalid initial value 0 through sysfs interface. To show only valid allowed read buffers value and eliminate confusion, directly initialize the allowed read buffers to IDXD's max read buffers. User still can change the value through sysfs interface. Suggested-by: Ramesh Thomas <ramesh.thomas@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Nikhil Rao <nikhil.rao@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230127192855.966929-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: sf-pdma: pdma_desc memory leak fixShravan Chippa2023-02-162-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b2cc5c465c2c ("dmaengine: sf-pdma: Add multithread support for a DMA channel") changed sf_pdma_prep_dma_memcpy() to unconditionally allocate a new sf_pdma_desc each time it is called. The driver previously recycled descs, by checking the in_use flag, only allocating additional descs if the existing one was in use. This logic was removed in commit b2cc5c465c2c ("dmaengine: sf-pdma: Add multithread support for a DMA channel"), but sf_pdma_free_desc() was not changed to handle the new behaviour. As a result, each time sf_pdma_prep_dma_memcpy() is called, the previous descriptor is leaked, over time leading to memory starvation: unreferenced object 0xffffffe008447300 (size 192): comm "irq/39-mchp_dsc", pid 343, jiffies 4294906910 (age 981.200s) hex dump (first 32 bytes): 00 00 00 ff 00 00 00 00 b8 c1 00 00 00 00 00 00 ................ 00 00 70 08 10 00 00 00 00 00 00 c0 00 00 00 00 ..p............. backtrace: [<00000000064a04f4>] kmemleak_alloc+0x1e/0x28 [<00000000018927a7>] kmem_cache_alloc+0x11e/0x178 [<000000002aea8d16>] sf_pdma_prep_dma_memcpy+0x40/0x112 Add the missing kfree() to sf_pdma_free_desc(), and remove the redundant in_use flag. Fixes: b2cc5c465c2c ("dmaengine: sf-pdma: Add multithread support for a DMA channel") Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230120100623.3530634-1-shravan.chippa@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: Simplify dmaenginem_async_device_register() functionAndy Shevchenko2023-02-101-16/+4
| | | | | | | | | | | | | | | | | | | | Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230130112830.52353-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: use sysfs_emit() to instead of scnprintf()Andy Shevchenko2023-02-101-3/+3
| | | | | | | | | | | | | | | | | | | | Follow the advice of the Documentation/filesystems/sysfs.rst and show() should only use sysfs_emit() or sysfs_emit_at() when formatting the value to be returned to user space. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230130111141.59627-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx: xdma: Add user logic interrupt supportLizhi Hou2023-02-101-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xilinx DMA/Bridge Subsystem for PCIe (XDMA) provides up to 16 user interrupt wires to user logic that generate interrupts to the host. This patch adds APIs to enable/disable user logic interrupt for a given interrupt wire index. Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Sonal Santan <sonal.santan@amd.com> Signed-off-by: Max Zhen <max.zhen@amd.com> Signed-off-by: Brian Xu <brian.xu@amd.com> Tested-by: Martin Tuma <tumic@gpxsee.org> Link: https://lore.kernel.org/r/1674145926-29449-3-git-send-email-lizhi.hou@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx: xdma: Add xilinx xdma driverLizhi Hou2023-02-104-0/+1074
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver to enable PCIe board which uses XDMA (the DMA/Bridge Subsystem for PCI Express). For example, Xilinx Alveo PCIe devices. https://www.xilinx.com/products/boards-and-kits/alveo.html The XDMA engine support up to 4 Host to Card (H2C) and 4 Card to Host (C2H) channels. Memory transfers are specified on a per-channel basis in descriptor linked lists, which the DMA fetches from host memory and processes. Events such as descriptor completion and errors are signaled using interrupts. The hardware detail is provided by https://docs.xilinx.com/r/en-US/pg195-pcie-dma/Introduction This driver implements dmaengine APIs. - probe the available DMA channels - use dma_slave_map for channel lookup - use virtual channel to manage dmaengine tx descriptors - implement device_prep_slave_sg callback to handle host scatter gather list - implement device_config to config device address for DMA transfer Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Sonal Santan <sonal.santan@amd.com> Signed-off-by: Max Zhen <max.zhen@amd.com> Signed-off-by: Brian Xu <brian.xu@amd.com> Tested-by: Martin Tuma <tumic@gpxsee.org> Link: https://lore.kernel.org/r/1674145926-29449-2-git-send-email-lizhi.hou@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: drivers: Use devm_platform_ioremap_resource()Tudor Ambarus2023-01-1829-100/+36
| | | | | | | | | | | | | | | | | | | | | | | | platform_get_resource() and devm_ioremap_resource() are wrapped up in the devm_platform_ioremap_resource() helper. Use the helper and get rid of the local variable for struct resource *. We now have a function call less. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20221110152528.7821-1-tudor.ambarus@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: at_xdmac: remove empty lineClaudiu Beznea2023-01-181-1/+0
| | | | | | | | | | | | | | | | Remove empty line. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221117131547.293044-4-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: at_xdmac: add runtime pm supportClaudiu Beznea2023-01-181-15/+202
| | | | | | | | | | | | | | | | | | | | | | | | Add runtime PM support which involves disabling/enabling controller's clocks on runtime PM suspend/resume ops. The runtime suspend/resume is done based on the work submitted to the controller: runtime resume is happening on at_xdmac_start_xfer() and runtime suspend on at_xdmac_tasklet(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221117131547.293044-2-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: at_xdmac: align properly function membersClaudiu Beznea2023-01-181-1/+1
| | | | | | | | | | | | | | | | Align properly function members. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221117131547.293044-3-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ppc4xx: Convert to use sysfs_emit()/sysfs_emit_at() APIsye xingchen2023-01-181-7/+5
| | | | | | | | | | | | | | | | | | | | Follow the advice of the Documentation/filesystems/sysfs.rst and show() should only use sysfs_emit() or sysfs_emit_at() when formatting the value to be returned to user space. Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202212061714501297954@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: sun6i: Set the maximum segment sizeSamuel Holland2023-01-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun6i DMA engine supports segment sizes up to 2^25-1 bytes. This is explicitly stated in newer SoC documentation (H6, D1), and it is implied in older documentation by the 25-bit width of the "bytes left in the current segment" register field. Exposing the real segment size limit (instead of the 64k default) reduces the number of SG list segments needed for a transaction. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20230101193605.50285-1-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ti: k3-udma: remove non-fatal probe deferral logJayesh Choudhary2023-01-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | Drop the non-fatal probe deferral log for getting MSI domain. This makes the kernel log clean and we do not get recurring logs stating: "Failed to get MSI domain". Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20230117051855.29644-1-j-choudhary@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: imx-sdma: support hdmi in sdmaJoy Zou2022-12-281-8/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hdmi script already supported in sdma firmware. So add support hdmi in sdma driver. The design of hdmi script is different from common script such as sai. There is no need to config buffer descriptor for HDMI. The cyclic capability is achieved by the hdmi script. The slave config is so simple, only config src_addr, dts_addr and direction DMA_TRANS_NONE. Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20221115093823.2879128-3-joy.zou@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: HISI_DMA should depend on ARCH_HISIGeert Uytterhoeven2022-12-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | The HiSilicon DMA Engine is only present on HiSilicon SoCs. Hence add a dependency on ARCH_HISI, to prevent asking the user about this driver when configuring a kernel without HiSilicon SoC support. Fixes: e9f08b65250d73ab ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/363a1816d36cd3cf604d88ec90f97c75f604de64.1669044190.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: idxd: Set traffic class values in GRPCFG on DSA 2.0Fenghua Yu2022-12-283-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DSA/IAX 1.0, TC-A and TC-B in GRPCFG are set as 1 to have best performance and cannot be changed through sysfs knobs unless override option is given. The same values should be set on DSA 2.0 as well. Fixes: ea7c8f598c32 ("dmaengine: idxd: restore traffic class defaults after wq reset") Fixes: ade8a86b512c ("dmaengine: idxd: Set defaults for GRPCFG traffic class") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20221209172141.562648-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: idxd: Remove the unused function set_completion_address()Jiapeng Chong2022-12-281-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function set_completion_address is defined in the dma.c file, but not called elsewhere, so remove this unused function. drivers/dma/idxd/dma.c:66:20: warning: unused function 'set_completion_address'. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3416 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20221212033514.5831-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ti: k3-udma: Add support for BCDMA CSI RXVignesh Raghavendra2022-12-281-5/+32
| | | | | | | | | | | | | | | | | | | | BCDMA CSI RX present on AM62Ax SoC is a dedicated DMA for servicing Camera Serial Interface (CSI) IP. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20221213164304.1126945-6-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ti: k3-udma: Add support for DMAs on AM62A SoCVignesh Raghavendra2022-12-281-0/+1
| | | | | | | | | | | | | | | | | | | | AM62A SoC has a BCDMA and PKTDMA as systems DMAs for service various peripherals similar to AM64 SoC. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20221213164304.1126945-5-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ti: k3-psil-am62a: Add AM62Ax PSIL and PDMA dataJai Luthra2022-12-284-1/+200
| | | | | | | | | | | | | | | | | | | | Add PSIL and PDMA data for AM62Ax SoC. Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20221213164304.1126945-4-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: ti: k3-udma: Fix BCDMA for case w/o BCHANVignesh Raghavendra2022-12-281-0/+3
| | | | | | | | | | | | | | | | | | | | Reusing loop iterator fails if BCHAN is not present as iterator is uninitialized Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20221213164304.1126945-3-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | Merge tag 'pci-v6.3-changes' of ↵Linus Torvalds2023-02-248-378/+369
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Rework portdrv shutdown so it disables interrupts but doesn't disable bus mastering, which leads to hangs on Loongson LS7A - Add mechanism to prevent Max_Read_Request_Size (MRRS) increases, again to avoid hardware issues on Loongson LS7A (and likely other devices based on DesignWare IP) - Ignore devices with a firmware (DT or ACPI) node that says the device is disabled Resource management: - Distribute spare resources to unconfigured hotplug bridges at boot-time (not just when hot-adding such a bridge), which makes hot-adding devices to docks work better. Tried this in v6.1 but had to revert for regressions, so try again - Fix root bus issue that dropped resources that happened to end at 0, e.g., [bus 00] PCI device hotplug: - Remove device locking when marking device as disconnected so this doesn't have to wait for concurrent driver bind/unbind to complete - Quirk more Qualcomm bridges that don't fully implement the PCIe Slot Status 'Command Completed' bit Power management: - Account for _S0W of the target bridge in acpi_pci_bridge_d3() so we don't miss hot-add notifications for USB4 docks, Thunderbolt, etc Reset: - Observe delay after reset, e.g., resuming from system sleep, regardless of whether a bridge can suspend to D3cold at runtime - Wait for secondary bus to become ready after a bridge reset Virtualization: - Avoid FLR on some AMD FCH AHCI adapters where it doesn't work - Allow independent IOMMU groups for some Wangxun NICs that prevent peer-to-peer transactions but don't advertise an ACS Capability Error handling: - Configure End-to-End-CRC (ECRC) only if Linux owns the AER Capability - Remove redundant Device Control Error Reporting Enable in the AER service driver since this is already done for all devices during enumeration ASPM: - Add pci_enable_link_state() interface to allow drivers to enable ASPM link state Endpoint framework: - Move dra7xx and tegra194 linkup processing from hard IRQ to threaded IRQ handler - Add a separate lock for endpoint controller list of endpoint function drivers to prevent deadlock in callbacks - Pass events from endpoint controller to endpoint function drivers via callbacks instead of notifiers Synopsys DesignWare eDMA controller driver (acked by Vinod): - Fix CPU vs PCI address issues - Fix source vs destination address issues - Fix issues with interleaved transfer semantics - Fix channel count initialization issue (issue still exists in several other drivers) - Clean up and improve debugfs usage so it will work on platforms with several eDMA devices Baikal T-1 PCIe controller driver: - Set a 64-bit DMA mask Freescale i.MX6 PCIe controller driver: - Add i.MX8MM, i.MX8MQ, i.MX8MP endpoint mode DT binding and driver support Intel VMD host bridge driver: - Add quirk to configure PCIe ASPM and LTR. This is normally done by BIOS, and will be for future products Marvell MVEBU PCIe controller driver: - Mark this driver as broken in Kconfig since bugs prevent its daily usage MediaTek MT7621 PCIe controller driver: - Delay PHY port initialization to improve boot reliability for ZBT WE1326, ZBT WF3526-P, and some Netgear models Qualcomm PCIe controller driver: - Add MSM8998 DT compatible string - Unify MSM8996 and MSM8998 clock orderings - Add SM8350 DT binding and driver support - Add IPQ8074 Gen3 DT binding and driver support - Correct qcom,perst-regs in DT binding - Add qcom_pcie_host_deinit() so the PHY is powered off and regulators and clocks are disabled on late host-init errors Socionext UniPhier Pro5 controller driver: - Clean up uniphier-ep reg, clocks, resets, and their names in DT binding Synopsys DesignWare PCIe controller driver: - Restrict coherent DMA mask to 32 bits for MSI, but allow controller drivers to set 64-bit streaming DMA mask - Add eDMA engine support in both Root Port and Endpoint controllers Miscellaneous: - Remove MODULE_LICENSE from boolean drivers so they don't look like modules so modprobe can complain about them" * tag 'pci-v6.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (86 commits) PCI: dwc: Add Root Port and Endpoint controller eDMA engine support PCI: bt1: Set 64-bit DMA mask PCI: dwc: Restrict only coherent DMA mask for MSI address allocation dmaengine: dw-edma: Prepare dw_edma_probe() for builtin callers dmaengine: dw-edma: Depend on DW_EDMA instead of selecting it dmaengine: dw-edma: Add mem-mapped LL-entries support PCI: Remove MODULE_LICENSE so boolean drivers don't look like modules PCI: hv: Drop duplicate PCI_MSI dependency PCI/P2PDMA: Annotate RCU dereference PCI/sysfs: Constify struct kobj_type pci_slot_ktype PCI: hotplug: Allow marking devices as disconnected during bind/unbind PCI: pciehp: Add Qualcomm quirk for Command Completed erratum PCI: qcom: Add IPQ8074 Gen3 port support dt-bindings: PCI: qcom: Add IPQ8074 Gen3 port dt-bindings: PCI: qcom: Sort compatibles alphabetically PCI: qcom: Fix host-init error handling PCI: qcom: Add SM8350 support dt-bindings: PCI: qcom: Add SM8350 dt-bindings: PCI: qcom-ep: Correct qcom,perst-regs dt-bindings: PCI: qcom: Unify MSM8996 and MSM8998 clock order ...
| * | dmaengine: dw-edma: Depend on DW_EDMA instead of selecting itSerge Semin2023-02-221-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig "select" is discouraged for visible symbols like DW_EDMA because it makes it possible to set DW_EDMA even if DW_EDMA depends on things that are not set (see Documentation/kbuild/kconfig-language.txt). Convert DW_EDMA_PCIE so it depends on DW_EDMA instead of selecting it. There will likely be several future drivers that depend on DW_EDMA, so this uses "if DW_EDMA" to enclose them all rather than repeating "depends on DW_EDMA" for each. [bhelgaas: split to separate patch, commit log] Link: https://lore.kernel.org/r/20230113171409.30470-25-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Add mem-mapped LL-entries supportSerge Semin2023-02-222-41/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the DW eDMA driver only supports the linked lists memory allocated locally with respect to the remote eDMA engine setup. It means the linked lists will be accessible by the CPU via the MMIO space only. If eDMA is embedded into the DW PCIe Root Ports or local Endpoints (which support will be added in subsequent commits) the linked lists are supposed to be allocated in the CPU memory. In that case the LL-entries can be directly accessed, while the former case implies using the MMIO accessors for that. In order to have both cases supported by the driver, the dw_edma_region descriptor should be fixed to contain the MMIO-backed and just memory-based virtual addresses. The linked lists initialization procedure will use one of them depending on the eDMA device nature. If the eDMA engine is embedded into the local DW PCIe Root Port/Endpoint controllers, the list entries will be directly accessed by referencing the corresponding structure fields. Otherwise the MMIO accessors usage will be preserved. Link: https://lore.kernel.org/r/20230113171409.30470-24-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Skip cleanup procedure if no private data foundSerge Semin2023-02-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DW eDMA driver private data is preserved in the passed DW eDMA chip info structure. If the probe fails or for some reason the passed info object doesn't have the private data pointer initialized, halt the DMA device cleanup procedure to prevent system crashes. Link: https://lore.kernel.org/r/20230113171409.30470-23-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Replace chip ID number with device nameSerge Semin2023-02-103-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using an abstract number as the DW eDMA chip identifier isn't practical because there can be more than one DW eDMA controller on the platform. Some may be detected as the PCIe Endpoints, and others may be embedded in DW PCIe Root Port/Endpoint controllers. An abstract number in, for instance, the IRQ handlers list, doesn't give a notion regarding their reference to the particular DMA controller. To preserve the code simplicity and support multi-eDMA platforms, use the parental device name to create the DW eDMA controller name. Link: https://lore.kernel.org/r/20230113171409.30470-22-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Drop DT-region allocationSerge Semin2023-02-101-17/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in allocating additional memory for the data target regions passed to the client drivers. Use the already available structures defined in the dw_edma_chip instance. Note: these regions are unused in normal circumstances since they are specific to the case of eDMA being embedded into the DW PCIe Endpoint and having its CSRs accessible via an Endpoint BAR. This case is only known to be implemented as a part of the Synopsys PCIe Endpoint IP prototype kit. Link: https://lore.kernel.org/r/20230113171409.30470-21-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Use non-atomic io-64 methodsSerge Semin2023-02-101-26/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of splitting 64-bits IOs up into two 32-bits ones, use the existing non-atomic readq()/writeq() functions. By doing so we can discard CONFIG_64BIT #ifdefs from the code. Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Fix readq_ch() return value truncationSerge Semin2023-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, readq_ch() did a 64-bit readq(), but truncated the result by storing it in the u32 "value". Change "value" to u64 to avoid the truncation. Note: the method is currently unused, so the bug hasn't caused any problem so far. Fixes: 04e0a39fc10f ("dmaengine: dw-edma: Add writeq() and readq() for 64 bits architectures") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | dmaengine: dw-edma: Use DMA engine device debugfs subdirectorySerge Semin2023-02-106-29/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all DW eDMA read and write channels are now installed in a framework of a single DMA engine device, move all the DW eDMA-specific debugfs nodes into a ready-to-use DMA-engine debugfs subdirectory. It's created during the DMA-device registration and can be found in the dma_device.dbg_dev_root field. Link: https://lore.kernel.org/r/20230113171409.30470-19-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Join read/write channels into a single deviceSerge Semin2023-02-102-60/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in splitting read/write channels. First of all, eDMA read and write channels belong to one physical controller. Secondly, channel differentiation can be done by filtering and dma_get_slave_caps(). Finally, having these channels handled separately needlessly complicates the code and causes this debugfs warning: debugfs: Directory '1f052000.pcie' with parent 'dmaengine' already present! Join the read/write channels into a single DMA device. Client drivers can choose the correct channel via the DMA slave direction setting. The default value is overridden by the dw_edma_device_caps() callback in accordance with the channel type. Link: https://lore.kernel.org/r/20230113171409.30470-18-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Move eDMA data pointer to debugfs node descriptorSerge Semin2023-02-101-125/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last thing that stops the debugfs part of the eDMA driver from supporting multi-eDMA platforms is keeping the eDMA private data pointer in the static area of the debugfs module. Since the debugfs node descriptors are now heap-allocated, we can freely move that pointer to being preserved in the descriptors. After the debugfs initialization procedure, that pointer will be used in the debugfs files getter to access the common CSRs space and the context CSRs spinlock. So the main part of this change is connected with the debugfs nodes descriptors initialization macros, which aside with already defined prototypes now require to have the DW eDMA private data pointer passed. [bhelgaas: squash in https://lore.kernel.org/r/20230130185101.2883245-1-arnd@kernel.org] Link: https://lore.kernel.org/r/20230113171409.30470-17-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Simplify debugfs context CSRs init procedureSerge Semin2023-01-271-46/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DW eDMA v4.70a and older have the read and write channels context CSRs indirectly accessible, which means CSRs like Channel Control, Xfer size, SAR, DAR and LLP address are accessed at a fixed MMIO address, with their reference to the corresponding channel determined by the Viewport CSR. To have a coherent access to these registers the CSR IOs are supposed to be protected with a spinlock. DW eDMA v4.80a and newer normally have unrolled Read/Write channel context registers, with these CSRs directly mapped in the controller MMIO space. Both normal and viewport-based registers are exposed via debugfs nodes, and the original algorithm was based on the unrolled CSRs mapping and recalculated the viewport addresses when required. This is unscalable (it only supports a platform with a single eDMA since a base address is statically preserved) and also needlessly overcomplicated (it loops over all Rd/Wr context addresses and recalculates the viewport base address on each debugfs node access). Simplify the algorithm by adding the channel ID and its direction fields in the eDMA debugfs node descriptor. These new fields can be used to find a CSR offset in the channel register space. The DW eDMA debugfs node getter will also use them to activate the respective context CSRs viewport before reading data from the specified register. For the unrolled CSR mapping, no spinlock or viewport activation is needed. Note: this replaces some REGISTER() uses with CTX_REGISTER(), which avoids an implicit dependency on a local variable name. The same problem with the rest of the macro will be fixed in the next commit. Link: https://lore.kernel.org/r/20230113171409.30470-16-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Rename debugfs dentry variables to 'dent'Serge Semin2023-01-271-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we are about to add the eDMA channels direction support to the debugfs module it will be confusing to have both the debugfs directory and the channels direction short names used in the same code. Rename the debugfs dentry 'dir' variables to 'dent' to prevent confusion. Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230113171409.30470-15-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Convert debugfs descs to being heap-allocatedSerge Semin2023-01-271-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently DW eDMA debugfs node descriptors are allocated on the stack, which won't work for multi-eDMA platforms. As a preparation to supporting multi-eDMA systems, allocate each debugfs node separately. Afterwards we'll add info like Read/Write channel flag, channel ID, DW eDMA private data reference. Note: this conversion is mainly required due to having the legacy DW eDMA controllers with indirect Read/Write channels context CSRs access. If we didn't need to synchronize access to these registers, the debugfs code of the driver would have been much simpler. Link: https://lore.kernel.org/r/20230113171409.30470-14-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Add dw_edma prefix to debugfs nodes descriptorSerge Semin2023-01-271-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other local names include a "dw_edma" prefix. Add a "dw_edma" prefix to the debugfs_entries structure, too, so it won't be confused with global debugfs things. Link: https://lore.kernel.org/r/20230113171409.30470-13-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Stop checking debugfs_create_*() return valueSerge Semin2023-01-271-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debugfs_create_*() functions never return NULL, so checking their return value for NULL is pointless. Secondly, the debugfs subsystem is designed to be as simple as possible, so if one of the debugfs_create_*() method in a hierarchy fails, the following methods should silently return the passed erroneous parental dentry. Finally, the code should work no matter whether anything debugfs-related fails. To make code simpler and debugfs-independent, stop checking the debugfs_create_*() return values. If the debugfs file system is unavailable, skip the debugfs node initialization altogether to preserve some memory space. Link: https://lore.kernel.org/r/20230113171409.30470-12-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Drop unnecessary debugfs reg castsSerge Semin2023-01-271-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debugfs_entries structure declared in dw-edma-v0-debugfs.c contains the debugfs node register address. The address is declared as dma_addr_t type, but is cast to "void *". Change the type to "void __iomem *" and drop the unnecessary casts. Link: https://lore.kernel.org/r/20230113171409.30470-11-Sergey.Semin@baikalelectronics.ru Fixes: 305aebeff879 ("dmaengine: Add Synopsys eDMA IP version 0 debugfs support") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Drop chancnt initializationSerge Semin2023-01-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA engine core manages dma_device.chancnt itself, e.g., in dma_async_device_register(). DMA device drivers should not initialize chancnt because it causes the wrong number of channels printed in the device summary. Drop the dw-edma chancnt initialization. Link: https://lore.kernel.org/r/20230113171409.30470-10-Sergey.Semin@baikalelectronics.ru Fixes: e63d79d1ffcd ("dmaengine: Add Synopsys eDMA IP core driver") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Add PCI bus address getter to the remote EP glue driverSerge Semin2023-01-271-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synopsys PCIe Endpoint IP prototype kit can be attached via any PCI host controller, including one where the PCI bus address space is different from the CPU address space. Therefore, we need to make sure the source and destination addresses of the DMA slave devices are converted to the PCI bus address space; otherwise DMA transactions may cause memory corruption. Add a new dw_edma_pcie_address() interface to perform this translation by using pcibios_resource_to_bus(). Link: https://lore.kernel.org/r/20230113171409.30470-9-Sergey.Semin@baikalelectronics.ru Fixes: 41aaff2a2ac0 ("dmaengine: Add Synopsys eDMA IP PCIe glue-logic") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Add CPU to PCI bus address translationSerge Semin2023-01-271-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 9575632052ba ("dmaengine: make slave address physical"), the source and destination addresses of the DMA slave device have been converted to physical addresses in the CPU address space. It's the DMA device driver's responsibility to convert them to the DMA bus address space. In case of the DW eDMA device, the source or destination peripheral (slave) devices reside in PCI bus space. Thus we need to perform the PCI Host/Endpoint windows- based (i.e. DT "ranges" property) address translation; otherwise the eDMA transactions won't work as expected (or can be even harmful) if the CPU and PCI address spaces don't match. Note 1: Even though the DMA interleaved template has both source and destination addresses declared as dma_addr_t, only the CPU memory range should be mapped to be seen by the DMA device since it's a subject of the DMA getting towards the system side. The device part must not be mapped since the slave device resides in the PCI bus space, which isn't affected by IOMMUs or iATU translations. DW PCIe eDMA generates corresponding MWr/MRd TLPs on its own. Note 2: This functionality is mainly required for the remote eDMA setup since the CPU address must be manually translated into the PCI bus space before being written to LLI.{SAR,DAR}. If eDMA is embedded in the locally accessible DW PCIe Root Port/Endpoint, software-based translation isn't required since hardware will translate it via the Outbound iATU as long as the DMA_BYPASS flag is cleared. If DMA_BYPASS is set or there is no Outbound iATU entry that contains the SAR or DAR (for Read and Write channel respectively), there won't be any translation performed but DMA will proceed with the corresponding source/destination address as-is. Link: https://lore.kernel.org/r/20230113171409.30470-8-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Fix invalid interleaved xfers semanticsSerge Semin2023-01-271-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interleaved DMA transfer support added by 85e7518f42c8 ("dmaengine: dw-edma: Add device_prep_interleave_dma() support") seems contradictory to what the DMA engine defines. The next conditional statements: if (!xfer->xfer.il->numf) return NULL; if (xfer->xfer.il->numf > 0 && xfer->xfer.il->frame_size > 0) return NULL; mean that numf can't be zero and frame_size must always be zero, otherwise the transfer won't be executed. Furthermore, the transfer execution method takes the frame size from the dma_interleaved_template.sgl[] array for each frame. That array in accordance with [1] is supposed to be of dma_interleaved_template.frame_size size, which as we discovered before the code expects to be zero. So judging by the dw_edma_device_transfer() implementation, the method implies the dma_interleaved_template.sgl[] array being of dma_interleaved_template.numf size, which is wrong. Since the dw_edma_device_transfer() method doesn't permit dma_interleaved_template.frame_size being non-zero, the multi-chunk interleaved transfer turns to be unsupported even though the code implies having it supported. Add fully functioning support of interleaved DMA transfers. First of all, dma_interleaved_template.frame_size is supposed to be greater or equal to one thus having at least simple linear chunked frames. Secondly, we can create a walk-through over all the chunks and frames by initializing the number of the eDMA burst transactions as a multiple of dma_interleaved_template.numf and dma_interleaved_template.frame_size and getting the frame_size-modulo of the iteration step as an index of the dma_interleaved_template.sgl[] array. [1] include/linux/dmaengine.h: doc struct dma_interleaved_template Link: https://lore.kernel.org/r/20230113171409.30470-7-Sergey.Semin@baikalelectronics.ru Fixes: 85e7518f42c8 ("dmaengine: dw-edma: Add device_prep_interleave_dma() support") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Don't permit non-inc interleaved xfersSerge Semin2023-01-271-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DW eDMA controller always increments both source and destination addresses. Permitting DMA interleaved transfers with no src_inc/dst_inc flags set may lead to unexpected behaviour for the device users. Terminate interleaved transfers if at least one of the dma_interleaved_template.{src_inc,dst_inc} flag is initialized to "false". Note that in addition, we need to increase the source and destination addresses after each iteration. Link: https://lore.kernel.org/r/20230113171409.30470-6-Sergey.Semin@baikalelectronics.ru Fixes: 85e7518f42c8 ("dmaengine: dw-edma: Add device_prep_interleave_dma() support") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | dmaengine: dw-edma: Fix missing src/dst address of interleaved xfersSerge Semin2023-01-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interleaved DMA transfer support was added by 85e7518f42c8 ("dmaengine: dw-edma: Add device_prep_interleave_dma() support"), but depending on the selected channel, either source or destination address are left uninitialized which was obviously wrong. Initialize the destination address of the eDMA burst descriptors for DEV_TO_MEM interleaved operations and the source address for MEM_TO_DEV operations. Link: https://lore.kernel.org/r/20230113171409.30470-5-Sergey.Semin@baikalelectronics.ru Fixes: 85e7518f42c8 ("dmaengine: dw-edma: Add device_prep_interleave_dma() support") Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-11 06:18:54 +0000