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[ Upstream commit 61e749d7e1627d375156553ea0ae83c4f6bb5a9b ]
The CrystalCove GPIO irqchip doesn't have irq_set_wake callback defined
so we should set IRQCHIP_SKIP_SET_WAKE for it or it would cause an irq
desc's wake_depth unbalanced warning during system resume phase from the
gpio_keys driver, which is the driver for the power button of the ASUS
T100 laptop.
Signed-off-by: Aaron Lu <aaron.lu@intel.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
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commit e733a2fb8cbcff0747108cb529ffb4e4a00465ac upstream.
The CrystalCove GPIO chip has can_sleep set so its demultiplexed irqs
will have IRQ_NESTED_THREAD flag set, thus we should use the nested
version handle_nested_irq in CrystalCove's irq handler instead of
handle_generic_irq, or the following warning will be hit and the
functionality is lost:
[ 4089.639554] Hardware name: ASUSTeK COMPUTER INC. T100TA/T100TA, BIOS T100TA.313 08/13/2014
[ 4089.639564] 00000002 00000000 c24fbdf4 c16e0257 c24fbe38 c24fbe28 c105390c c18ec480
[ 4089.639596] c24fbe54 00000048 c18f8e3b 00000295 c10a60fc 00000295 c10a60fc f4464540
[ 4089.639626] f446459c c278ad40 c24fbe40 c1053974 00000009 c24fbe38 c18ec480 c24fbe54
[ 4089.639656] Call Trace:
[ 4089.639685] [<c16e0257>] dump_stack+0x41/0x52
[ 4089.639707] [<c105390c>] warn_slowpath_common+0x8c/0xc0
[ 4089.639727] [<c10a60fc>] ? irq_nested_primary_handler+0x2c/0x30
[ 4089.639744] [<c10a60fc>] ? irq_nested_primary_handler+0x2c/0x30
[ 4089.639763] [<c1053974>] warn_slowpath_fmt+0x34/0x40
[ 4089.639781] [<c10a60fc>] irq_nested_primary_handler+0x2c/0x30
[ 4089.639800] [<c10a5c56>] handle_irq_event_percpu+0x76/0x190
[ 4089.639818] [<c1461570>] ? regmap_format_10_14_write+0x30/0x30
[ 4089.639836] [<c1464f4c>] ? _regmap_bus_raw_write+0x4c/0x70
[ 4089.639854] [<c10a5da1>] handle_irq_event+0x31/0x50
[ 4089.639872] [<c10a83eb>] handle_simple_irq+0x4b/0x70
[ 4089.639889] [<c10a5384>] generic_handle_irq+0x24/0x40
[ 4089.639908] [<c1366d87>] crystalcove_gpio_irq_handler+0xa7/0xc0
[ 4089.639927] [<c10a85a7>] handle_nested_irq+0x77/0x190
[ 4089.639947] [<c1469801>] regmap_irq_thread+0x1b1/0x360
[ 4089.639966] [<c10a6ae8>] irq_thread_fn+0x18/0x30
[ 4089.639983] [<c10a6906>] irq_thread+0xf6/0x110
[ 4089.640001] [<c10a6ad0>] ? irq_finalize_oneshot.part.30+0x1b0/0x1b0
[ 4089.640019] [<c10a6b50>] ? irq_forced_thread_fn+0x50/0x50
[ 4089.640037] [<c10a6810>] ? irq_thread_check_affinity+0xc0/0xc0
[ 4089.640054] [<c106f389>] kthread+0xa9/0xc0
[ 4089.640074] [<c16e6401>] ret_from_kernel_thread+0x21/0x30
[ 4089.640091] [<c106f2e0>] ? kthread_create_on_node+0x110/0x110
[ 4089.640105] ---[ end trace dca7946ad31eba7d ]---
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=90521
Reported-and-tested-by: Brian Loften <bloften80@gmail.com>
Signed-off-by: Aaron Lu <aaron.lu@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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The virtual GPIO introduced in ACPI table of Baytrail-T based system is
used to solve a problem under Windows. We do not have such problems
under Linux so we do not actually need them. But we have to tell GPIO
library that the Crystal Cove GPIO chip has this many GPIO pins or the
common GPIO handler will refuse any access to those high number GPIO
pins, which will resulted in a failure evaluation of every ACPI control
method that is used to turn on/off power resource and/or report sensor
temperatures.
Signed-off-by: Aaron Lu <aaron.lu@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
[changed vgpio number from 0x5e to 94]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some drivers accidentally still use the return value from
gpiochip_remove(). Get rid of them so we can simplify this function
and get rid of the return value.
Cc: Abdoulaye Berthe <berthe.ab@gmail.com>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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drivers/gpio/gpio-crystalcove.c: In function 'crystalcove_gpio_dbg_show':
drivers/gpio/gpio-crystalcove.c:286:3: error: implicit declaration of function 'seq_printf'
seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Devices based on Intel SoC products such as Baytrail have a Power
Management IC. In the PMIC there are subsystems for voltage regulation,
A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is
called Crystal Cove.
This patch adds support for the GPIO function in Crystal Cove.
Signed-off-by: Yang, Bin <bin.yang@intel.com>
Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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