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path: root/drivers/gpio/gpio-tegra186.c
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* Merge tag 'pinctrl-v6.5-1' of ↵Linus Torvalds2023-06-301-5/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time New drivers: - Tegra234 support - Qualcomm IPQ5018 support - Intel Meteor Lake-S support - Qualcomm SDX75 subdriver - Qualcomm SPMI-based PM8953 support Improvements: - Fix up support for GPIO3 on the AXP209 - Push-pull drive configuration support for the AT91 PIO4 - Fix misc non-urgent bugs in the AMD driver - Misc non-urgent improved error handling - Misc janitorial and minor improvements" * tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: cherryview: Drop goto label pinctrl: baytrail: invert if condition pinctrl: baytrail: add warning for BYT_VAL_REG retrieval failure pinctrl: baytrail: reduce scope of spinlock in ->dbg_show() hook pinctrl: tegra: avoid duplicate field initializers dt-bindings: pinctrl: qcom,sdx65-tlmm: add pcie_clkreq function pinctrl: mlxbf3: remove broken Kconfig 'select' pinctrl: spear: Remove unused of_gpio.h inclusion pinctrl: lantiq: Remove unused of_gpio.h inclusion pinctrl: at91-pio4: check return value of devm_kasprintf() pinctrl: microchip-sgpio: check return value of devm_kasprintf() pinctrl: freescale: Fix a memory out of bounds when num_configs is 1 pinctrl: intel: refine ->irq_set_type() hook pinctrl: intel: refine ->set_mux() hook pinctrl: baytrail: Use str_hi_lo() helper lib/string_choices: Add str_high_low() helper lib/string_helpers: Split out string_choices.h lib/string_helpers: Add missing header files to MAINTAINERS database pinctrl: npcm7xx: Add missing check for ioremap pinctrl:sunplus: Add check for kmalloc ...
| * gpio: tegra186: Check PMC driver status before any requestPrathamesh Shete2023-06-091-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the PMC device is disabled, probing of the Tegra186 GPIO driver fails because the IRQ domain that is registered by the PMC driver is not found. The PMC IRQ domain is only used for wake-up and does not impact GPIO functionality in general. Therefore, if the PMC device is disabled, skip looking up the PMC IRQ domain to allow the GPIO driver to be probed. Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230607113104.11761-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | gpio: tegra186: Check GPIO pin permission before access.Prathamesh Shete2023-05-261-0/+78
|/ | | | | | | | | | | | | | | | This change checks if we have the necessary permission to access the GPIO. For devices that have support for virtualisation we need to check both the TEGRA186_GPIO_VM_REG and the TEGRA186_GPIO_SCR_REG registers. For device that do not have virtualisation support for GPIOs we only need to check the TEGRA186_GPIO_SCR_REG register. Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
* gpio: tegra186: Add Tegra234 hte supportDipen Patel2023-04-261-0/+1
| | | | | | | | | | To enable timestamp support for the Tegra234, has_gte variable needs to be set true. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: remove unneeded loop in tegra186_gpio_init_route_mapping()Tom Rix2023-02-021-22/+18
| | | | | | | | | | | Reviewing the j loop over num_irqs_per_bank, in the code previous to the fixes: commit, every j was used. now only when j == 0. If only j == 0 is used, there is no need for the loop. Fixes: 210386804745 ("gpio: tegra186: Support multiple interrupts per bank") Signed-off-by: Tom Rix <trix@redhat.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
* gpio: tegra186: add Tegra234 PMC compatible in GPIO driverPrathamesh Shete2023-01-301-0/+1
| | | | | | | | | | | Using this patch we are adding PMC compatible string for Tegra234 in GPIO driver so the IRQ hierarchy can be set. Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
* gpio: tegra186: Add missing header(s)Andy Shevchenko2022-10-241-1/+2
| | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: Remove dynamic allocation from populate_parent_alloc_arg()Marc Zyngier2022-07-101-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpiolib is unique in the way it uses intermediate fwspecs when feeding an interrupt specifier to the parent domain, as it relies on the populate_parent_alloc_arg() callback to perform a dynamic allocation. This is pretty inefficient (we free the structure almost immediately), and the only reason this isn't a stack allocation is that our ThunderX friend uses MSIs rather than a FW-constructed structure. Let's solve it by providing a new type composed of the union of a struct irq_fwspec and a msi_info_t, which satisfies both requirements. This allows us to use a stack allocation, and we can move the handful of users to this new scheme. Also perform some additional cleanup, such as getting rid of the stub versions of the irq_domain_translate_*cell helpers, which are never used when CONFIG_IRQ_DOMAIN_HIERARCHY isn't selected. Tested on a Tegra186. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Daniel Palmer <daniel@thingy.jp> Cc: Romain Perier <romain.perier@gmail.com> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Robert Richter <rric@kernel.org> Cc: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220707182314.66610-2-prabhakar.mahadev-lad.rj@bp.renesas.com
* Merge tag 'hte/for-5.19-rc1' of ↵Linus Torvalds2022-06-051-1/+80
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux Pull hardware timestamping subsystem from Thierry Reding: "This contains the new HTE (hardware timestamping engine) subsystem that has been in the works for a couple of months now. The infrastructure provided allows for drivers to register as hardware timestamp providers, while consumers will be able to request events that they are interested in (such as GPIOs and IRQs) to be timestamped by the hardware providers. Note that this currently supports only one provider, but there seems to be enough interest in this functionality and we expect to see more drivers added once this is merged" [ Linus Walleij mentions the Intel PMC in the Elkhart and Tiger Lake platforms as another future timestamp provider ] * tag 'hte/for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: timestamp: Correct id path dt-bindings: Renamed hte directory to timestamp hte: Uninitialized variable in hte_ts_get() hte: Fix off by one in hte_push_ts_ns() hte: Fix possible use-after-free in tegra_hte_test_remove() hte: Remove unused including <linux/version.h> MAINTAINERS: Add HTE Subsystem hte: Add Tegra HTE test driver tools: gpio: Add new hardware clock type gpiolib: cdev: Add hardware timestamp clock type gpio: tegra186: Add HTE support gpiolib: Add HTE support dt-bindings: Add HTE bindings hte: Add Tegra194 HTE kernel provider drivers: Add hardware timestamp engine (HTE) subsystem Documentation: Add HTE subsystem guide
| * gpio: tegra186: Add HTE supportDipen Patel2022-05-041-1/+80
| | | | | | | | | | | | | | | | | | | | | | | | Tegra194 AON GPIO controller with the use of its internal hardware timestamping engine (HTE), also known as GTE, can timestamp GPIO lines through system counter. This patch implements enable/disable callbacks for the GPIO controller. In enable call, it will set timestamp function bit and GPIO line rising/falling edges in the config register. In disable call, it restores the state. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | gpio: tegra186: Make the irqchip immutableMarc Zyngier2022-04-191-9/+23
|/ | | | | | | | | | | Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419141846.598305-5-maz@kernel.org
* gpio: tegra186: Add IRQ per bank for Tegra241Akhil R2022-03-071-0/+2
| | | | | | | | | Add the number of interrupts per bank for Tegra241 (Grace) to fix the probe failure. Fixes: d1056b771ddb ("gpio: tegra186: Add support for Tegra241") Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* gpio: tegra186: Fix chip_data type confusionMarc Zyngier2022-02-191-4/+10
| | | | | | | | | | | | | | | | | | | | | | | The tegra186 GPIO driver makes the assumption that the pointer returned by irq_data_get_irq_chip_data() is a pointer to a tegra_gpio structure. Unfortunately, it is actually a pointer to the inner gpio_chip structure, as mandated by the gpiolib infrastructure. Nice try. The saving grace is that the gpio_chip is the first member of tegra_gpio, so the bug has gone undetected since... forever. Fix it by performing a container_of() on the pointer. This results in no additional code, and makes it possible to understand how the whole thing works. Fixes: 5b2b135a87fc ("gpio: Add Tegra186 support") Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20220211093904.1112679-1-maz@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: Add support for Tegra241Akhil R2021-12-231-0/+52
| | | | | | | | | | Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra241 (Grace). While the programming model remains the same, the number of pins has slightly changed. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* gpio: Get rid of duplicate of_node assignment in the driversAndy Shevchenko2021-12-171-1/+0
| | | | | | | | | | | | | | GPIO library does copy the of_node from the parent device of the GPIO chip, there is no need to repeat this in the individual drivers. Remove these assignment all at once. For the details one may look into the of_gpio_dev_init() implementation. While at it, remove duplicate parent device assignment where it is the case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-By: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* gpio: tegra186: Add support for Tegra234Prathamesh Shete2021-12-171-0/+76
| | | | | | | | | | | Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra234. While the programming model remains the same, the number of pins has slightly changed. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* gpio: tegra186: Support multiple interrupts per bankThierry Reding2021-09-221-7/+41
| | | | | | | | | | | | | | Tegra194 and later support more than a single interrupt per bank. This is primarily useful for virtualization but can also be helpful for more fine-grained CPU affinity control. To keep things simple for now, route all pins to the first interrupt. For backwards-compatibility, support old device trees that specify only one interrupt per bank by counting the interrupts at probe time. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* gpio: tegra186: Force one interrupt per bankThierry Reding2021-09-221-6/+62
| | | | | | | | | | | | Newer chips support up to 8 interrupts per bank, which can be useful to balance the load and decrease latency. However, it also required a very complicated interrupt routing to be set up. To keep things simple for now, ensure that a single interrupt per bank is enforced, even if all possible interrupts are described in device tree. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
* Merge tag 'gpio-updates-for-v5.15' of ↵Linus Torvalds2021-09-071-6/+24
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "We mostly have various improvements and refactoring all over the place but also some interesting new features - like the virtio GPIO driver that allows guest VMs to use host's GPIOs. We also have a new/old GPIO driver for rockchip - this one has been split out of the pinctrl driver. Summary: - new driver: gpio-virtio allowing a guest VM running linux to access GPIO lines provided by the host - split the GPIO driver out of the rockchip pin control driver - add support for a new model to gpio-aspeed-sgpio, refactor the driver and use generic device property interfaces, improve property sanitization - add ACPI support to gpio-tegra186 - improve the code setting the line names to support multiple GPIO banks per device - constify a bunch of OF functions in the core GPIO code and make the declaration for one of the core OF functions we use consistent within its header - use software nodes in intel_quark_i2c_gpio - add support for the gpio-line-names property in gpio-mt7621 - use the standard GPIO function for setting the GPIO names in gpio-brcmstb - fix a bunch of leaks and other bugs in gpio-mpc8xxx - use generic pm callbacks in gpio-ml-ioh - improve resource management and PM handling in gpio-mlxbf2 - modernize and improve the gpio-dwapb driver - coding style improvements in gpio-rcar - documentation fixes and improvements - update the MAINTAINERS entry for gpio-zynq - minor tweaks in several drivers" * tag 'gpio-updates-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (35 commits) gpio: mpc8xxx: Use 'devm_gpiochip_add_data()' to simplify the code and avoid a leak gpio: mpc8xxx: Fix a potential double iounmap call in 'mpc8xxx_probe()' gpio: mpc8xxx: Fix a resources leak in the error handling path of 'mpc8xxx_probe()' gpio: viperboard: remove platform_set_drvdata() call in probe gpio: virtio: Add missing mailings lists in MAINTAINERS entry gpio: virtio: Fix sparse warnings gpio: remove the obsolete MX35 3DS BOARD MC9S08DZ60 GPIO functions gpio: max730x: Use the right include gpio: Add virtio-gpio driver gpio: mlxbf2: Use DEFINE_RES_MEM_NAMED() helper macro gpio: mlxbf2: Use devm_platform_ioremap_resource() gpio: mlxbf2: Drop wrong use of ACPI_PTR() gpio: mlxbf2: Convert to device PM ops gpio: dwapb: Get rid of legacy platform data mfd: intel_quark_i2c_gpio: Convert GPIO to use software nodes gpio: dwapb: Read GPIO base from gpio-base property gpio: dwapb: Unify ACPI enumeration checks in get_irq() and configure_irqs() gpiolib: Deduplicate forward declaration in the consumer.h header MAINTAINERS: update gpio-zynq.yaml reference gpio: tegra186: Add ACPI support ...
| * gpio: tegra186: Add ACPI supportAkhil R2021-08-051-6/+24
| | | | | | | | | | | | | | | | | | | | Add ACPI module ID to probe the driver from the ACPI based bootloader firmware. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | gpio: Bulk conversion to generic_handle_domain_irq()Marc Zyngier2021-08-121-6/+3
|/ | | | | | | | | | | Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
* Merge tag 'gpio-updates-for-v5.14' of ↵Linus Torvalds2021-07-051-13/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "One new driver, support for new models in existing ones, dt-bindings conversions for several modules and improvements all over the place. Summary: - new driver for the IDT 79RC3243x GPIO controller - device tree bindings coversion to YAML for the following drivers: gpio-rk3328-grf, gpio-omap, gpio-davinci, gpio-zynq, gpio-stp, gpio-pcf857x - cleanup of probe functions in many drivers from Alexandru Ardelean, mostly dropping unnecessary calls to platform_set_drvdata() and removing error messages where none are needed (handled by the subsystem already) - several improvements to the core gpiolib and the sysfs interface code from Andy Shevchenko - conversion of the gpio-xilinx driver to using the bitmap API + improvements of suspend/resume handling + minor tweaks - convert the gpio-stmpe to using devres helpers exclusively in probe for improved robustness - updates for the generic gpio-regmap driver - updates for the gpio-dwapb driver - support for a new model in gpio-pca953x - cleanups in gpio-tegra186, gpio-104-idio-16, gpio-mxs & gpio-xgene - slight code refactoring of the gpio-zynq driver - documentation fixes from Mauro Carvalho Chehab - a bunch of minor tweaks and improvements all over the place" * tag 'gpio-updates-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (57 commits) docs: driver-api: gpio: using-gpio.rst: avoid using ReST :doc:`foo` markup dt-bindings: gpio: pcf857x: Convert to json-schema gpio: mxs: Prefer unsigned int to bare use of unsigned dt-bindings: gpio: stp: convert to json-schema dt-bindings: gpio: zynq: convert bindings to YAML dt-bindings: gpio: gpio-davinci: Convert to json-schema gpio: pca953x: Add support for the On Semi pca9655 gpio: gpio-xilinx: update on suspend and resume calls gpio: zynq: Check return value of irq_get_irq_data gpio: zynq: Check return value of pm_runtime_get_sync gpio: zynq: use module_platform_driver to simplify the code gpio: idt3243x: Fix return value check in idt_gpio_probe() MAINTAINERS: update ti,omap-gpio.yaml reference dt-bindings: gpio: Add devicetree binding for IDT 79RC32434 GPIO controller gpio: Add support for IDT 79RC3243x GPIO controller gpio: regmap: move drvdata to config data gpio-dwapb: Drop unused headers and sort the rest gpio: gpio-regmap: Use devm_add_action_or_reset() gpio: dwapb: Switch to use fwnode_irq_get() gpio: dwapb: Drop redundant check in dwapb_irq_set_type() ...
| * gpio: gpio-tegra186: remove platform_set_drvdata() + cleanup probeAlexandru Ardelean2021-05-231-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The platform_set_drvdata() call is only useful if we need to retrieve back the private information. Since the driver doesn't do that, it's not useful to have it. If this is removed, we can also just do a direct return on devm_gpiochip_add_data(). We don't need to print that this call failed as there are other ways to log/see this during probe. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
| * gpio: gpio-tegra186: remove empty remove hookAlexandru Ardelean2021-05-231-6/+0
| | | | | | | | | | | | | | | | | | The tegra186_gpio_remove hook simply does a return 0. Not defining it yields pretty much the same result. So, this can be removed. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | gpio: tegra186: Don't set parent IRQ affinityJon Hunter2021-05-121-11/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hotplugging CPUs on Tegra186 and Tegra194 errors such as the following are seen ... IRQ63: set affinity failed(-22). IRQ65: set affinity failed(-22). IRQ66: set affinity failed(-22). IRQ67: set affinity failed(-22). Looking at the /proc/interrupts the above are all interrupts associated with GPIOs. The reason why these error messages occur is because there is no 'parent_data' associated with any of the GPIO interrupts and so tegra186_irq_set_affinity() simply returns -EINVAL. To understand why there is no 'parent_data' it is first necessary to understand that in addition to the GPIO interrupts being routed to the interrupt controller (GIC), the interrupts for some GPIOs are also routed to the Tegra Power Management Controller (PMC) to wake up the system from low power states. In order to configure GPIO events as wake events in the PMC, the PMC is configured as IRQ parent domain for the GPIO IRQ domain. Originally the GIC was the IRQ parent domain of the PMC and although this was working, this started causing issues once commit 64a267e9a41c ("irqchip/gic: Configure SGIs as standard interrupts") was added, because technically, the GIC is not a parent of the PMC. Commit c351ab7bf2a5 ("soc/tegra: pmc: Don't create fake interrupt hierarchy levels") fixed this by severing the IRQ domain hierarchy for the Tegra GPIOs and hence, there may be no IRQ parent domain for the GPIOs. The GPIO controllers on Tegra186 and Tegra194 have either one or six interrupt lines to the interrupt controller. For GPIO controllers with six interrupts, the mapping of the GPIO interrupt to the controller interrupt is configurable within the GPIO controller. Currently a default mapping is used, however, it could be possible to use the set affinity callback for the Tegra186 GPIO driver to do something a bit more interesting. Currently, because interrupts for all GPIOs are have the same mapping and any attempts to configure the affinity for a given GPIO can conflict with another that shares the same IRQ, for now it is simpler to just remove set affinity support and this avoids the above warnings being seen. Cc: <stable@vger.kernel.org> Fixes: c4e1f7d92cd6 ("gpio: tegra186: Set affinity callback to parent") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: convert comma to semicolonZheng Yongjun2021-02-151-1/+1
| | | | | | | Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: Set affinity callback to parentLinus Walleij2020-12-041-0/+11
| | | | | | | | | | | | | | | This assigns the .irq_set_affinity to the parent callback. I assume the Tegra186 is an SMP system so this would be beneficial. I used the pattern making the hirerarchy tolerant for missing parent as in Marc's earlier patch. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20201117213351.249668-2-linus.walleij@linaro.org
* gpio: tegra186: Allow optional irq parent callbacksMarc Zyngier2020-10-101-2/+13
| | | | | | | | | Make the tegra186 GPIO driver resistent to variable depth interrupt hierarchy, which we are about to introduce. No functionnal change yet. Signed-off-by: Marc Zyngier <maz@kernel.org>
* gpio: tegra186: export MODULE_DEVICE_TABLEMian Yousaf Kaukab2020-05-051-0/+1
| | | | | | | Export MODULE_DEVICE_TABLE since the driver can be built as a module. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1Thierry Reding2020-03-271-0/+8
| | | | | | | | | | | | | | | | | | | | | The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for PCIe controller 5 on Tegra194. When this controller is configured in endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint driver. Typically the mode programming of these pins (GPIO vs. SFIO) is performed by early boot firmware to ensure that the configuration is consistent. However, the GG.0 and GG.1 pins are part of a special power partition that is not enabled during early boot, and hence the early boot firmware cannot program these pins to be GPIOs (they are SFIO by default). Adding them as pin ranges for the pin controller allows the pin controller to be involved when these pins are requested as GPIOs and allows the proper programming to take place. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-4-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: Add support for pin rangesThierry Reding2020-03-271-0/+56
| | | | | | | | | | Add support for Tegra SoC generations to specify a list of pin ranges that map GPIOs to ranges of pins in the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-3-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpiolib: Add support for the irqdomain which doesn't use irq_fwspec as argKevin Hao2020-01-151-3/+10
| | | | | | | | | | | | Some gpio's parent irqdomain may not use the struct irq_fwspec as argument, such as msi irqdomain. So rename the callback populate_parent_fwspec() to populate_parent_alloc_arg() and make it allocate and populate the specific struct which is needed by the parent irqdomain. Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://lore.kernel.org/r/20200114082821.14015-3-haokexin@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: Add debounce supportThierry Reding2019-11-121-0/+38
| | | | | | | | The GPIO controller found on Tegra186 and later supports debouncing for inputs for up to 255 ms. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: Program interrupt route mappingThierry Reding2019-11-121-0/+46
| | | | | | | | | | | | | | The controls for the GG port on Tegra194 resides in the power partition of the C5 PCIe controller and its interrupt route mapping can therefore not be programmed by early boot firmware along with that of the other ports. Detect this generically by looking at which controls have already been locked down using the security registers and fill in default values for controls that are unlocked. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: Derive register offsets from bank/portThierry Reding2019-11-121-95/+100
| | | | | | | | | The register offsets for a given bank and port can be easily derived from the bank and port indices. Update the port descriptors to list only the bank and port numbers to simplify this. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* Merge remote-tracking branch 'driver-core/driver-core-next' into gpio/for-nextBartosz Golaszewski2019-11-121-3/+1
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| * gpio: tegra186: use devm_platform_ioremap_resource_byname()Bartosz Golaszewski2019-11-051-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191022084318.22256-9-brgl@bgdev.pl Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | gpio: Use new GPIO_LINE_DIRECTIONMatti Vaittinen2019-11-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's hard for occasional GPIO code reader/writer to know if values 0/1 equal to IN or OUT. Use defined GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT to help them out. NOTE - for gpio-amd-fch and gpio-bd9571mwv: This commit also changes the return value for direction get to equal 1 for direction INPUT. Prior this commit these drivers might have returned some other positive value but 1 for INPUT. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com> Acked-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | gpio: tegra186: Implement wake event supportThierry Reding2019-10-051-18/+79
|/ | | | | | | | | | | | | | | | | The GPIO controller doesn't have any controls to enable the system to wake up from low power states based on activity on GPIO pins. An extra hardware block that is part of the power management controller (PMC) contains these controls. In order for the GPIO controller to be able to cooperate with the PMC, obtain a reference to the PMC's IRQ domain and make it a parent to the GPIO controller's IRQ domain. This way the PMC gets an opportunity to program the additional registers required to enable wakeup sources on suspend. Based on additional work by Bitan Biswas <bbiswas@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20191002144502.156393-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 233Thomas Gleixner2019-06-191-4/+1
| | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 6 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.720704315@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* gpio: tegra186: Use TEGRA186_ prefix for GPIO namesThierry Reding2019-02-141-35/+35
| | | | | | | | | | The new prefix allows the GPIOs to be uniquely identified on a per-chip basis, which makes it easier to distinguish Tegra186 specific GPIOs from those of later chips such as Tegra194 which supports a very different set of GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* gpio: tegra186: Rename flow variable to typeThierry Reding2018-12-141-3/+3
| | | | | | | | | | The IRQ core code refers to the interrupt type by that name, whereas the term flow is almost never used. Some GPIO controllers use the term flow_type, but it is most consistent to just go with the IRQ core terminology. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: Add support for Tegra194Mikko Perttunen2018-07-021-0/+74
| | | | | | | | Add support for the Tegra194 GPIO bank configuration. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: tegra186: Remove tegra186_gpio_lock_classAxel Lin2017-11-131-3/+0
| | | | | | | | | This is no longer required after commit 959bc7b22bd2 ("gpio: Automatically add lockdep keys") Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: Add Tegra186 supportThierry Reding2017-11-081-0/+623
Tegra186 has two GPIO controllers that are largely register compatible between one another but are completely different from the controller found on earlier generations. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 03:48:37 +0000