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path: root/drivers/gpu/drm/amd/display/dc/dc_stream.h
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* Revert "drm/amd/display: Disable DWB frame capture to emulate oneshot"Alex Hung2023-10-131-4/+0
| | | | | | | | | | | This reverts commit 77a66faaccc0455fe30e326e9a997aec8d0abed4. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Adjust code style for hw_sequencer.hAurabindo Pillai2023-10-041-6/+0
| | | | | | | | | | | [Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable DWB frame capture to emulate oneshotAlex Hung2023-10-031-0/+4
| | | | | | | | | | | | | [WHY] drm_writeback requires to capture exact one frame in each writeback call. [HOW] frame_capture is disabled after each writeback is completed. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove unused display_content_supportJoshua Ashton2023-09-201-1/+0
| | | | | | | | | | | | | | | | | This was never filled in and thus never truly used. Checking the EDID for content_type support is not required for sending the avi infoframe packet. v2: - rebase to amd-staging-drm-next Reviewed-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Hook up 'content type' property for HDMIJoshua Ashton2023-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Implements the 'content type' property for HDMI connectors. Verified by checking the avi infoframe on a connected TV. This also simplifies a lot of the code in that area as well, there were a lot of temp variables doing very little and unnecessary logic that was quite confusing. It is not necessary to check for support in the EDID before sending a 'content type' value in the avi infoframe also. v2: - rebase to amd-staging-drm-next - mark CRTC state for reset if content_type differs Reviewed-by: Harry Wentland <harry.wentland@amd.com> (v1) Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor edp power controlIan Chen2023-08-301-1/+0
| | | | | | | | | | | | | | | [Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add control flag to dc_stream_state to skip eDP BL off/link offMax Tseng2023-06-091-0/+1
| | | | | | | | | | Add control flag to dc_stream_state to skip eDP BL off/link off. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Max Tseng <max.tseng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Check Vactive for VRR active for FPO + VactiveAlvin Lee2023-06-091-0/+2
| | | | | | | | | | | | | | | | | | | [Description] - For FPO + Vactive cases, we rely on the Vactive display to be at it's nominal refresh rate because the Vactive pipe may not necessarily assert P-State allow while it's in VBLANK - For cases where the Vactive display has a stretched VBLANK due to VRR, we could underflow when trying to complete an FPO + Vactive MCLK switch because the FPO display has limited VBLANK time in waiting for the Vactive display to assert P-State allow naturally - Block FPO + Vactive if the Vactive display has VRR active (variable or fixed) Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add extra dc odm debug optionsDmytro Laktyushkin2023-04-181-0/+5
| | | | | | | | | | | [Why & How] Add options for dc odm debug. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add FAMS validation before trying to use itRodrigo Siqueira2023-04-181-0/+1
| | | | | | | | | | | To ensure that FAMS can be used, DC must check if there is VRR support. This commit adds the required configuration to ensure FAMS can be executed in the target system. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Reduce SubVP + DRR stretch marginAlvin Lee2023-04-181-1/+1
| | | | | | | | | | | | | | [Description] - Having excessively large margin causes failure in the static schedulability check in some cases for SubVP + DRR - 100us of DRR margin is sufficient based on a weeks worth of stress testing on different display configs Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use per pipe P-State force for FPOAlvin Lee2023-03-311-0/+1
| | | | | | | | | | | | | | | | | | | [Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive * Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable AdaptiveSync in DC interfaceSung Joon Kim2023-01-241-0/+2
| | | | | | | | | | | | | | | | | [why] Start enabling AdaptiveSync feature on Linux environment. [how] Adding AdaptiveSync support in DC layer - building AdaptiveSync info_packets - adjusting the v_startup parameter Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement multiple secure displayAlan Liu2022-12-151-2/+1
| | | | | | | | | | | | | | | | | [Why] Current secure display only work with single display, now make it work with multiple displays. [How] Create secure_display_context for each crtc instance to store its own Region of Interest (ROI) information. v2: squash in warning fix (Alex) Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)Alvin Lee2022-11-291-0/+11
| | | | | | | | | | | | | | | | [Description] - When entering into a SubVP config that requires a minimal transition we need to retain phantom pipes and also restore the mall config - This is because the min transition will remove phantom pipes from the context (shallow copy) and not restore it's original state - This is just a workaround, and needs a proper fix Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add margin on DRR vblank start for subvpAlvin Lee2022-11-231-1/+1
| | | | | | | | | | | | | [Description] - Add margin for HUBP "jitter" for SubVp + DRR case - Also do a min transition even if MPO is added on a non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR) Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Expand kernel doc for DCRodrigo Siqueira2022-10-271-0/+11
| | | | | | | | | | This commit adds extra documentation for elements related to FAMs. Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Drop struct crc_region and reuse struct rectAlan Liu2022-10-271-1/+1
| | | | | | | | | | | | | | | | [Why] reuse struct rect rather than adding a new struct. [How] - Userspace keeps inputting x_start, y_start, x_end, y_end - We translate data to x, y, width, height in code flow to store - translate back to x_start, y_start, x_end, y_end before programming HW Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement secure display on DCN21Alan Liu2022-10-271-4/+4
| | | | | | | | | | | | | | | | | | | | [Why] Porting secure display feature from DCN10 to DCN21. Support single display for now and will extend to multiple displays. [How] - use workqueue to offload works for dmub or dmcu firmware - after receiving ROI update from userspace, set skip_frame_cnt to 1 - refactor amdgpu_dm_crtc_handle_crc_window_irq() - disable PSR before activating secure_display on a crtc - check if secure_display is activated before enabling psr - only work for single display for now. Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Include surface of unaffected streamsRodrigo Siqueira2022-10-241-0/+4
| | | | | | | | | | | | | | | | The commit stream function does not include surfaces of unaffected streams, which may lead to some blank screens during mode change in some edge cases. This commit adds surfaces of unaffected streams followed by kernel-doc for documenting some of the fields that participate in this change. v2: squash in kerneldoc warning fix (Alex) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Co-developed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove interface for periodic interrupt 1Aric Cyr2022-09-291-4/+2
| | | | | | | | | | | | | | | [why] Only a single VLINE interrupt is available so interface should not expose the second one which is used by DMU firmware. [how] Remove references to periodic_interrupt1 and VLINE1 from DC interfaces. Reviewed-by: Jaehyun Chung <jaehyun.chung@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: HDMI ODM Combine Policy CorrectionSaaem Rizvi2022-08-251-2/+0
| | | | | | | | | | | | | | | | | | | | [WHY] Reprogramming the stream despite no changes in ODM combine mode. Reprogramming the stream would cause intermittent black screen on display which could only be recovered through enable/disable sequence. [HOW] Fixed bug where we detected a change in ODM combine mode despite ODM combine mode being disabled. Also removed code which required stream to be reprogrammed once a change in ODM combine mode was noticed. Lastly we do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32, therefore we never want to change its ODM policy. Reviewed-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove unused struct freesync_contextMaíra Canal2022-07-281-8/+0
| | | | | | | | | All references to struct freesync_context were removed, so remove the struct freesync_context itself and its entry on struct dc_stream_state. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Maíra Canal <mairacanal@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Indicate stream change on ODM changeChris Park2022-07-051-0/+2
| | | | | | | | | | | | | | | | | | | | [Why] With ODM policy 2 to 1, there exists a new use case scenario where stream content is unchanged, but ODM may be used. When this happens, the stream needs to be committed with a new pipe setting. This did not happen due to stream change detection logic not accounting for ODM. [How] Set ODM flag in stream and commit stream when change in ODM has been detected due to policy change. Reviewed-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add minimal pipe split transition stateRodrigo Siqueira2022-07-051-0/+18
| | | | | | | | | | | | | | | | | | | [WHY?] When adding/removing a plane to some configurations, unsupported pipe programming can occur when moving to a new plane. Such cases include pipe split on multi-display, with MPO, and/or ODM. [HOW?] Add a safe transistion state that minimizes pipe usage before programming new configuration. When adding a plane, the current state has the least pipes required so it is applied without splitting. This must be applied prior to updating the plane_state for seamless transition. When removing a plane, the new state has the least pieps required so it is applied without splitting. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add SubVP required codeAlvin Lee2022-07-051-4/+0
| | | | | | | | | | | | | | | | | | | This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Revert "drm/amd/display: turn DPMS off on connector unplug"Wayne Lin2022-06-211-1/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit 3c4d55c9b9becedd8d31a7c96783a364533713ab. Revert the commit because: - It's incomplete of the function dm_set_dpms_off() for mst case. For stream sinks whithin the same mst topology, they share the same dc_link. dm_set_dpms_off() tries to update one mst stream only which is incomplete. - Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add vrr_active_variable to dc_stream_updateHarry VanZyllDeJong2022-06-141-0/+1
| | | | | | | | | | | | | | | [WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Harry VanZyllDeJong <harry.vanzylldejong@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Pass vrr mode to dcnFelipe Clark2022-06-141-0/+1
| | | | | | | | | | | | | [WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Felipe Clark <Felipe.Clark@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Adding VTEM to dcAhmad Othman2022-06-141-0/+2
| | | | | | | | | | | | | | | [Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add support for HF-VSIFAhmad Othman2022-06-141-0/+2
| | | | | | | | | | | | | | | | | [Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Firmware assisted MCLK switch and FSFelipe Clark2022-06-141-1/+2
| | | | | | | | | | | | | | | | | | | [WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Felipe Clark <felipe.clark@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: combine dirty rectangles in DMUB FWDavid Zhang2022-06-061-0/+5
| | | | | | | | | | | | | | | | | [why] In PSR-SU design, the DMUB FW handles the combination of multiple dirty rectangles. [how] - create DC dmub update dirty rectangle helper which sends the dirty rectangles per pipe from DC to DMUB, and DMUB FW will handle to combine the dirty RECTs - call the helper from DC commit plane update function. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai2022-06-031-0/+21
| | | | | | | | | | | | [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Keep track of DSC packed PPSIlya Bakoulin2022-04-251-1/+1
| | | | | | | | | | | [Why] Store current packed PPS data in dc_stream_state for future use. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add odm seamless boot supportDuncan Ma2022-04-121-0/+1
| | | | | | | | | | | | | | | | | | | [WHY] Implement changes to transition from Pre-OS odm to Post-OS odm support. Seamless boot case is also considered. [HOW] Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has odm enabled. Reset odm and det size when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Duncan Ma <Duncan.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add support for zstate during extended vblankGabe Teeger2022-03-251-0/+2
| | | | | | | | | | | | | | | | | | | | | [why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible. [how] When we enter freesync, a full update is triggered and the new vtotal with extra lines is passed to dml in a stream update. The time gained from extra vblank lines is calculated in microseconds. We allow zstate entry if the time gained is greater than 5 ms, which is the current policy. Furthermore, an optimized value for min_dst_y_next_start is calculated and written to its register. When exiting freesync, another full update is triggered and default values are restored. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add function to get the pipe from the stream contextLeo (Hanghong) Ma2022-03-151-0/+2
| | | | | | | | | | | | | | | [Why] We need a helper function in dc to grab the pipe from the stream context. [How] Add it. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Drop DCN for DP2.x logicWenjing Liu2022-01-251-6/+0
| | | | | | | | | | | | | | | [Why & How] DCN guard is not necessary for DP2.x relevant logic. Drop them. v2: squash in fix for misplaced #endif (Alex) Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DP 2.0 MST DC SupportFangzhi Zuo2021-10-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | [Why] configure/call DC interface for DP2 mst support. This is needed to make DP2 mst work. [How] - add encoding type, logging, mst update/reduce payload functions Use the link encoding to determine the DP type (1.4 or 2.0) and add a flag to dc_stream_update to determine whether to increase/reduce payloads. v2: * add DP_UNKNOWN_ENCODING handling Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: "Lin, Wayne" <Wayne.Lin@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211025223825.301703-4-lyude@redhat.com
* drm/amd/display: Return last used DRR VTOTAL from DCJayendran Ramani2021-06-081-0/+4
| | | | | | | | | | | [How] Add call to get the last used VTOTAL from DC Signed-off-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: disable desktop VRR when using older flip modelhvanzyll2021-05-271-0/+3
| | | | | | | | | | | | | | | | | [WHY] OS uses older flip model which does not work with desktop VRR causing memory allocations at the wrong IRQ level. [HOW] Checks added to flip model to verify model is 2.2 or greater when doing any of the desktop VRR checks for full updates. This prevents full updates when VRR changes until a mode change. Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove unused flag from stream stateMikita Lipski2021-04-151-1/+0
| | | | | | | | | | | | | [why & how] Removing unused DSC flag which is incorrect and is not used. We are only using stream->timing.flags.DSC for DSC's current state. Stream state as an input parameter and should not contain any past status flags. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Acked-by: Bindu Ramamurthy <bindur12@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: New path for enabling DPGWesley Chalmers2021-04-091-0/+12
| | | | | | | | | | | | | | [WHY] We want to make enabling test pattern a part of the stream update code path. This change is the first step towards that goal. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add dynamic link encoder selection.Jimmy Kizito2021-04-091-0/+4
| | | | | | | | | | | | | | | | | | | [Why] Some display endpoints may be programmably mapped to compatible link encoders. The assignment of link encoders to links has to be dynamic to accommodate the increased flexibility in comparison to conventional display endpoints. [How] - Add link encoder assignment tracking variables. - Execute link encoder assignment algorithm before enabling link and release link encoders from links once they are disabled. Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Process crc window at DMCUWayne Lin2021-03-051-0/+7
| | | | | | | | | | | | [Why & How] Add additional MCP_SCP commands for starting/stopping updaing crc window at DMCU Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Synchronize displays with different timingsVladimir Stempen2021-02-221-0/+3
| | | | | | | | | | | | | | | [why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/amd/display: reuse current context instead of recreating one"Anson Jacob2021-02-221-1/+2
| | | | | | | | | | | | | | | This reverts commit 8866a67ab86cc0812e65c04f1ef02bcc41e24d68. Reason for revert: This breaks hotplug of HDMI on some systems, resulting in a blank screen. Caused general hangs on boot/hotplugs. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1487 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1492 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211649 Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/amd/display: New path for enabling DPG"Wesley Chalmers2021-02-181-11/+0
| | | | | | | | | | | | | | | | | This reverts commit f8e792dc5c45d306a542b9ee991ae80e1c78e4c5 [Why] We are not implementing the planned new HW sequence for HUBP disable. [How] Revert most related changes to minimize regressions. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: reuse current context instead of recreating oneBhawanpreet Lakha2021-02-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] Currently we discard the current context and recreate it. The current context is what is applied to the HW so we should be re-using this rather than creating a new context. Recreating the context can lead to mismatch between new context and the current context For example: gsl groups get changed when we create a new context this can cause issues in a multi display config (with flip immediate) because we don't align the existing gsl groups in the new and current context. If we reuse the current context the gsl group assignment stays the same. [How] Instead of discarding the current context, we instead just copy the current state and add/remove planes and streams. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-08 13:10:00 +0000