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path: root/drivers/gpu/drm/amd/display/dc/dcn321
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* drm/amd/display: Fix register definitions for DCN32/321Aurabindo Pillai2022-09-131-15/+9
| | | | | | | | | | | | | [Why & How] Fix the instatiation sequence for MPC registers and add a few other missing register definitions that were ommited erroneously when copying them over to enable runtime initialization of reigster offsets for DCN32/321 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add workaround for subvp cursor corruption for DCN32/321Aurabindo Pillai2022-09-131-1/+2
| | | | | | | | | | | | | | | [Why&How] Kernel does not have a means to tell the userspace to use software cursor. Due to lack of this functionality, reducing the max cursor size is the only way to ensure that power savings of Subview port feature is utilized for asics that support it. The workaround could be removed after cursor caching is fixed while a subviewport config is active. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: SW cursor fallback for SubVPAlvin Lee2022-09-131-0/+1
| | | | | | | | | | | | | | [Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Correct I2C register offsetChris Park2022-09-131-1/+8
| | | | | | | | | | | | | | | | | [Why] I2C register name starts with 1, unlike other registers that start with 0. This creates a problem with the new register macro refactoring when I2C HW objects are created in an array. [How] Correct I2C register offset by making a new macro to account for array offset. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: change to runtime initialization for reg offsets for DCN321Aurabindo Pillai2022-08-251-293/+355
| | | | | | | | | | | | | | | | DC was using compile time initialization of register addresses using SR_* macros and their variants. These have been converted to use runtime initialization. The REG_STRUCT macro is a definition that is added to SR_* macros. During initialization, this must be defined before SR_* macros are invoked, which are in turn invoked through various IP initialization macros. Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Include scaling factor for SubVP commandAlvin Lee2022-08-161-1/+1
| | | | | | | | | | | | | [Description] For SubVP scaling cases, we must include the scaling info as part of the cmd. This is required when converting OTG line to HUBP line for the MALL_START_LINE programming. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add 16 lines margin for SubVPAlvin Lee2022-08-101-0/+1
| | | | | | | | | | | | | [Description] SUBVP_START_LINE must be aligned to 2 swaths, so add 16 lines of margin so the start line can be adjusted by up to 16 lines for alignment purposes in FW. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable SubVP by default on DCN32 & DCN321Aurabindo Pillai2022-08-101-1/+1
| | | | | | | | | | | [Why&How] Set the debug options to enable SubVP feature Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add debug option for idle optimizations on cursor updatesAlvin Lee2022-07-251-0/+1
| | | | | | | | | | For optimizations and debug purposes we added an option to exit idle operations on cursor updates. Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable MPC split for DCN32/321Alvin Lee2022-07-251-1/+1
| | | | | | | | | | | Due to CRB, no need to rely on MPC splitting to maximize use of DET anymore. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add dc_ctx to link_enc_create() parametersAurabindo Pillai2022-07-251-0/+1
| | | | | | | | | | | | | | [Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Drop FPU code from dcn321 resourceRodrigo Siqueira2022-07-252-475/+2
| | | | | | | | | | This commit fully move the missing FPU operations from dcn321 resource to dcn321 fpu. It also remove those FPU flags from the Makefile. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Create dcn321_fpu fileRodrigo Siqueira2022-07-252-208/+20
| | | | | | | | | | | The file dcn321_resource has a lot of FPU operations that should be inside the dml folder. This commit introduces the dcn321_fpu file and moves some of the FPU operation functions to this new file. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable GPUVM in IP resource configurationVladimir Stempen2022-07-251-1/+1
| | | | | | | | | | | | | | | | | [Why] VM enabled in IP configuration causes UCLK not reaching DPM0. The expectation for VM enable should be that KMD will indicate to DAL when VM is enabled, then DAL will set the bit accordingly [How] Set gpuvm_enable to zero in DCN3_20 and DCN3_21 resource. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable ODM combine default policyAurabindo Pillai2022-07-081-1/+3
| | | | | | | | | | | | | | | | [Why&How] Output Data Mapping is a power saving feature that allows us to run at reduced DPP and DISP clocks compared to what could be achieved with a single pipe. Set the default policy for single display use case to use 2 to 1 ODM combine. The options are queried by DC and appropriate register programming sequence is initiated to enable this feature. Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: rename hdmi_frl_pcon_supportHamza Mahfooz2022-07-051-1/+1
| | | | | | | | | hdmi_frl_pcon_support has been the source of confusion. So, rename it to dp_hdmi21_pcon_support. Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: enable PCON SST support for newer ASICsHamza Mahfooz2022-07-051-0/+1
| | | | | | | | | | Generic PCON SST support already exists and works for newer ASICs. So, enable it by default. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Extend soc BB capabilitiyJun Lei2022-07-051-114/+389
| | | | | | | | | | | | | | [why] Some parts are consuming dangerously close to maximum number of states supported when updating the BB (i.e. 8). [how] Change maximum stages from 9 to 20. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update gpuvm_max_page_table_levels IP paramEric Bernstein2022-07-051-1/+1
| | | | | | | | | After some experimental tests, we noticed that we need to set gpuvm_max_page_table_levels to '4' to meet the hardware requirements. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Prepare for new interfacesMartin Leung2022-07-051-10/+6
| | | | | | | | | | | | | | | [WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/display: make FP handling in Makefiles consistentAlex Deucher2022-06-141-2/+3
| | | | | | | | Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/display: fix DCN3.2 Makefiles for non-x86Alex Deucher2022-06-061-1/+8
| | | | | | | | Add proper handling for PPC64. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement DTBCLK ref switching on dcn32Alvin Lee2022-06-031-3/+8
| | | | | | | | | | | [WHY & HOW] Implements DTB ref clock switching with reg key default to OFF. Refactors dccg DTBCLK logic to not store redundant state information dccg. Also removes duplicated functions that should be inherited from other dcn versions. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove W/A for ODM memory pinsAlvin Lee2022-06-031-1/+1
| | | | | | | | | [Description] By default we can now set ODM_MEM_VBLANK_PWR_MODE=1 Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: change dsc image width cap for dcn32 and dcn321Dillon Varone2022-06-031-0/+3
| | | | | | | Set appropriate caps for DCN3.2.x. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: set dram speed for all statesDillon Varone2022-06-031-1/+5
| | | | | | | | | | | | [WHY?] If higher states have memory speed set to 0 MT/s currently they do not get set to the highest value which can cause validation failures. [HOW?] Set unpopulated higher states to max value. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: use updated clock source init routineCharlene Liu2022-06-031-1/+1
| | | | | | | | | [why] Use correct clock source initialization routine for DCN32/321 Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add missing instance for clock source registerAlvin Lee2022-06-031-1/+2
| | | | | | | | | | [Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix USBC link creationDillon Varone2022-06-034-2/+244
| | | | | | | | | | | | | [Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add DCN32/321 specific files for Display CoreAurabindo Pillai2022-06-033-18/+90
| | | | | | | | | Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add CLKMGR changes for DCN32/321Aurabindo Pillai2022-06-031-0/+2325
Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-20 16:22:15 +0000