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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 443Thomas Gleixner2019-06-051-5/+1
| | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software and is provided to you under the terms of the gnu general public license version 2 as published by the free software foundation and any use by you of this program is subject to the terms of such gnu licence extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 13 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.691558990@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drm/arm/malidp: Specified the rotation memory requirements for AFBC YUV formatsAyan Kumar Halder2019-03-121-9/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly supported AFBC YUV formats have the following rotation memory constraints (in DP550/DP650). 1. DRM_FORMAT_VUY888/DRM_FORMAT_VUY101010 :- It can rotate upto 8 horizontal lines in the AFBC output buffer. 2. DRM_FORMAT_YUV420_8BIT :- It can rotate upto 16 horizontal lines in the AFBC output buffer. Also some of the pixel formats are specified in bits per pixel (rather than bytes per pixel), so the calculation needs to take note of this. Besides there are some difference between DP550 and DP650 and these are as follows:- 1. DRM_FORMAT_X0L2 (in uncompressed format) does not support rotation in DP550. For DP650, it can rotate upto 16 horizontal lines in the AFBC output buffer, whereas in DP550 (with AFBC), it can rotate upto 8 horizontal lines. 2. DRM_FORMAT_YUV420_10BIT :- It can rotate upto 8 horizontal lines in dp550 and 16 horizontal lines in DP650. Changes since v3 (series): - Added the ack - Rebased on the latest drm-misc-next Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://patchwork.freedesktop.org/patch/291763/?series=57895&rev=1
* drm/arm/malidp:- Define a common list of AFBC format modifiers supported for ↵Ayan Kumar Halder2019-03-121-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DP500, DP550 and DP650 We need to define a common list of format modifiers supported by each of the Mali display processors. The following are the constraints with AFBC:- 1. AFBC is not supported for the formats defined in malidp_hw_format_is_linear_only() 2. Some of the formats are supported only with AFBC modifiers. Thus we have introduced a new function 'malidp_hw_format_is_afbc_only()' which verifies the same. 3. AFBC_FORMAT_MOD_YTR needs to be provided for any RGB format. 4. Formats <= 16bpp cannot support AFBC_FORMAT_MOD_SPLIT. 5. CBR should not be set for non-subsampled formats. 6. SMART layer does not support framebuffer with AFBC modifiers. Return -EINVAL for such a scenario. 7. AFBC_FORMAT_MOD_YTR is not supported for any YUV formats. 8. Formats which are subsampled cannot support AFBC_FORMAT_MOD_SPLIT. However in DP550, YUV_420_10BIT is supported with AFBC_FORMAT_MOD_SPLIT. This feature has been identified with MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT. 9. In DP550 and DP650, for YUYV, the hardware supports different format-ids to be used with and without AFBC modifier. We have used the feature 'MALIDP_DEVICE_AFBC_YUYV_USE_422_P2' to identify this characteristic. 10. DP500 does not support split mode (ie AFBC_FORMAT_MOD_SPLIT). We have used the feature 'MALIDP_DEVICE_AFBC_SUPPORT_SPLIT' to identify the DPs which support SPLIT mode. 11. DP550 supports YUV420 with split mode. We have defined the feature 'AFBC_SUPPORT_SPLIT_WITH_YUV_420_10' to identify this characteristic. Changes since v1:- - Merged https://patchwork.freedesktop.org/patch/265215/ into this patch - As Liviu pointed out in the last patch, we can pull the checks outside of the 'while (*modifiers != DRM_FORMAT_MOD_INVALID)' loop - Rebased Changes since v3 (series): - Added the ack - Rebased on the latest drm-misc-next Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://patchwork.freedesktop.org/patch/291762/?series=57895&rev=1
* drm/arm/malidp:- Added support for new YUV formats for DP500, DP550 and DP650Ayan Kumar Halder2019-03-121-1/+21
| | | | | | | | | | | | | | | | | | | | | | We have added support for some AFBC only pixel formats like :- DRM_FORMAT_YUV420_8BIT (single plane YUV 420 8 bit format) DRM_FORMAT_VUY888 (single plane YUV 444 8 bit format) DRM_FORMAT_VUY101010 (single plane YUV 444 10 bit format) DRM_FORMAT_YUV420_10BIT (single plane YUV 420 10 bit format) Generally, these formats are supported by our hardware using the same hw-ids as the equivalent multi plane pixel formats. Also we have added support for XYUV 444 8 and 10 bit formats Changes since v3 (series): - Added the ack - Rebased on the latest drm-misc-next Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://patchwork.freedesktop.org/patch/291761/?series=57895&rev=1
* drm/arm/malidp: Set the AFBC register bits if the framebuffer has AFBC modifierAyan Kumar Halder2019-03-121-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the AFBC decoder registers for DP500 , DP550 and DP650. These registers control the processing of AFBC buffers. It controls various features like AFBC decoder enable, lossless transformation and block split as well as setting of the left, right, top and bottom cropping of AFBC buffers (in number of pixels). All the layers (except DE_SMART) support framebuffers with AFBC modifiers. One needs to set the pixel values of the top, left, bottom and right cropping for the AFBC framebuffer. Cropping an AFBC framebuffer is controlled by the AFBC crop registers. In that case, the layer input size registers should be configured with framebuffer's dimensions and not with drm_plane_state source width/height values (which is used for non AFBC framebuffer to denote cropping). Changes from v1: - Removed the "if (fb->modifier)" check from malidp_de_plane_update() and added it in malidp_de_set_plane_afbc(). This will consolidate all the AFBC specific register configurations in a single function ie malidp_de_set_plane_afbc(). Changes from v2: - For AFBC framebuffer, layer input size register should be set to framebuffer's width and height. Changes from v3: - Rebased on top of latest drm-misc-next - Some cleanups/sanity changes based on Liviu's comments Changes from v3 (series): - Added the ack - Rebased on the latest drm-misc-next Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://patchwork.freedesktop.org/patch/291760/?series=57895&rev=1
* drm: mali-dp: Enable Mali-DP tiled buffer formatsAlexandru Gheorghe2018-11-021-3/+11
| | | | | | | | | | Enable the following formats - DRM_FORMAT_X0L0: DP650 - DRM_FORMAT_X0L2: DP550, DP650 Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181101151051.1509-4-alexandru-cosmin.gheorghe@arm.com
* drm/arm/malidp: Validate rotations for compressed/uncompressed framebuffers ↵Liviu Dudau2018-10-021-22/+17
| | | | | | | | | | | | | | | | for each layer Add support for compressed framebuffers that are described using the framebuffer's modifier field. Mali DP uses the rotation memory for the decompressor of the format, so we need to check for space when the modifiers are present. Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> [re-worded commit, rebased, cleaned up duplicated checks for RGB888 and BGR888 and removed additional parameter for rotmem_required function hook] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/malidp: Enable MMU prefetch on Mali-DP650Jamie Fox2018-10-021-9/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mali-DP650 supports warming up the SMMU translations, by sending requsts to the SMMU before a buffer is read. There are two modes supported: - PARTIAL: could be enabled when the buffer is composed of 4K or 64K pages, the display hardware will send a configurable number of requests before the actual reading. - FULL: could be enabled when the buffer is composed of 1M or 2M pages, the display hardware will send requests before reading for all pages composing the buffer. This patch adds a mechanism for detecting the page size and set the MMU prefetch mode if possible. Changes since v1: - For imported buffers use the already populated drm_gem_cma_object.sgt instead of calling driver.gem_prime_get_sg_table, which works just for buffers allocated through the gem_cma API. Signed-off-by: Jamie Fox <jamie.fox@arm.com> Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> [rebased and re-ordered functions] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/malidp: Fix writeback in NV12Alexandru Gheorghe2018-10-021-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | When we want to writeback to memory in NV12 format we need to program the RGB2YUV coefficients. Currently, we don't program the coefficients and NV12 doesn't work at all. This patchset fixes that by programming a sane default(bt709, limited range) as rgb2yuv coefficients. In the long run, probably we need to think of a way for userspace to be able to program that, but for now I think this is better than not working at all or not advertising NV12 as a supported format for memwrite. Changes since v1: - Write the rgb2yuv coefficients only once, since we don't change them at all, just write them the first time NV12 is programmed, suggested by Brian Starkey, here [1] [1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186819.html Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/arm/malidp: Set the output_depth register in modesetAyan Kumar Halder2018-07-051-0/+4
| | | | | | | | | | One needs to store the value of the OUTPUT_DEPTH that one has parsed from device tree, so that it can be restored on system resume. This value is set in the modeset function as this gets reset when the system suspends. Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/arm/malidp: Split malidp interrupt initialization functions.Ayan Kumar Halder2018-07-051-9/+29
| | | | | | | | | | | | | | Malidp uses two interrupts ie 1. se_irq - used for memory writeback. and 2. de_irq - used for display output. Extract the hardware initialization part from malidp interrupt registration ie (malidp_de_irq_init()/ malidp_se_irq_init()) into a separate function (ie malidp_de_irq_hw_init()/malidp_se_irq_hw_init()) which will be later invoked from runtime_pm_resume function when it needs to re-enable the interrupts. Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/arm/malidp: Modified the prototype of malidp irq de-initializersAyan Kumar Halder2018-07-051-8/+2
| | | | | | | | | | | | | | | Malidp uses two interrupts ie 1. se_irq - used for memory writeback. and 2. de_irq - used for display output. 'struct drm_device' is being replaced with 'struct malidp_hw_device' as the function argument. The reason being the dependency of malidp_de_irq_fini on 'struct drm_device' needs to be removed so as to enable it to call from functions which receives 'struct malidp_hw_device' as argument. Furthermore, there is no way to retrieve 'struct drm_device' from 'struct malidp_hw_device'. Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Add debugfs file for reporting internal errorsAlexandru Gheorghe2018-07-051-7/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Status register contains a lot of bits for reporting internal errors inside Mali DP. Currently, we just silently ignore all of the errors, that doesn't help when we are investigating different bugs, especially on the FPGA models which have a lot of constraints, so we could easily end up in AXI or underrun errors. Add a new file called debug that contains an aggregate of the errors reported by the Mali DP hardware. E.g: [root@alarm ~]# cat /sys/kernel/debug/dri/1/debug [DE] num_errors : 167 [DE] last_error_status : 0x00000001 [DE] last_error_vblank : 385 [SE] num_errors : 3 [SE] last_error_status : 0x00e23001 [SE] last_error_vblank : 201 Changes since v2: - Add lock to protect the errors stats. - Add possibility to reset the error stats by writing anything to the debug file. Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/mali-dp: Improve writeback handling for DP500.Liviu Dudau2018-07-051-11/+28
| | | | | | | | | | | | | | | | | | | Mali DP500 operates in continuous writeback mode (writes frame content until stopped) and it needs special handling in order to behave like a one-shot writeback engine. The original state machine added for DP500 was a bit fragile, as it did not handle correctly cases where a new atomic commit was in progress when the SE IRQ happens and it would commit some partial updates. Improve the handling by adding a parameter to the set_config_valid() function to clear the config valid bit in hardware before starting a new commit and by introducing a MW_RESTART state in the writeback state machine to cater for the case where a new writeback commit gets submitted while the last one is still being active. Reported-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Add writeback connectorBrian Starkey2018-07-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Mali-DP has a memory writeback engine which can be used to write the composition result to a memory buffer. Expose this functionality as a DRM writeback connector on supported hardware. Changes since v1: Daniel Vetter: - Don't require a modeset when writeback routing changes - Make writeback connector always disconnected Changes since v2: - Rebase onto new drm_writeback_connector - Add reset callback, allocating subclassed state Daniel Vetter: - Squash out-fence support into this commit Gustavo Padovan: - Don't signal fence directly from driver (and drop malidp_mw_job) Changes since v3: - Modifications to fit with Mali-DP commit tail changes Signed-off-by: Brian Starkey <brian.starkey@arm.com> [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/mali-dp: Add RGB writeback formats for DP500.Liviu Dudau2018-07-051-5/+5
| | | | | | | | Annotate the pixel format matrix for DP500 with the memory-write flag for formats that are supported by the SE memwrite engine. Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/mali-dp: Add writeback support for DP500.Liviu Dudau2018-07-051-3/+79
| | | | | | | | | | | | | | | | | | | | | | | | Mali DP500 behaves differently from the rest of the Mali DP IP, in that it does not have a one-shot mode and keeps writing the content of the current frame to the provided memory area until stopped. As a way of emulating the one-shot behaviour, we are going to use the CVAL interrupt that is being raised at the start of each frame, during prefetch phase, to act as End-of-Write signal, but with a twist: we are going to disable the memory write engine right after we're notified that it has been enabled, using the knowledge that the bit controlling the enabling will only be acted upon on the next vblank/prefetch. CVAL interrupt will fire durint the next prefetch phase every time the global CVAL bit gets set, so we need a state byte to track the memory write enabling. We also need to pay attention during the disabling of the memory write engine as that requires the CVAL bit to be set in the control register, but we don't want to do that during an atomic commit, as it will write into the hardware a partial state. Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Add RGB writeback formats for DP550/DP650Brian Starkey2018-07-051-11/+11
| | | | | | | | | | Add a layer bit for the SE memory-write, and add it to the pixel format matrix for DP550/DP650. Signed-off-by: Brian Starkey <brian.starkey@arm.com> [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Add support for writeback on DP550/DP650Liviu Dudau2018-07-051-2/+53
| | | | | | | | | | | | | | | | | Mali-DP display processors are able to write the composition result to a memory buffer via the SE. Add entry points in the HAL for enabling/disabling this feature, and implement support for it on DP650 and DP550. DP500 acts differently and so is omitted from this change. Changes since v3: - Fix missing vsync interrupt for DP550 Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Brian Starkey <brian.starkey@arm.com> [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com>
* drm: mali-dp: Enable Global SE interrupts mask for DP500Alison Wang2018-06-181-1/+2
| | | | | | | | | | | In the situation that DE and SE aren’t shared the same interrupt number, the Global SE interrupts mask bit MASK_IRQ_EN in MASKIRQ must be set, or else other mask bits will not work and no SE interrupt will occur. This patch enables MASK_IRQ_EN for SE to fix this problem. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Add YUV->RGB conversion support for video layersMihail Atanassov2018-03-141-7/+7
| | | | | | | | | | | | | | | | Internally Mali DP uses an RGB pipeline so video layers that support YUV input buffers need to convert the input data to RGB. The YUV buffers can have various encodings and this patch introduces support for BT.601, BT.709 and BT.2020 encodings, both limited and full ranges. This patch adds support for specifying the color encoding of the input buffers for the planes that are backed by the video layers and programs the YUV2RGB coefficients into hardware based on the selected encoding. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> [updated to use standard properties] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending.Liviu Dudau2018-03-141-3/+9
| | | | | | | | | | | | | | | | | | | Mali DP hardware has a 'go' bit (config_valid) for making the new scene parameters active at the next page flip. The problem with the current code is that the driver first sets this bit and then proceeds to wait for confirmation from the hardware that the configuration has been updated before arming the vblank event. As config_valid is actually asserted by the hardware after the vblank event, during the prefetch phase, when we get to arming the vblank event we are going to send it at the next vblank, in effect halving the vblank rate from the userspace perspective. Fix it by sending the userspace event from the IRQ handler, when we handle the config_valid interrupt, which syncs with the time when the hardware is active with the new parameters. Reported-by: Alexandru-Cosmin Gheorghe <alexandru-cosmin.gheorghe@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Separate static internal data into a read-only structure.Liviu Dudau2017-11-241-21/+25
| | | | | | | | | | | | | The malidp_hw_device structure that the driver uses to handle the differences between versions of the IP contains both non-changeable data and fields that get updated at probe time. Previously we were copying the read-only part into allocated memory, but that can be completely avoided by splitting the structure into a read-only part and keeping the runtime modifiable fields into the old structure. Reviewed-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm/mali-dp: Check PM status when sharing interrupt linesLiviu Dudau2017-06-161-3/+16
| | | | | | | | | | | If an instance of Mali DP hardware shares the interrupt line with another hardware (usually another instance of the Mali DP) its interrupt handler can get called when the device is suspended. Check the PM status before making access to the hardware registers to avoid deadlocks. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: Check the mclk rate and allow up/down scalingMihail Atanassov2017-04-241-0/+70
| | | | | | | | | | | When downscaling, mclk needs to be sufficiently higher than pxlclk in order to be able to fetch the higher-resolution data and produce output pixels. When not scaling, or when upscaling, mclk can be equal to pxlclk. Since the driver doesn't control mclk, just ensure that the requirement is satisfied with the current clock rate. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: Add plane upscaling supportMihail Atanassov2017-04-241-0/+140
| | | | | | | | | | | Enable the scaling engine for upscaling a single plane using the polyphase scaler. No image enhancement support or downscaling yet*, and composition result scaling is not implemented. * Downscaling a plane requires mclk > pxlclk. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: enable gamma supportMihail Atanassov2017-04-241-0/+3
| | | | | | | | | | | | | | Add gamma via the DRM GAMMA_LUT/GAMMA_LUT_SIZE CRTC properties. The expected LUT size is 4096 in order to produce as accurate a set of segments as possible. This version uses only the green channel's gamma curve to set the hardware curve on DP550/650. For the sake of simplicity, it uses the same table of coefficients for all 3 curves on DP500. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: Fix smart layer not going to compositionMihail Atanassov2017-03-101-1/+1
| | | | | | | | | | Use rectangle 1 as a generic plane. Existing code already sets the smart layer bounding box size + offset. The rectangles' offsets are relative to the bounding box, so there is no need to set R1's offset (reset value is 0), just its size which is the same as the bounding box. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* drm: mali-dp: fix stride setting for multi-plane formatsMihail Atanassov2017-01-261-7/+10
| | | | | | | | | | | | Hardware has multiple (2 or 3, depending on model) stride registers per layer; add a function that correctly takes that into account. On hardware that only has 2 stride registers, ensure that 3-plane (YUV) content has identical strides for both chroma planes. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> [Removed smart layer stride setup, comment and commit message clarifications] Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: Rename malidp_input_format to malidp_pixel_formatBrian Starkey2017-01-261-12/+12
| | | | | | | | | We're going to use the same format list for output formats, so rename everything related to input formats to avoid confusion. Signed-off-by: Brian Starkey <brian.starkey@arm.com> [touched commit title to clarify the final struct name] Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: Clear CVAL when leaving config modeBrian Starkey2016-11-081-0/+2
| | | | | | | | | | | | | It's possible for CVAL to get set whilst we are in config mode. If this happens, afer we leave config mode the HW will latch whatever configuration is in the registers at the next vsync. Most likely this will be a partial configuration, as we'll be racing against the ongoing atomic_commit. To avoid this, clear CVAL before leaving config mode. Signed-off-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm: mali-dp: Add pitch alignment check functionBrian Starkey2016-11-041-0/+3
| | | | | | | | | Different hardware versions have different requirements when it comes to pitch alignment. Add a function which can be used to check pitch alignment for a device. Signed-off-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
* drm/arm: mali-dp: Replace drm_fb_get_bpp_depth() with drm_format_plane_cpp()Laurent Pinchart2016-10-181-6/+1
| | | | | | | | | | The driver doesn't need the color depth, only the number of bits per pixel. Use the right API. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1476744081-24485-13-git-send-email-laurent.pinchart@ideasonboard.com
* drm/arm: Add support for Mali Display ProcessorsLiviu Dudau2016-06-151-0/+691
Add support for the new family of Display Processors from ARM Ltd. This commit adds basic support for Mali DP500, DP550 and DP650 parts, with only the display engine being supported at the moment. Cc: David Brown <David.Brown@arm.com> Cc: Brian Starkey <Brian.Starkey@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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