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path: root/drivers/gpu/drm/i915/i915_pci.c
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* drm/i915: Move display device info capabilities to its own structJosé Roberto de Souza2018-12-031-53/+64
| | | | | | | | | | | | | This helps separate what capabilities are display capabilities. v3: Moving display struct right after flags (Lucas) Cc: Jani Nikula <jani.nikula@linux.intel.com> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-2-jose.souza@intel.com
* drm/i915: Make pipe/transcoder offsets not depend on enum valuesImre Deak2018-11-211-14/+38
| | | | | | | | | | | | Depending on the transcoder enum values to translate from transcoder to pipe/transcoder register addresses can easily break if we add a new transcoder. So remove the dependency by using named initializers. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120092325.21249-1-imre.deak@intel.com
* drm/i915: remove excess line continuation backslashesJani Nikula2018-11-151-2/+2
| | | | | | | | | | | | | | | While removing .palette_offsets, I removed the commas after .trans_offsets in the macros, but failed to remove the line continuation backslashes. While at it, also remove another extra comma to be in line with the other related macros. Fixes: 74c1e826427a ("drm/i915: remove palette_offsets from device info in favor of _PICK()") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114112130.22264-1-jani.nikula@intel.com
* drm/i915: remove palette_offsets from device info in favor of _PICK()Jani Nikula2018-11-021-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device info offset arrays for unevenly spaced register offsets is great for widely used registers. However, the palette registers are only used in one function, i9xx_load_luts_internal(), and only for GMCH platforms, wasting device info. Replace palette_offsets with _PICK() in palette register definition. While the use of _PICK() does not check for pipe C existence, neither does the current offset array usage, and leads to bogus address when pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads to a sensible register offset, just non-existing on non-CHV. Either way, this shouldn't happen anyway. Remove unused old palette macros while at it. Bloat-o-meter results below for completeness. add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184) Function old new delta i9xx_load_luts_internal 394 483 +89 i915_driver_load 5103 5107 +4 g4x_pre_enable_dp 378 379 +1 intel_engines_init_mmio 1117 1116 -1 intel_engine_lookup_user 47 46 -1 hdmi_port_clock_valid 310 309 -1 gen11_irq_handler 707 706 -1 intel_device_info_dump_runtime 329 311 -18 intel_device_info_runtime_init 5166 4910 -256 Total: Before=918650, After=918466, chg -0.02% add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576) Data old new delta intel_valleyview_info 200 188 -12 intel_skylake_gt4_info 200 188 -12 intel_skylake_gt3_info 200 188 -12 intel_skylake_gt2_info 200 188 -12 intel_skylake_gt1_info 200 188 -12 intel_sandybridge_m_gt2_info 200 188 -12 intel_sandybridge_m_gt1_info 200 188 -12 intel_sandybridge_d_gt2_info 200 188 -12 intel_sandybridge_d_gt1_info 200 188 -12 intel_pineview_info 200 188 -12 intel_kabylake_gt3_info 200 188 -12 intel_kabylake_gt2_info 200 188 -12 intel_kabylake_gt1_info 200 188 -12 intel_ivybridge_q_info 200 188 -12 intel_ivybridge_m_gt2_info 200 188 -12 intel_ivybridge_m_gt1_info 200 188 -12 intel_ivybridge_d_gt2_info 200 188 -12 intel_ivybridge_d_gt1_info 200 188 -12 intel_ironlake_m_info 200 188 -12 intel_ironlake_d_info 200 188 -12 intel_icelake_11_info 200 188 -12 intel_i965gm_info 200 188 -12 intel_i965g_info 200 188 -12 intel_i945gm_info 200 188 -12 intel_i945g_info 200 188 -12 intel_i915gm_info 200 188 -12 intel_i915g_info 200 188 -12 intel_i865g_info 200 188 -12 intel_i85x_info 200 188 -12 intel_i845g_info 200 188 -12 intel_i830_info 200 188 -12 intel_haswell_gt3_info 200 188 -12 intel_haswell_gt2_info 200 188 -12 intel_haswell_gt1_info 200 188 -12 intel_gm45_info 200 188 -12 intel_geminilake_info 200 188 -12 intel_g45_info 200 188 -12 intel_g33_info 200 188 -12 intel_coffeelake_gt3_info 200 188 -12 intel_coffeelake_gt2_info 200 188 -12 intel_coffeelake_gt1_info 200 188 -12 intel_cherryview_info 200 188 -12 intel_cannonlake_info 200 188 -12 intel_broxton_info 200 188 -12 intel_broadwell_rsvd_info 200 188 -12 intel_broadwell_gt3_info 200 188 -12 intel_broadwell_gt2_info 200 188 -12 intel_broadwell_gt1_info 200 188 -12 Total: Before=195529, After=194953, chg -0.29% Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181031110453.12722-1-jani.nikula@intel.com
* drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan2018-10-221-0/+3
| | | | | | | | | | | | | | | | This patch defines TRANS_CONF registers for DSI ports 0 and 1. Bitfields of these registers used for enabling and reading the current state of transcoder. v2: Add blank line before comment v3 by Jani: - Move DSI specific .pipe_offsets to GEN11_FEATURES - Macro placement and comment juggling Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3aa11e41ea0d4eb434423cc5ddf0a63b19d54deb.1539613303.git.jani.nikula@intel.com
* drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan2018-10-221-0/+3
| | | | | | | | | | | | | | | | | | This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2 registers and their bitfields for DSI. These registers are used for enabling port sync mode, input pipe select, data lane width configuration etc. v2: Changes: - Remove redundant extra line - Correct some of bitfield definition v3 by Jani: - Move DSI transcoder offsets to GEN11_FEATURES Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6b2d87db82660320be10e423742cbf5a31e18037.1539613303.git.jani.nikula@intel.com
* drm/i915/aml: Add new Amber Lake PCI IDJosé Roberto de Souza2018-10-111-1/+2
| | | | | | | | | | | | | | | | | This new AML PCI ID uses the same gen graphics as Coffe Lake not a Kaby Lake one like the other AMLs. So to make it more explicit renaming INTEL_AML_GT2_IDS to INTEL_AML_KBL_GT2_IDS and naming this id as INTEL_AML_CFL_GT2_IDS. v2: - missed add new AML macro to INTEL_CFL_IDS() - added derivated platform initials to AML macros Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180927010650.22731-1-jose.souza@intel.com
* drm/i915: Remove i915.enable_ppgtt overrideChris Wilson2018-09-271-11/+6
| | | | | | | | | | | | | | | | | | | Now that we are confident in providing full-ppgtt where supported, remove the ability to override the context isolation. v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted. v3: s/USES/HAS/ to match usage and reject attempts to load the module on old GVT-g setups that do not provide support for full-ppgtt. v4: Insulate ABI ppGTT values from our internal enum (later plans involve moving ppGTT depth out of the enum, thus potentially breaking ABI unless we document the current values). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Zhi Wang <zhi.a.wang@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180926201222.5643-1-chris@chris-wilson.co.uk
* drm/i915: Move SKL IPC WA to HAS_IPC()José Roberto de Souza2018-09-261-0/+2
| | | | | | | | | | | SKL has IPC but it should not be set according to the WA, so lets just mark as it don't have it to simply the code and avoid unnecessary MMIO writes at every call to intel_enable_ipc(). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180918204714.27306-4-jose.souza@intel.com
* drm/i915: Do not redefine the has_csr parameter.Anusha Srivatsa2018-08-171-1/+0
| | | | | | | | | | | | | | | | | Let us reuse the already defined has_csr check and not redefine it. The main difference is that in effect this will flip .has_csr to 1 (via GEN9_FEATURES which GEN11_FEATURES pulls in). Suggested-by: Imre Deak <imre.deak@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107382 Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1534527210-16841-1-git-send-email-anusha.srivatsa@intel.com
* drm/i915: kill resource streamer supportLucas De Marchi2018-08-061-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After disabling resource streamer on ICL (due to it actually not existing there), I got feedback that there have been some experimental patches for mesa to use RS years ago, but nothing ever landed or shipped because there was no performance improvement. This removes it from kernel keeping the uapi defines around for compatibility. v2: - re-add the inadvertent removal of CTX_CTRL_INHIBIT_SYN_CTX_SWITCH - don't bother trying to document removed params on uapi header: applications should know that from the query. (from Chris) v3: - disable CTX_CTRL_RS_CTX_ENABLE istead of removing it - reword commit message after Daniele confirmed no performance regression on his machine - reword commit message to make clear RS is being removed due to never been used v4: - move I915_EXEC_RESOURCE_STREAMER to __I915_EXEC_ILLEGAL_FLAGS so the check on ioctl() is made much earlier by i915_gem_check_execbuffer() (suggested by Tvrtko) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180803232443.17193-1-lucas.demarchi@intel.com
* drm/i915/icl: move has_resource_streamer to GEN11_FEATURESLucas De Marchi2018-08-061-1/+1
| | | | | | | | | | Resource streamer has been removed on GEN11 so move it to the FEATURES macro. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180719170557.10729-1-lucas.demarchi@intel.com
* drm/i95: Mark GGTT as incoherent for gen10+Chris Wilson2018-08-011-0/+1
| | | | | | | | | | | | | | The evidence suggests that we need to start treating writes via GGTT as incoherent for gen10+, that is that they are internally buffered and not immediately visible via a read along a different physical path. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107398 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107400 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107435 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180801104721.4030-1-chris@chris-wilson.co.uk
* drm/i915: Only force GGTT coherency w/a on required chipsetsChris Wilson2018-07-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | Not all chipsets have an internal buffer delaying the visibility of writes via the GGTT being visible by other physical paths, but we use a very heavy workaround for all. We only need to apply that workarounds to the chipsets we know suffer from the delay and the resulting coherency issue. Similarly, the same inconsistent coherency fouls up our ABI promise that a write into a mmap_gtt is immediately visible to others. Since the HW has made that a lie, let userspace know when that contract is broken. (Not that userspace would want to use mmap_gtt on those chipsets for other performance reasons...) Testcase: igt/drv_selftest/live_coherency Testcase: igt/gem_mmap_gtt/coherency Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100587 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Tomasz Lis <tomasz.lis@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180720101910.11153-1-chris@chris-wilson.co.uk
* drm/i915: Remove pci private pointer after destroying the device privateChris Wilson2018-07-161-1/+12
| | | | | | | | | | | On an aborted module load, we unwind and free our device private - but we left a dangling pointer to our privates inside the pci_device. After the attempted aborted unload, we may still get a call to i915_pci_remove() when the module is removed, potentially chasing stale data. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180716080332.32283-5-chris@chris-wilson.co.uk
* drm/i915/aml: Introducing Amber Lake platformJosé Roberto de Souza2018-06-181-0/+1
| | | | | | | | | | | | | | | Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180614233720.30517-2-jose.souza@intel.com
* drm/i915/whl: Introducing Whiskey Lake platformJosé Roberto de Souza2018-06-181-1/+3
| | | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. v2: Fixing GT level of some ids Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180614233720.30517-1-jose.souza@intel.com
* drm/i915/psr: Nuke PSR support for VLV and CHVDhinakaran Pandiyan2018-05-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | PSR hardware and hence the driver code for VLV and CHV deviates a lot from their DDI counterparts. While the feature has been disabled for a long time now, retaining support for these platforms is a maintenance burden. There have been multiple refactoring commits to just keep the existing code for these platforms in line with the rest. There are known issues that need to be fixed to enable PSR on these platforms, and there is no PSR capable platform in CI to ensure the code does not break again if we get around to fixing the existing issues. On account of all these reasons, let's nuke this code for now and bring it back if a need arises in the future. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180511230059.19387-1-dhinakaran.pandiyan@intel.com
* drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11Oscar Mateo2018-03-201-0/+1
| | | | | | | | | | | | | | Icelake 11 has one vebox and two vdboxes (0 and 2). Bspec: 21140 v2: Split out in two (Daniele) Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-2-mika.kuoppala@linux.intel.com Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
* drm/i915/icl: Enhanced execution list supportThomas Daniel2018-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhanced Execlists is an upgraded version of execlists which supports up to 8 ports. The lrcs to be submitted are written to a submit queue (the ExecLists Submission Queue - ELSQ), which is then loaded on the HW. When writing to the ELSP register, the lrcs are written cyclically in the queue from position 0 to position 7. Alternatively, it is possible to write directly in the individual positions of the queue using the ELSQC registers. To be able to re-use all the existing code we're using the latter method and we're currently limiting ourself to only using 2 elements. v2: Rebase. v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio). v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio) v5: Reword commit, rename regs to be closer to specs, turn off preemption (Daniele), reuse engine->execlists.elsp (Chris) v6: use has_logical_ring_elsq to differentiate the new paths v7: add preemption support, rename els to submit_reg (Chris) v8: save the ctrl register inside the execlists struct, drop CSB handling updates (superseded by preempt_complete_status) (Chris) v9: s/drm_i915_gem_request/i915_request (Mika) v10: resolved conflict in inject_preempt_context (Mika) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180302161501.28594-4-mika.kuoppala@linux.intel.com
* drm/i915/icl: Add the ICL PCI IDsPaulo Zanoni2018-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This is the current PCI ID list in our documentation. Let's leave the _gt#_ part out for now since our current documentation is not 100% clear and we don't need this info now anyway. v2: Use the new ICL_11 naming (Kelvin Gardiner). v3: Latest IDs as per BSpec (Oscar). v4: Make it compile (Paulo). v5: Remove comments (Lucas). v6: Multile rebases (Paulo). v7: Rebase (Mika) Reviewed-by: Anuj Phogat <anuj.phogat@intel.com> (v1) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180220153755.13509-1-mika.kuoppala@linux.intel.com
* drm/i915: Store platform_mask inside the static device infoChris Wilson2018-02-151-32/+38
| | | | | | | | | | | | Rather than deriving the platform_mask from the intel_device_static_info->platform at runtime, pre-fill it in the static data. v2: Undefine macros at end of their scope Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180215081930.11477-3-chris@chris-wilson.co.uk
* drm/i915: Always define GEN as part of GENx_FEATURESChris Wilson2018-02-151-5/+3
| | | | | | | | | Be consistent and define the device's GEN as part of the GENx_FEATURE. It will be overridden by the next gen upon inheriting, as per usual. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180215081930.11477-2-chris@chris-wilson.co.uk
* drm/i915: Store gen_mask inside the static device infoChris Wilson2018-02-151-15/+26
| | | | | | | | | | | Rather than deriving the gen_mask from the static intel_device_info->gen at runtime, pre-fill it in the static data. v2: Undefine local macros at end of their scope. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180215081930.11477-1-chris@chris-wilson.co.uk
* drm/i915/cnl: Remove alpha_support protectionRodrigo Vivi2018-02-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have a stable cnl on our CI and it seems mostly green without big risks of blank screen or anything blowing up on linux installations in the future. As a reminder i915.alpha_support was created to protect future linux installation's iso images that might contain a kernel from the enabling time of the new platform. Without this protection most of linux installation was recommending nomodeset option during installation that was getting stick there after installation. Specifically, alpha support says nothing about the development state of the hardware, and everything about the state of the driver in a kernel release. This is semantically no different from the old preliminary_hw_support flag, but the old one was all too often interpreted as (preliminary hw) support instead of the intended (preliminary) hw support, and it was misleading for everyone. Hence the rename. v2: Fix the typos and include more history about the parameter rename on commit message. (Jani) Reference: https://intel-gfx-ci.01.org/tree/drm-tip/fi-cnl-y3.html Cc: James Ausmus <james.ausmus@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Saarinen <jani.saarinen@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180214204205.4446-1-rodrigo.vivi@intel.com
* drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.Rodrigo Vivi2018-01-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference is that this SKUs has the full Port A/E split named as Port F. But since SKUs differences don't matter on the platform definition group and ids, let's merge all off them together. v2: Really include the PCI IDs to the picidlist[]; v3: Add the PCI Id for another SKU (Anusha). v4: Update IDs, really include to pciidlists again. v5: Unify all GT2 IDs. v6: Unify in a way that we don't break early-quirks.c v7: Remove GT reference since it doesn't matter here (Paulo) Also move IS_CNL_WITH_PORT_F macro to this patch to make it easier for review this part and also to get used sooner. v8: Rebased on top of commit 5db47e37b387 ("Revert "drm/i915: mark all device info struct with __initconst"") Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-1-rodrigo.vivi@intel.com
* Revert "drm/i915: mark all device info struct with __initconst"Lionel Landwerlin2018-01-291-48/+48
| | | | | | | | | | | | | This reverts commit 5b54eddd3920e9f6f1a6d972454baf350cbae77e. Conflicts: drivers/gpu/drm/i915/i915_pci.c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104805 Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Fixes: 5b54eddd3920 ("drm/i915: mark all device info struct with __initconst") Link: https://patchwork.freedesktop.org/patch/msgid/20180129083346.29173-1-lionel.g.landwerlin@intel.com
* drm/i915/icl: Add initial Icelake definitions.Rodrigo Vivi2018-01-191-0/+13
| | | | | | | | | | | | | | | | | | | | Icelake is an Intel® Processor containing an Intel® Graphics Controller. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the ICL_FEATURES macro (Kelvin Gardiner). v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics controller" instead of something that looks like an official marketing name but isn't (Chris). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180111180010.24357-3-paulo.r.zanoni@intel.com
* drm/i915/cfl: Adding more Coffee Lake PCI IDs.Rodrigo Vivi2017-12-201-0/+2
| | | | | | | | | | | | Spec has been updated with more reserved IDs for existent SKUs. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Anuj Phogat <anuj.phogat@gmail.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171220182919.21108-1-rodrigo.vivi@intel.com
* drm/i915: Remove unsafe i915.enable_rc6Chris Wilson2017-12-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | It has been many years since the last confirmed sighting (and fix) of an RC6 related bug (usually a system hang). Remove the parameter to stop users from setting dangerous values, as they often set it during triage and end up disabling the entire runtime pm instead (the option is not a fine scalpel!). Furthermore, it allows users to set known dangerous values which were intended for testing and not for production use. For testing, we can always patch in the required setting without having to expose ourselves to random abuse. v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the lack of ilk support better. v3: Clear intel_info->rc6p if we don't support rc6 itself. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171201113030.18360-1-chris@chris-wilson.co.uk
* drm/i915: remove g4x lowfreq_avail and has_pipe_cxsrJani Nikula2017-10-191-2/+0
| | | | | | | | | | | | | | They're unused and unsupported. Leave the reduced_clock pointers in place still, should they prove useful later on. v2: go from nuking DDI lowfreq_avail to nuking it entirely (Ville) Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171017140234.20677-1-jani.nikula@intel.com
* drm/i915: Replace *_reference/unreference() or *_ref/unref with _get/put()Harsha Sharma2017-10-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Replace instances of drm_framebuffer_reference/unreference() with *_get/put() suffixes and drm_dev_unref with *_put() suffix because get/put is shorter and consistent with the kernel use of *_get/put suffixes. Done with following coccinelle semantic patch @@ expression ex; @@ ( -drm_framebuffer_unreference(ex); +drm_framebuffer_put(ex); | -drm_dev_unref(ex); +drm_dev_put(ex); | -drm_framebuffer_reference(ex); +drm_framebuffer_get(ex); ) Signed-off-by: Harsha Sharma <harshasharmaiitr@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20171014183644.21990-1-harshasharmaiitr@gmail.com
* drm/i915: enable platform support for 2M pagesMatthew Auld2017-10-071-2/+4
| | | | | | | | | | | | | For gen8+ platforms which support the 48b PPGTT, enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-22-matthew.auld@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-21-chris@chris-wilson.co.uk
* drm/i915: enable platform support for 64K pagesMatthew Auld2017-10-071-1/+2
| | | | | | | | | | | | | For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-21-matthew.auld@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-20-chris@chris-wilson.co.uk
* drm/i915: introduce page_sizes field to dev_infoMatthew Auld2017-10-071-0/+18
| | | | | | | | | | | | | | | | | | | | In preparation for huge gtt pages expose page_sizes as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. v2: s/page_size_mask/page_sizes/ v3: introduce I915_GTT_MAX_PAGE_SIZE Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-5-matthew.auld@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-4-chris@chris-wilson.co.uk
* drm/i915/execlists: Preemption!Chris Wilson2017-10-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we write to ELSP, it triggers a context preemption at the earliest arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other operations and the explicit MI_ARB_CHECK). If this is to the same context, it triggers a LITE_RESTORE where the RING_TAIL is merely updated (used currently to chain requests from the same context together, avoiding bubbles). However, if it is to a different context, a full context-switch is performed and it will start to execute the new context saving the image of the old for later execution. Previously we avoided preemption by only submitting a new context when the old was idle. But now we wish embrace it, and if the new request has a higher priority than the currently executing request, we write to the ELSP regardless, thus triggering preemption, but we tell the GPU to switch to our special preemption context (not the target). In the context-switch interrupt handler, we know that the previous contexts have finished execution and so can unwind all the incomplete requests and compute the new highest priority request to execute. It would be feasible to avoid the switch-to-idle intermediate by programming the ELSP with the target context. The difficulty is in tracking which request that should be whilst maintaining the dependency change, the error comes in with coalesced requests. As we only track the most recent request and its priority, we may run into the issue of being tricked in preempting a high priority request that was followed by a low priority request from the same context (e.g. for PI); worse still that earlier request may be our own dependency and the order then broken by preemption. By injecting the switch-to-idle and then recomputing the priority queue, we avoid the issue with tracking in-flight coalesced requests. Having tried the preempt-to-busy approach, and failed to find a way around the coalesced priority issue, Michal's original proposal to inject an idle context (based on handling GuC preemption) succeeds. The current heuristic for deciding when to preempt are only if the new request is of higher priority, and has the privileged priority of greater than 0. Note that the scheduler remains unfair! v2: Disable for gen8 (bdw/bsw) as we need additional w/a for GPGPU. Since, the feature is now conditional and not always available when we have a scheduler, make it known via the HAS_SCHEDULER GETPARAM (now a capability mask). v3: Stylistic tweaks. v4: Appease Joonas with a snippet of kerneldoc, only to fuel to fire of the preempt vs preempting debate. Suggested-by: Michal Winiarski <michal.winiarski@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-8-chris@chris-wilson.co.uk
* drm/i915: Organize GLK_COLORS.Rodrigo Vivi2017-10-031-2/+4
| | | | | | | | | | | | | Let's organize this in a way that it gets more obvious when looking to the platform colors and in a easier way to get inherited. v2: Add comma at the end (Jani), when possible. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171003063652.17248-3-rodrigo.vivi@intel.com
* drm/i915: Organize GEN features inheritance.Rodrigo Vivi2017-10-031-26/+22
| | | | | | | | | | | | | | | As Chris noticed the current organization is confusing and inheritance is not clear. So, let's split it in GEN<n>_FEATURES <cdn>_PLATFORM where new GEN inherit features from previous gens and Platforms only use gen features plus what ever is specific for that platform and shouldn't be passed on. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171003063652.17248-2-rodrigo.vivi@intel.com
* drm/i915/skl: Fix has_ipc on skl and document WaDisableIPC.Rodrigo Vivi2017-10-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Spec for SKL+: "Isochronous Priority Control. If enabled, Display sends demoted requests once the transition watermark is reached. If transition watermark is not enabled, Display sends demoted requests when the display buffer is full." The commit 'e57f1c02155f ("drm/i915/gen9+: Add has_ipc flag in device info structure")' introduced that as gen9+ but missing many SKL Skus. I believe the reason for that is Spec also mentions workarounds for SKL-ALL: "IPC (Isoch Priority Control) may cause underflows WA: Do not enable IPC in register ARB_CTL2" It seems lame to add the feature and forever disable it, but it will avoid a mistake of enabling it when we are reorganizing the feature definitions on i915_pci.c later. It will also allow us to probably extend that workaround for other platforms. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003063652.17248-1-rodrigo.vivi@intel.com
* drm/i915: Add has_psr-flag to gen9lpDavid Weinehall2017-10-021-0/+1
| | | | | | | | | | | | | | While testing Jim Bride's latest batch of PSR patches I noticed that gen9lp doesn't include the has_psr flag, and that our GLK system thus reported PSR as unsupported. This patch simply adds has_psr. Signed-off-by: David Weinehall <david.weinehall@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170808100952.26448-1-david.weinehall@linux.intel.com
* drm/i915: Rename global i915 to i915_modparamsMichal Wajdeczko2017-09-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our global struct with params is named exactly the same way as new preferred name for the drm_i915_private function parameter. To avoid such name reuse lets use different name for the global. v5: pure rename v6: fix Credits-to: Coccinelle @@ identifier n; @@ ( - i915.n + i915_modparams.n ) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170919193846.38060-1-michal.wajdeczko@intel.com
* drm/i915/cfl: Remove alpha support protection.Rodrigo Vivi2017-09-191-1/+0
| | | | | | | | | | | | | | | We now have Coffee Lake on our CI systems. Coffee Lake is at this point in same stage as Kaby Lake. And it seems that we don't have any risk of bad blank screens or anything like that. So let's remove the protection. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170907230632.25650-1-rodrigo.vivi@intel.com
* drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4xVille Syrjälä2017-09-151-6/+0
| | | | | | | | | | | | | | | | | | Now that we're not using MSI anymore on gen4 we can start using GMBUS and AUX interrupts again. These were disabled on account of them causing the hardware to somehow generate legacy interrupts even when MSI was enabled. See commit c12aba5aa0e6 ("drm/i915: stop using GMBUS IRQs on Gen4 chips") and commit 4e6b788c3f23 ("drm/i915: Disable dp aux irq on g4x") for more details. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jiri Kosina <jkosina@suse.cz> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-17-ville.syrjala@linux.intel.com Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/gen9+: Add has_ipc flag in device info structureMahesh Kumar2017-09-071-0/+4
| | | | | | | | | | | | New Isochronous Priority Control (IPC) capability is introduced in newer GEN platforms. This patch adds a device info flag to indicate if platform supports IPC. Patch also sets this flag in supported platforms. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-7-mahesh1.kumar@intel.com
* drm/i915: Disable snooping (userptr, set-cache-level) on gen4Chris Wilson2017-09-071-0/+2
| | | | | | | | | | | | | | | The original gen4 has an issue where writes (both render and blt) into snoopable pages are lost. We've previously worked around this in userspace (ddx, igt) by simply not requesting snoopable buffers, but upon rediscovering this problem for a third time, make the kernel reject such requests with -ENODEV. This disables snooping on userspace buffers for i965g and i965gm (original gen4) machines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170906192424.26970-1-chris@chris-wilson.co.uk
* drm/i915: Move device_info.has_snoop into the static tablesChris Wilson2017-09-061-0/+7
| | | | | | | | | | | | | | Currently we define any !llc machine as using snoop instead. However, some platforms run into trouble using snoop that we would like to disable, and to do so easily we want to be able to use the static device_info tables. v2: Leave the old snoop = !llc as a warning for the time being to check that all stanzas are filled as either llc or snoop. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170906105653.3665-1-chris@chris-wilson.co.uk
* drm/i915: mark all device info struct with __initconstLionel Landwerlin2017-09-011-47/+47
| | | | | | | | | | As recommended by Chris. v2: Switch from __initdata to __initconst. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-3-lionel.g.landwerlin@intel.com
* drm/i915: add GT number to intel_device_infoLionel Landwerlin2017-09-011-43/+150
| | | | | | | | | | | | | | | | | | | | | | | | Up to Coffeelake we could deduce this GT number from the device ID. This doesn't seem to be the case anymore. This change reorders pciids per GT and adds a gt field to intel_device_info. We set this field on the following platforms : - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL Before & After : $ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l 209 v2: Add SNB & IVB (Chris) v3: Fix compilation error in early-quirks (Lionel) v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-2-lionel.g.landwerlin@intel.com
* drm/i915: Re-enable per-engine reset for BroxtonMichel Thierry2017-08-221-1/+0
| | | | | | | | | | | | | | | | | | | | The corruption in CSB mmio reads we were seeing has been tracked down to incorrectly touching forcewake of all domains, following an engine reset. It is still a mistery why we only catched this in Broxton, since it could happen in any platform. With that fix already merged, commit 4055dc75d6b5 ("drm/i915: Stop touching forcewake following a gen6+ engine reset"), lets try to enable per-engine resets in Broxton one more time. This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for Broxton"). Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818172342.7282-1-michel.thierry@intel.com Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Disable per-engine reset for BroxtonChris Wilson2017-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Triggering a GPU reset for one engine affects another, notably corrupting the context status buffer (CSB) effectively losing track of inflight requests. Adding a few printks: diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ad41836fa5e5..a969456bc0fa 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1953,6 +1953,7 @@ int i915_reset_engine(struct intel_engine_cs *engine) goto out; } + pr_err("Resetting %s\n", engine->name); ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); if (ret) { /* If we fail here, we expect to fallback to a global reset */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 716e5c9ea222..a72bc35d0870 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -355,6 +355,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); port_set(&port[n], port_pack(rq, count)); desc = execlists_update_context(rq); + pr_err("%s: in (rq=%x) ctx=%d\n", engine->name, rq->global_seqno, upper_32_bits(desc)); GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); } else { GEM_BUG_ON(!n); @@ -594,9 +595,23 @@ static void intel_lrc_irq_handler(unsigned long data) if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; + pr_err("%s: out CSB (%x head=%d, tail=%d), ctx=%d, rq=%d\n", + engine->name, + readl(csb_mmio), + head, tail, + readl(buf+2*head+1), + port->context_id); + /* Check the context/desc id for this event matches */ - GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != - port->context_id); + if (readl(buf + 2 * head + 1) != port->context_id) { + pr_err("%s: BUG CSB (%x head=%d, tail=%d), ctx=%d, rq=%d\n", + engine->name, + readl(csb_mmio), + head, tail, + readl(buf+2*head+1), + port->context_id); + BUG(); + } rq = port_unpack(port, &count); GEM_BUG_ON(count == 0); Results in: [ 6423.006602] Resetting rcs0 [ 6423.009080] rcs0: in (rq=fffffe70) ctx=1 [ 6423.009216] rcs0: in (rq=fffffe6f) ctx=3 [ 6423.009542] rcs0: out CSB (2 head=1, tail=2), ctx=3, rq=3 [ 6423.009619] Resetting bcs0 [ 6423.009980] rcs0: BUG CSB (0 head=1, tail=2), ctx=0, rq=3 Note that this bug may be affect all machines and not just Broxton, Broxton is just the first machine on which I have confirmed this bug. Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Acked-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-13-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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