summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
Commit message (Collapse)AuthorAgeFilesLines
...
* | drm/i915/color: Extract icl_read_luts()Swati Sharma2020-03-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For icl+, have hw read out to create hw blob of gamma lut values. icl+ platforms supports multi segmented gamma mode by default, add hw lut creation for this mode. This will be used to validate gamma programming using dsb (display state buffer) which is a tgl specific feature. v2: -readout code for multisegmented gamma has to come up with some intermediate entries that aren't preserved in hardware (Jani N) -linear interpolation (Ville) -moved common code to check gamma_enable to specific funcs, since icl doesn't support that v3: -use u16 instead of __u16 [Jani N] -used single lut [Jani N] -improved and more readable for loops [Jani N] -read values directly to actual locations and then fill gaps [Jani N] -moved cleaning to patch 1 [Jani N] -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to make it similar to icl_load_luts() -renamed icl_compute_interpolated_gamma_blob() to icl_compute_interpolated_gamma_lut_values() more sensible, I guess v4: -removed interpolated func for creating gamma lut values -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA correctly v5: -added gamma_enable check inside read_luts() v6: -renamed intel_color_lut_entry_equal() to intel_color_lut_entries_equal() [Ville] -changed if-else to switch [Ville] -removed intel_color_lut_entry_multi_equal() [Ville] v7: -checkpatch warnings v8: -rebased v9: -rebased, aligned with Ville's style of gamma cleanup Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200317135736.14305-1-swati2.sharma@intel.com
* | drm/i915/perf: Invalidate OA TLB on when closing perf streamUmesh Nerlige Ramappa2020-03-181-0/+2
|/ | | | | | | | | | | | | On running several back to back perf capture sessions involving closing and opening the perf stream, invalid OA reports are seen in the beginning of the OA buffer in some sessions. Fix this by invalidating OA TLB when the perf stream is closed or disabled on gen12. Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200309211057.38575-1-umesh.nerlige.ramappa@intel.com
* drm/i915: Add Wa_1406306137:icl,ehlMatt Roper2020-03-131-0/+1
| | | | | | | | | | v2: - Move to context workarounds. ROW_CHICKEN4 is part of the context image on gen11 (although it isn't on gen12). Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-5-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* drm/i915: Add Wa_1604278689:icl,ehlMatt Roper2020-03-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The bspec description for this workaround tells us to program 0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've previously found that this leads to failures in CI. Our suspicion is that the failures are caused by this valid turning on the "address valid bit" even though we're intentionally supplying an invalid address. Experimentation has shown that setting all bits _except_ for the RT_VALID bit seems to avoid these failures. v2: - Mask off the RT_VALID bit. Experimentation with CI trybot indicates that this is necessary to avoid reset failures on BCS. v3: - Program RT_BASE before RT_BASE_UPPER so that the valid bit is turned off by the first write. (Chris) Bspec: 11388 Bspec: 33451 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-4-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* drm/i915: Add missing HDMI audio pixel clocks for gen12Kai Vehmanen2020-03-111-0/+4
| | | | | | | | | | | | Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz and 593.4/594Mhz. Add the missing rates and add logic to ignore them if running on older hardware. Bspec: 49333 Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200310162338.9387-1-kai.vehmanen@linux.intel.com
* drm/i915: Fix readout of PIPEGCMAXVille Syrjälä2020-03-091-1/+0
| | | | | | | | | | | PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can represent a value of 1.0 when the maximum we can store in the software LUT is 0.ffff. Clamp the value so that it gets saturated to the max the uapi supports. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200303173313.28117-9-ville.syrjala@linux.intel.com Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
* drm/i915/tgl: Add Wa_1409085225, Wa_14010229206Matt Atwood2020-03-021-0/+3
| | | | | | | | | | | | | | | | Disable Push Constant buffer addition for TGL. v2: typos, add additional Wa reference v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit message. Bspec: 52890 Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-3-jose.souza@intel.com
* drm/i915/tgl: Implement Wa_1409804808José Roberto de Souza2020-03-021-2/+3
| | | | | | | | | | | | | | | This workaround the CS not done issue on PIPE_CONTROL. v2: - replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits - shortened the name of the new bit BSpec: 52890 BSpec: 46218 Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com
* drm/i915: Set up PIPE_MISC truncate bit on tgl+Ville Syrjälä2020-02-271-0/+1
| | | | | | | | | | | | | Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to PIPE_MISC on tgl. Frob the new location. Bspec does still document the old bits as well, so I left the code for them as is until we get clarification from the hw folks on whether the old bits still do something useful. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200226163054.9509-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* drm/i915: remove ICP_PP_CONTROLLucas De Marchi2020-02-271-10/+0
| | | | | | | | | | | | | This register was placed in the middle of the PP_STATUS definition instead of together with the PP_CONTROL where it should. Since it's not used and there are no current plans to use it, just remove the definition. v2: remove the define rather than moving it. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190308232321.30168-1-lucas.demarchi@intel.com
* drm/i915/tgl: Add Wa_22010178259:tglMatt Roper2020-02-211-0/+1
| | | | | | | | | | | | | | | | | We need to explicitly set the TLB Request Timer initial value in the BW_BUDDY registers to 0x8 rather than relying on the hardware default. v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the correct bits during the rmw. (Jose) Bspec: 52890 Bspec: 50044 Fixes: 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init") Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219215655.2923650-1-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* drm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display initMatt Roper2020-02-201-0/+2
| | | | | | | | | | | | | | | | | On gen11 we only needed to program MBus credits into MBUS_ABOX_CTL during display initialization, but on gen12 we're now supposed to program the same values into MBUS_ABOX1_CTL and MBUS_ABOX2_CTL as well. v2: - Program registers with rmw to preserve contents of unrelated bits. - Switch to the new display uncore helpers. Bspec: 49213 Bspec: 50096 Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200204011032.582737-2-matthew.d.roper@intel.com Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
* drm/i915: Parametrize PFIT_PIPEVille Syrjälä2020-02-201-0/+1
| | | | | | | | Make the PFIT_PIPE stuff less ugly via parametrization. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212161738.28141-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/debugfs: Remove i915_energy_uJTvrtko Ursulin2020-02-081-2/+0
| | | | | | | | | | Last IGT user (intel_gpu_overlay) stopped using it in October 2019 so we are good to remove the file. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200206140725.10973-1-tvrtko.ursulin@linux.intel.com
* drm/i915: Implement Wa_1607090982Mika Kuoppala2020-02-071-0/+2
| | | | | | | | | | | SIMD16 with Src0 scalar might conflict between Src1/Src2 and cause GRF read issue. Workaround this issue by setting bit 14 in 0xe4f4 which will disable early read/src swap of Src0. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200207155138.30978-2-mika.kuoppala@linux.intel.com
* drm/i915: Disable tesselation clock gating on tgl A0Mika Kuoppala2020-02-071-0/+1
| | | | | | | | | | Disable TEDOP clock gating flow by programming 0x20A0[19] = 1 References: HSDES#1407928979 Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200207155138.30978-1-mika.kuoppala@linux.intel.com
* drm/i915: Introduce parameterized DBUF_CTLStanislav Lisovskiy2020-02-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Now start using parameterized DBUF_CTL instead of hardcoded, this would allow shorter access functions when reading or storing entire state. Tried to implement it in a MMIO_PIPE manner, however DBUF_CTL1 address is higher than DBUF_CTL2, which implies that we have to now subtract from base rather than add. v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR macros. Started to use _PICK construct as suggested by Matt Roper. v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice" in macro(Ville Syrjälä) - Introduced enum for enumerating DBUF slices(Ville Syrjälä) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200202230630.8975-5-stanislav.lisovskiy@intel.com
* drm/i915: Polish WM_LINETIME register stuffVille Syrjälä2020-01-311-7/+7
| | | | | | | | | | | Let's store the normal and IPS linetime watermarks individually, and while at it we'll pimp the register definitions as well. v2: Deal with gvt Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-2-ville.syrjala@linux.intel.com
* drm/i915: add extra slice common debug registersLionel Landwerlin2020-01-301-0/+2
| | | | | | | | | Could be helpful for debugging purposes. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200129181638.1528150-1-lionel.g.landwerlin@intel.com
* drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPTChris Wilson2020-01-291-1/+4
| | | | | | | | | | | | | | | | | Now that we have offline error capture and can reset an engine from inside an atomic context while also preserving the GPU state for post-mortem analysis, it is time to handle error interrupts thrown by the command parser. This provides a much, much faster mechanism for us to detect known problems than using heartbeats/hangchecks, and also provides a mechanism for when those are disabled. However, it is limited to problems the HW can detect in the CS and so not a complete solution for detecting lockups. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200128204318.4182039-2-chris@chris-wilson.co.uk
* drm/i915: add Wa_14010594013: icl,ehlMatt Atwood2020-01-161-0/+1
| | | | | | | | | | | | | | | | | The bspec tells us we need to set this bit to avoid potential underruns. v2: use new register write convention (Anshuman) add bspec 7386 ref. Bspec: 7386 Bspec: 33450 Bspec: 33451 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200114041128.11211-1-matthew.s.atwood@intel.com
* drm/i915/tgl: Add Wa_1409825376 to tglRadhakrishna Sripada2020-01-151-0/+3
| | | | | | | | | | | | | | | | Workaround database indicates we should disable VRH clockgating in pre-production hardware. V2: - Use REG_BIT macro - Update reference in commit message(Matt) Bspec: 52890 Bspec: 49424 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com
* drm/i915/gen11: Add additional pcode status valuesMatt Roper2020-01-141-0/+2
| | | | | | | | | | I don't think we've ever hit these new error codes, but they're documented in the gen11 pcode document, so we might as well add them to the handler. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200111014511.2988923-1-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* drm/i915/display/icl+: Do not program clockgatingJosé Roberto de Souza2020-01-081-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Talked with HW team and this is a left over, driver should not program clockgating, mg or dekel firmware is reponsible for any clockgating programing. Also removing the register and bits definition related to clockgating. v2: Added WARN_ON v3: Only calling icl_phy_set_clock_gating() on intel_ddi_pre_enable_hdmi for GEN11 v4: ICL should also not program clockgating (thanks Matt for catching this) BSpec issue: 20885 BSpec: 49292 BSpec: 21735 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200107170922.153612-1-jose.souza@intel.com
* drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media ↵Dhinakaran Pandiyan2020-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | engine Detect the modifier corresponding to media compression to enable display decompression for YUV and xRGB packed formats. A new modifier is added so that the driver can distinguish between media and render compressed buffers. Unlike render decompression, plane 6 and plane 7 do not support media decompression. v2: Fix checkpatch warnings on code style (Lucas) From DK: Separate modifier array for planes that cannot decompress media (Ville) v3: Support planar formats v4: Switch plane order v5: - Use format block descriptors to get CCS subsampling calculation right everywhere. - Extend the plane state normal view array to accommodate 4 color planes. - Use helpers to convert between main and CCS planes. v6: Add missing packed YUV formats to the MC format list. (Yang) v7: Align UV planes to tile-row size. Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Yang A Shi <yang.a.shi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231233756.18753-8-imre.deak@intel.com
* drm/i915: Add Wa_1407352427:icl,ehlMatt Roper2019-12-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | The workaround database now indicates we need to disable psdunit clock gating as well. v3: - Rebase on top of other workarounds that have landed. - Restrict cc:stable tag to 5.2+ since that's when ICL was first officially supported. Bspec: 32354 Bspec: 33450 Bspec: 33451 Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: stable@vger.kernel.org # v5.2+ Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231190713.1549533-1-matthew.d.roper@intel.com
* drm/i915/tgl: Extend Wa_1408615072 to tglMatt Roper2019-12-271-0/+3
| | | | | | | | | | | | | | | Although the workaround number and description are the same, the vsunit clock gate disable bit has moved to a new register and location on gen12. Bspec: 52890 Bspec: 52758 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-4-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
* drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehlMatt Roper2019-12-271-1/+3
| | | | | | | | | | | | | | | Workaround database indicates we should disable clock gating of both the vsunit and hsunit. Bspec: 33450 Bspec: 33451 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-3-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
* drm/i915/tgl: Gen-12 render decompressionDhinakaran Pandiyan2019-12-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gen-12 display decompression operates on Y-tiled compressed main surface. The CCS is linear and has 4 bits of metadata for each main surface cache line pair, a size ratio of 1:256. Gen-12 display decompression is incompatible with buffers compressed by earlier GPUs, so make use of a new modifier to identify gen-12 compression. Another notable change is that render decompression is supported on all planes except cursor and on all pipes. Start by adding render decompression support for [A,X]BGR888 pixel formats. v2: Fix checkpatch warnings (Lucas) v3: Rebase, disable color clear, styling changes and modify intel_tile_width_bytes and intel_tile_height to handle linear CCS v4: - Use format block descriptors and the i915 specific func to get the subsampling for each color plane. - Use helpers to convert between CCS and main planes. v5: - Fix subsampling returned by intel_fb_plane_get_subsampling() for the CCS plane of the first plane. v6: - Rebased on v2 of patch 4. v7: - Fix plane dimensions during FB check. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> (v6) Link: https://patchwork.freedesktop.org/patch/msgid/20191221120543.22816-7-imre.deak@intel.com
* drm/i915/tgl: Drop Wa#1178Matt Roper2019-12-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | The TGL workaround database no longer shows Wa #1178 (or anything similar under different workaround names/numbers) so we should be able to drop it. In fact Swati just discovered that applying this workaround is the root cause of some power well enable failures we've been seeing in CI (gitlab issue 498). Once we stop applying this WA, TGL no longer utilizes any of the special handling provided by icl_combo_phy_aux_power_well_ops so we can just drop back to using the standard hsw-style power well ops instead. v3: Drop now-unused _TGL_AUX_ANAOVRD1_C definition too. (Lucas) Closes: https://gitlab.freedesktop.org/drm/intel/issues/498 Fixes: deea06b47574 ("drm/i915/tgl: apply Display WA #1178 to fix type C dongles") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191213001511.678070-3-matthew.d.roper@intel.com
* drm/i915/dsb: Fix in mmio offset calculation of DSB instanceAnimesh Manna2019-12-111-1/+1
| | | | | | | | | | | | As the current usage is restricted to first DSB instance per pipe, so existing code could not catch the issue to calculate the mmio offset of different DSB instance per pipe. Corrected the offset calculation. Fixes: a6e58d9a2e04 ("drm/i915/dsb: Check DSB engine status.") Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191205123513.22603-1-animesh.manna@intel.com
* drm/i915/tgl: Program BW_BUDDY registers during display initMatt Roper2019-12-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gen12 can improve bandwidth efficiency by pairing up memory requests with similar addresses. We need to program the BW_BUDDY1 and BW_BUDDY2 registers according to the memory configuration during display initialization to take advantage of this capability. The magic numbers we program here feel like something that could definitely change on future platforms, so let's use a table-based programming scheme to make this easy to extend in the future. v2: - Add separate table for Wa_1409767108. (Stan) - Reorder structure reduce size by a word. Page mask can still be up to 28 bits (even though current values are small) so we should keep it as a u32, but just using a u8 for DRAM type instead of the actual enum type saves space. (Lucas, Ville) - Rename function to tgl_bw_buddy_init() to be more precise about what it does. (Lucas) Bspec: 49189 Bspec: 49218 Bspec: 52890 Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191205224848.76712-1-matthew.d.roper@intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
* drm/i915: Program SHPD_FILTER_CNT on CNP+Matt Roper2019-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | The bspec tells us 'Program SHPD_FILTER_CNT with the "500 microseconds adjusted" value before enabling hotplug detection' on CNP+. We haven't been touching this register at all thus far, but we should probably follow the bspec's guidance. The register also exists on LPT and SPT, but there isn't any specific guidance I can find on how we should be programming it there so let's leave it be for now. Bspec: 4342 Bspec: 31297 Bspec: 8407 Bspec: 49305 Bspec: 50473 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191127221314.575575-3-matthew.d.roper@intel.com
* drm/i915/tgl: Implement Wa_1604555607Michel Thierry2019-11-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). FF_MODE2 is part of the register state context, that's why it is implemented here. At TGL A0 stepping, FF_MODE2 register read back is broken, hence disabling the WA verification. v2: Rebased on top of the WA refactoring (Oscar) v3: Correctly add to ctx_workarounds_init (Michel) v4: uncore read is used [Tvrtko] Macros as used for MASK definition [Chris] v5: Skip the Wa_1604555607 verification [Ram] i915 ptr retrieved from engine. [Tvrtko] v6: Added wa_add as a wrapper for __wa_add [Chris] wa_add is directly called instead of new wrapper [tvrtko] BSpec: 19363 HSDES: 1604555607 Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Ramalingam C <ramlingam.c@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5] Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191128021005.3350-1-ramalingam.c@intel.com
* drm/i915: Fix frame start delay programmingVille Syrjälä2019-11-151-5/+7
| | | | | | | | | | | | | | | | | | | | Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on many platforms we're not doing anything at all here. Also we're forgetting about the PCH transcoder entirely. Add all the bit definitions for the various homes these bits have had throughout the years, and reset them all to zero. However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full readout+statecheck for this stuff. For now let's stick to the current logic and hope for the best. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024122138.25065-3-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
* Merge drm/drm-next into drm-intel-next-queuedJani Nikula2019-11-151-0/+10
|\ | | | | | | | | | | | | | | Backmerge to get dfce90259d74 ("Backmerge i915 security patches from commit 'ea0b163b13ff' into drm-next") and thus 100d46bd72ec ("Merge Intel Gen8/Gen9 graphics fixes from Jon Bloomfield."). Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * Backmerge i915 security patches from commit 'ea0b163b13ff' into drm-nextDave Airlie2019-11-141-0/+8
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | This backmerges the branch that ended up in Linus' tree. It removes all the changes for the rc6 patches from Linus' tree in favour of a patch that is based on a large refactor that occured. Otherwise it all looks good. Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * drm/i915/gen8+: Add RC6 CTX corruption WAImre Deak2019-11-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some circumstances the RC6 context can get corrupted. We can detect this and take the required action, that is disable RC6 and runtime PM. The HW recovers from the corrupted state after a system suspend/resume cycle, so detect the recovery and re-enable RC6 and runtime PM. v2: rebase (Mika) v3: - Move intel_suspend_gt_powersave() to the end of the GEM suspend sequence. - Add commit message. v4: - Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API change. v5: rebased on gem/gt split (Mika) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
| | * drm/i915: Lower RM timeout to avoid DSI hard hangsUma Shankar2019-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In BXT/APL, device 2 MMIO reads from MIPI controller requires its PLL to be turned ON. When MIPI PLL is turned off (MIPI Display is not active or connected), and someone (host or GT engine) tries to read MIPI registers, it causes hard hang. This is a hardware restriction or limitation. Driver by itself doesn't read MIPI registers when MIPI display is off. But any userspace application can submit unprivileged batch buffer for execution. In that batch buffer there can be mmio reads. And these reads are allowed even for unprivileged applications. If these register reads are for MIPI DSI controller and MIPI display is not active during that time, then the MMIO read operation causes system hard hang and only way to recover is hard reboot. A genuine process/application won't submit batch buffer like this and doesn't cause any issue. But on a compromised system, a malign userspace process/app can generate such batch buffer and can trigger system hard hang (denial of service attack). The fix is to lower the internal MMIO timeout value to an optimum value of 950us as recommended by hardware team. If the timeout is beyond 1ms (which will hit for any value we choose if MMIO READ on a DSI specific register is performed without PLL ON), it causes the system hang. But if the timeout value is lower than it will be below the threshold (even if timeout happens) and system will not get into a hung state. This will avoid a system hang without losing any programming or GT interrupts, taking the worst case of lowest CDCLK frequency and early DC5 abort into account. Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
| | * drm/i915: Add gen9 BCS cmdparsingJon Bloomfield2019-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For gen9 we enable cmdparsing on the BCS ring, specifically to catch inadvertent accesses to sensitive registers Unlike gen7/hsw, we use the parser only to block certain registers. We can rely on h/w to block restricted commands, so the command tables only provide enough info to allow the parser to delineate each command, and identify commands that access registers. Note: This patch deliberately ignores checkpatch issues in favour of matching the style of the surrounding code. We'll correct the entire file in one go in a later patch. v3: rebase (Mika) v4: Add RING_TIMESTAMP registers to whitelist (Jon) Signed-off-by: Jon Bloomfield <jon.bloomfield@intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tyler Hicks <tyhicks@canonical.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris.p.wilson@intel.com>
| * | drm/i915/gen8+: Add RC6 CTX corruption WAImre Deak2019-11-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some circumstances the RC6 context can get corrupted. We can detect this and take the required action, that is disable RC6 and runtime PM. The HW recovers from the corrupted state after a system suspend/resume cycle, so detect the recovery and re-enable RC6 and runtime PM. v2: rebase (Mika) v3: - Move intel_suspend_gt_powersave() to the end of the GEM suspend sequence. - Add commit message. v4: - Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API change. v5: - Rebased on latest upstream gt_pm refactoring. v6: - s/i915_rc6_/intel_rc6_/ - Don't return a value from i915_rc6_ctx_wa_check(). v7: - Rebased on latest gt rc6 refactoring. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> [airlied: pull this later version of this patch into drm-next to make resolving the conflict mess easier.] Signed-off-by: Dave Airlie <airlied@redhat.com>
* | | drm/i915/gt: Refactor mocs loops into single control macroChris Wilson2019-11-141-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We repeatedly (and more so in future) use the same looping construct over the mocs definition table to setup the register state. Refactor the loop construct into a reusable macro. add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217) Function old new delta intel_mocs_init_engine.cold - 71 +71 offset - 28 +28 __func__ 17273 17287 +14 intel_mocs_init 143 113 -30 mocs_register.isra 91 - -91 intel_mocs_init_engine 503 294 -209 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191112223600.30993-3-chris@chris-wilson.co.uk
* | | drm/i915/display/dsi: Add support to pipe DJosé Roberto de Souza2019-11-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding pipe D support to DSI transcoder. Not adding it for EDP transcoder code paths as only TGL has 4 pipes and it do not have a EDP transcoder. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191107214559.77087-2-jose.souza@intel.com
* | | drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definitionJosé Roberto de Souza2019-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking one bit from EDP/DSI Input Select. Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191107214559.77087-1-jose.souza@intel.com
* | | drm/i915/dsi: Define command mode registersVandita Kulkarni2019-11-121-8/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding all the register definitions needed for mipi dsi command mode. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191111111029.9126-2-vandita.kulkarni@intel.com
* | | drm/i915: Expose C8 on VLV/CHV sprite planesVille Syrjälä2019-11-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | VLV/CHV sprite planes also support the C8 format. Let's expose that. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-5-ville.syrjala@linux.intel.com
* | | drm/i915: Add missing 10bpc formats for pipe B sprites on CHVVille Syrjälä2019-11-041-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats. On VLV and CHV pipe A/C these are only supported by the primary plane. Add the require bits to expose the new formats. v2: Reorder the formats for consistency Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-4-ville.syrjala@linux.intel.com
* | | drm/i915: Expose alpha formats on VLV/CHV primary planesVille Syrjälä2019-11-041-0/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | Currently we expose VLV/CHV alpha blending only on the sprite planes, but the primary planes can do it as well. Let's flip it on. v2: Rebase due to fp16 landing Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-3-ville.syrjala@linux.intel.com
* | drm/i915/tgl: Add gam instdoneMika Kuoppala2019-10-301-0/+1
| | | | | | | | | | | | | | | | | | | | This has been asked from us already. Prepare for the next time. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191029163841.5224-2-mika.kuoppala@linux.intel.com
* | drm/i915/tgl: Add SFC instdone to error stateMika Kuoppala2019-10-301-0/+3
| | | | | | | | | | | | | | | | | | | | On debugging media workload hangs, sfc instdone might prove useful in future. Be prepared. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191029163841.5224-1-mika.kuoppala@linux.intel.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 08:56:57 +0000