summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon.h
Commit message (Collapse)AuthorAgeFilesLines
...
| | * drm/radeon: Make si_support and cik_support parameters always availableMichel Dänzer2017-06-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow amdgpu-pro / other out-of-tree amdgpu builds to make use of these options for using the out-of-tree amdgpu driver instead of the in-tree radeon driver in a clean way. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
| | * drm/radeon: Add module param to control SI supportFelix Kuehling2017-06-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If AMDGPU supports SI, add a module parameter to control SI support in radeon. It's on by default in radeon, while it will be off by default in AMDGPU as long as SI support is experimental. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com>
| | * drm/radeon: Cleanup pageflipping IRQ handling for evergreen, siLyude2017-05-241-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as the previous patch, but for pageflipping now. This also lets us clear up the copy paste for vblank/vline IRQs. Changes since v1: - Preserve the order all registers are written back Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/radeon: Cleanup HDMI audio interrupt handling for evergreenLyude2017-05-241-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as the previous patch, but now for handling HDMI audio interrupts. Changes since v1: - Preserve the order we write back all registers Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/radeon: Cleanup display interrupt handling for evergreen, siLyude2017-05-241-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code here is really, really bad. A huge amount of it looks to be copy pasted, it has some weird hatred of arrays and code sharing, switch cases everywhere for things that really don't need them, and it makes the file seem immensely more complex then it actually is. This is a pain for maintanence, and is vulnerable to more weird irq handling bugs. So, let's start cleaning this up a bit. Modify all of the IRQ handlers for evergreen/si so that they just use for loops. As well, we add a helper function radeon_irq_kms_set_irq_n_enabled(), whose purpose is just to update the state of registers that enable/disable interrupts while printing any changes to the set of enabled interrupts to the kernel log. Note in this commit, since vblank/vline irq acking is intertwined with page flip irq acking, we can't cut out all of the copy paste in evergreen/si_irq_ack() just yet. Changes since v1: - Preserve order we write back all registers Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/radeon: Add module param to control CIK supportFelix Kuehling2017-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If AMDGPU supports CIK, add a module parameter to control CIK support in radeon. It's off by default in radeon, while it will be on by default in AMDGPU. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/radeon: fix include notation and remove -Iinclude/drm flagMasahiro Yamada2017-05-171-5/+5
| |/ | | | | | | | | | | | | | | | | | | Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-14-git-send-email-yamada.masahiro@socionext.com
* / sched/wait: Rename wait_queue_t => wait_queue_entry_tIngo Molnar2017-06-201-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | Rename: wait_queue_t => wait_queue_entry_t 'wait_queue_t' was always a slight misnomer: its name implies that it's a "queue", but in reality it's a queue *entry*. The 'real' queue is the wait queue head, which had to carry the name. Start sorting this out by renaming it to 'wait_queue_entry_t'. This also allows the real structure name 'struct __wait_queue' to lose its double underscore and become 'struct wait_queue_entry', which is the more canonical nomenclature for such data types. Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
* drm/radeon: Maintain prime import/export refcount for BOsChristopher James Halse Rogers2017-04-071-0/+1
| | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>Joe Perches2017-03-291-1/+2
| | | | | | | | | | | | Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* dma-buf: Rename struct fence to dma_fenceChris Wilson2016-10-251-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I plan to usurp the short name of struct fence for a core kernel struct, and so I need to rename the specialised fence/timeline for DMA operations to make room. A consensus was reached in https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html that making clear this fence applies to DMA operations was a good thing. Since then the patch has grown a bit as usage increases, so hopefully it remains a good thing! (v2...: rebase, rerun spatch) v3: Compile on msm, spotted a manual fixup that I broke. v4: Try again for msm, sorry Daniel coccinelle script: @@ @@ - struct fence + struct dma_fence @@ @@ - struct fence_ops + struct dma_fence_ops @@ @@ - struct fence_cb + struct dma_fence_cb @@ @@ - struct fence_array + struct dma_fence_array @@ @@ - enum fence_flag_bits + enum dma_fence_flag_bits @@ @@ ( - fence_init + dma_fence_init | - fence_release + dma_fence_release | - fence_free + dma_fence_free | - fence_get + dma_fence_get | - fence_get_rcu + dma_fence_get_rcu | - fence_put + dma_fence_put | - fence_signal + dma_fence_signal | - fence_signal_locked + dma_fence_signal_locked | - fence_default_wait + dma_fence_default_wait | - fence_add_callback + dma_fence_add_callback | - fence_remove_callback + dma_fence_remove_callback | - fence_enable_sw_signaling + dma_fence_enable_sw_signaling | - fence_is_signaled_locked + dma_fence_is_signaled_locked | - fence_is_signaled + dma_fence_is_signaled | - fence_is_later + dma_fence_is_later | - fence_later + dma_fence_later | - fence_wait_timeout + dma_fence_wait_timeout | - fence_wait_any_timeout + dma_fence_wait_any_timeout | - fence_wait + dma_fence_wait | - fence_context_alloc + dma_fence_context_alloc | - fence_array_create + dma_fence_array_create | - to_fence_array + to_dma_fence_array | - fence_is_array + dma_fence_is_array | - trace_fence_emit + trace_dma_fence_emit | - FENCE_TRACE + DMA_FENCE_TRACE | - FENCE_WARN + DMA_FENCE_WARN | - FENCE_ERR + DMA_FENCE_ERR ) ( ... ) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161025120045.28839-1-chris@chris-wilson.co.uk
* drm/radeon: Provide page_flip_target hookMichel Dänzer2016-08-101-0/+1
| | | | | | | | | | Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying radeon_flip_work_func considerably. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* dma-buf/fence: make fence context 64 bit v2Christian König2016-06-021-1/+1
| | | | | | | | | | | | | | | | | | | Fence contexts are created on the fly (for example) by the GPU scheduler used in the amdgpu driver as a result of an userspace request. Because of this userspace could in theory force a wrap around of the 32bit context number if it doesn't behave well. Avoid this by increasing the context number to 64bits. This way even when userspace manages to allocate a billion contexts per second it takes more than 500 years for the context number to wrap around. v2: fix printf formats as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1464786612-5010-2-git-send-email-deathsimple@vodafone.de
* drm/radeon: handle more than 10 UVD sessionsArindam Nath2016-05-041-3/+6
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support for loading new UVD fwArindam Nath2016-05-041-0/+1
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNCMichel Dänzer2016-05-041-2/+3
| | | | | | | | | | | | | | When this flag is set, we program the hardware to execute the flip during horizontal blank (i.e. for the next scanline) instead of during vertical blank (i.e. for the next frame). Currently this is only supported on ASICs which have a page flip completion interrupt (>= R600), and only if the use_pflipirq parameter has value 2 (the default). Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: delete unused struct member suspend from radeon_deviceNils Wallménius2016-05-021-1/+0
| | | | | Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: hard reset r600 and newer GPU when hibernating.Jérome Glisse2016-05-021-1/+2
| | | | | | | | | | | | Some GPU block like UVD and VCE require hard reset to be properly resume if there is no real powerdown of the asic like during various hibernation step. This patch perform such hard reset. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: allow to force hard GPU reset.Jérome Glisse2016-05-021-2/+2
| | | | | | | | | | | | | In some cases, like when freezing for hibernation, we need to be able to force hard reset even if no engine are stuck. This patch add a bool option to current asic reset callback to allow to force hard reset on asic that supports it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add driver option to disable vce block.Jérome Glisse2016-05-021-0/+1
| | | | | | | | | | | Quite few suspend/hibernation bugs are related to this block. Add an option to disable those as a work around. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add driver option to disable uvd block.Jérome Glisse2016-05-021-0/+1
| | | | | | | | | | | Quite few suspend/hibernation bugs are related to this block. Add an option to disable those as a work around. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a vce flag to know if need to initialize vce or not.Jérome Glisse2016-05-021-0/+1
| | | | | | | | | | This will later on serve for module option to disable vce. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Avoid double gpu reset by adding a timeout on IB ring tests.Matthew Dawson2016-02-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the radeon driver resets a gpu, it attempts to test whether all the rings can successfully handle an IB. If these rings fail to respond, the process will wait forever. Another gpu reset can't happen at this point, as the current reset holds a lock required to do so. Instead, make all the IB tests run with a timeout, so the system can attempt to recover in this case. While this doesn't fix the underlying issue with card resets failing, it gives the system a higher chance of recovering. These timeouts have been confirmed to help both a Tathi and Hawaii card recover after a gpu reset. This also adds a new function, radeon_fence_wait_timeout, that behaves like fence_wait_timeout. It is used instead of fence_wait_timeout as it continues to work during a reset. radeon_fence_wait is changed to be implemented using this function. V2: - Changed the timeout to 1s, as the default 10s from radeon_wait_timeout was too long. A timeout of 100ms was tested and found to be too short. - Changed radeon_fence_wait_timeout to behave more like fence_wait_timeout. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Matthew Dawson <matthew@mjdsystems.ca> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: cleaned up VCO output settings for DP audioSlava Grigorev2016-01-271-1/+1
| | | | | | | | | | This is preparation for the fixes in the following patches. Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* Merge branch 'drm-next-4.5' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2015-12-231-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next [airlied: fixup build problems on arm - added errno.h include] * 'drm-next-4.5' of git://people.freedesktop.org/~agd5f/linux: (152 commits) amd/powerplay: fix copy paste typo in hardwaremanager.c amd/powerplay: disable powerplay by default initially amd/powerplay: don't enable ucode fan control if vbios has no fan table drm/amd/powerplay: show gpu load when print gpu performance for Cz. (v2) drm/amd/powerplay: check whether need to enable thermal control. (v2) drm/amd/powerplay: add point check to avoid NULL point hang. drm/amdgpu/powerplay: Program a calculated value as Deep Sleep clock. drm/amd/powerplay: Don't return an error if fan table is missing drm/powerplay/hwmgr: log errors in tonga_hwmgr_backend_init drm/powerplay: add debugging output to processpptables.c drm/powerplay: add debugging output to tonga_processpptables.c amd/powerplay: Add structures required to report configuration change amd/powerplay: Fix get dal power level amd\powerplay Implement get dal power level drm/amd/powerplay: display gpu load when print performance for tonga. drm/amdgpu/powerplay: enable sysfs and debugfs interfaces late drm/amd/powerplay: move shared function of vi to hwmgr. (v2) drm/amd/powerplay: check whether enable dpm in powerplay. drm/amd/powerplay: fix bug that dpm funcs in debugfs/sysfs missing. drm/amd/powerplay: fix boolreturn.cocci warnings ...
| * drm/radeon: Fix "slow" audio over DP on DCE8+Slava Grigorev2015-12-181-0/+1
| | | | | | | | | | | | | | | | DP audio is derived from the dfs clock. Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon: constify radeon_asic_ring structuresJulia Lawall2015-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | The radeon_asic_ring structures are never modified, so declare them as const. Done with the help of Coccinelle. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: Retry DDC probing on DVI on failure if we got an HPD interruptLyude2015-12-041-1/+1
|/ | | | | | | | | | | | | | | | | | | | | HPD signals on DVI ports can be fired off before the pins required for DDC probing actually make contact, due to the pins for HPD making contact first. This results in a HPD signal being asserted but DDC probing failing, resulting in hotplugging occasionally failing. This is somewhat rare on most cards (depending on what angle you plug the DVI connector in), but on some cards it happens constantly. The Radeon R5 on the machine used for testing this patch for instance, runs into this issue just about every time I try to hotplug a DVI monitor and as a result hotplugging almost never works. Rescheduling the hotplug work for a second when we run into an HPD signal with a failing DDC probe usually gives enough time for the rest of the connector's pins to make contact, and fixes this issue. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <cpaul@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: don't try to recreate sysfs entries on resumeAlex Deucher2015-10-231-0/+1
| | | | | | | | Fixes a harmless error message caused by: 51a4726b04e880fdd9b4e0e58b13f70b0a68a7f5 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: remove obsolete kfd_bo from radeon_deviceOded Gabbay2015-06-161-1/+0
| | | | Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
* radeon: Deinline indirect register accessor functionsDenys Vlasenko2015-05-281-197/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch deinlines indirect register accessor functions. These functions perform two mmio accesses, framed by spin lock/unlock. Spin lock/unlock by itself takes more than 50 cycles in ideal case (if lock is exclusively cached on current CPU). With this .config: http://busybox.net/~vda/kernel_config, after uninlining these functions have sizes and callsite counts as follows: r600_uvd_ctx_rreg: 111 bytes, 4 callsites r600_uvd_ctx_wreg: 113 bytes, 5 callsites eg_pif_phy0_rreg: 106 bytes, 13 callsites eg_pif_phy0_wreg: 108 bytes, 13 callsites eg_pif_phy1_rreg: 107 bytes, 13 callsites eg_pif_phy1_wreg: 108 bytes, 13 callsites rv370_pcie_rreg: 111 bytes, 21 callsites rv370_pcie_wreg: 113 bytes, 24 callsites r600_rcu_rreg: 111 bytes, 16 callsites r600_rcu_wreg: 113 bytes, 25 callsites cik_didt_rreg: 106 bytes, 10 callsites cik_didt_wreg: 107 bytes, 10 callsites tn_smc_rreg: 106 bytes, 126 callsites tn_smc_wreg: 107 bytes, 116 callsites eg_cg_rreg: 107 bytes, 20 callsites eg_cg_wreg: 108 bytes, 52 callsites Functions r100_mm_rreg() and r100_mm_rreg() have a fast path and a locked (slow) path. This patch deinlines only slow path. r100_mm_rreg_slow: 78 bytes, 2083 callsites r100_mm_wreg_slow: 81 bytes, 3570 callsites Reduction in code size is more than 65,000 bytes: text data bss dec hex filename 85740176 22294680 20627456 128662312 7ab3b28 vmlinux.before 85674192 22294776 20627456 128598664 7aa4288 vmlinux Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: stop using addr to check for BO moveChristian König2015-05-281-1/+3
| | | | | | | | | | It is theoretically possible that a swapped out BO gets the same GTT address, but different backing pages while being swapped in. Instead just use another VA state to note updated areas. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Use DECLARE_BITMAPJoe Perches2015-05-261-1/+1
| | | | | | | Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add VCE 1.0 support v4Christian König2015-05-261-0/+1
| | | | | | | | | | | Initial support for VCE 1.0 using newest firmware. v2: rebased v3: fix for TN v4: fix FW size calculation Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: implement si_set_vce_clocks v2Christian König2015-05-261-0/+7
| | | | | | | | | For setting clocks with VCE v1.0 v2: (chk) rebased on current tree Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework VCE FW size calculationChristian König2015-05-261-2/+0
| | | | | | | | Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a GPU reset counter queryable by userspaceMarek Olšák2015-05-261-0/+1
| | | | | | | | | Userspace will be able to tell whether a GPU reset occured by comparing an old referece value of the counter with a new value. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: stop trying to suspend UVD sessionsChristian König2015-05-071-1/+0
| | | | | | | | Saving the current UVD state on suspend and restoring it on resume just doesn't work reliable. Just close cleanup all sessions on suspend. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: allow creating overlapping userptrsChristian König2015-04-131-1/+1
| | | | | | | | | Similar to the Intel implementation, but instead of just falling back to a global linear list when we have an overlapping userptr request we accumulate all overlapping userptrs in a local list. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge tag 'imx-drm-fixes-2015-03-31' of ↵Dave Airlie2015-04-081-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.pengutronix.de/git/pza/linux into drm-next imx-drm limit fixes Fix IPU IC downscaler to its hardware limitation of 4:1 and the IPU DI pixel clock divider integer part to 8-bit. * tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: turns out the IPU can only downsize 4:1 gpu: ipu-v3: limit pixel clock divider to 8-bits drm/radeon: programm the VCE fw BAR as well drm/radeon: always dump the ring content if it's available radeon: Do not directly dereference pointers to BIOS area. drm/radeon/dpm: fix 120hz handling harder
| * drm/radeon/dpm: fix 120hz handling harderAlex Deucher2015-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Need to expand the check to handle short circuiting if the selected state is the same as current state. bug: https://bugs.freedesktop.org/show_bug.cgi?id=87796 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | drm/radeon: add DisplayPort MST support (v2)Dave Airlie2015-03-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial DP 1.2 MST support to radeon, on CAYMAN and up in theory. This is off by default. v2: agd5f: - add UNIPHY3 offsets - move atom cmd table code into atombios_encoders.c - whitespace cleanup - replace some magic numbers with proper defines Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | radeon: introduce a dp_work handlerDave Airlie2015-03-191-0/+1
| | | | | | | | | | | | | | | | This is to be called on short HPD irqs, just introduce the basic infrastructure for it. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: program auxch directly (v2)Dave Airlie2015-03-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The atombios tables have an unfortunate restriction on only being able to write 12 bytes, MST really wants 16-bytes here, and since the hw can do it, we should just write directly to it. This uses a module option to allow for it now, and maybe we should provide the old code as a fallback for a while. v2: (agd5f) - move registers to a proper register header - only enable on DCE5+ - enable by default on DCE5+ - Switch pad to aux mode before using it - reformat instance handling to better match the rest of the driver Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: add new callback for info ioctl register accessorAlex Deucher2015-03-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This adds a callback for each asic family to determine what registers are allowed to be read back via the info ioctl. The idea here is to allow usermode to query things like GPU status registers or GPU harvest registers for profiling and determining the gfx config. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon/dpm: add new callbacks to get the current sclk/mclkAlex Deucher2015-03-191-0/+4
|/ | | | | | | Needed to to expose the current clocks via the INFO ioctl. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'master' of ↵Dave Airlie2015-01-291-3/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next This backmerges drm-fixes into drm-next mainly for the amdkfd stuff, I'm not 100% confident, but it builds and the amdkfd folks can fix anything up. Signed-off-by: Dave Airlie <airlied@redhat.com> Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
| * drm/radeon: Remove rdev->gart.pages_addr arrayMichel Dänzer2015-01-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | radeon_vm_map_gart can use rdev->gart.pages_entry instead. Also move the masking of the page address to radeon_vm_map_gart from its callers. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: Split off gart_get_page_entry ASIC hook from set_page_entryMichel Dänzer2015-01-221-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | get_page_entry calculates the GART page table entry, which is just written to the GART page table by set_page_entry. This is a prerequisite for the following fix. Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: make MMU_NOTIFIER optionalRob Clark2015-01-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | In cases where MMU_NOTIFIER is not available, userptr will not be available. Similar to i915, although not making an exception for CAP_SYS_ADMIN. The proposed userspace patches for userptr seem to handle the fall- back properly, so a userptr-less kernel should not be a problem. Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 13:20:27 +0000