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path: root/drivers/gpu/drm
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* drm/amd/powerplay: set VCN1 pg only for sienna_cichlidJiansong Chen2020-07-151-6/+14
* drm/amd/display: add DC support for navy flounderBhawanpreet Lakha2020-07-153-2/+12
* drm/amdgpu: support athub cg setting for navy_flounderJiansong Chen2020-07-151-0/+1
* drm/amdgpu: enable GFX clock gating for navy_flounderJiansong Chen2020-07-151-1/+4
* drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang2020-07-151-2/+4
* drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang2020-07-151-1/+2
* drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang2020-07-151-2/+2
* drm/amdgpu: enable cp_fw_write_wait for navy_flounderJiansong Chen2020-07-151-0/+1
* drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang2020-07-151-0/+2
* drm/amdgpu: add navy_flounder vcn firmware supportBoyuan Zhang2020-07-151-0/+8
* drm/amdgpu/gfx10: add gc golden setting for navy_flounderJiansong Chen2020-07-151-0/+48
* drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd supportChengming Gui2020-07-151-0/+1
* drm/amdkfd: Support navy_flounder KFDChengming Gui2020-07-156-0/+24
* drm/amdgpu: use front door firmware loading for navy_flounderJiansong Chen2020-07-151-2/+1
* drm/amdgpu: add psp block for navy_flounderJiansong Chen2020-07-151-0/+5
* drm/amdgpu: add psp support for navy_flounderJiansong Chen2020-07-152-4/+16
* drm/amdgpu: add smu block for navy_flounderJiansong Chen2020-07-151-0/+3
* drm/amdgpu/powerplay: add smu support for navy_flounderJiansong Chen2020-07-153-1/+16
* drm/amdgpu: add gmc cg support for navy_flounderJiansong Chen2020-07-152-2/+5
* drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen2020-07-151-1/+2
* drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou2020-07-151-0/+9
* drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen2020-07-151-0/+2
* drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen2020-07-152-2/+19
* drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen2020-07-152-0/+5
* drm/amdgpu: add ih ip block for navy_flounderJiansong Chen2020-07-152-0/+2
* drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen2020-07-152-6/+13
* drm/amdgpu: add common ip block for navy_flounderJiansong Chen2020-07-151-0/+3
* drm/amdgpu: add support on mmhub for navy_flounderJiansong Chen2020-07-151-0/+5
* drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen2020-07-151-0/+1
* drm/amdgpu/soc15: add support for navy_flounderJiansong Chen2020-07-151-0/+7
* drm/amdgpu/gfx10: add clockgating support for navy_flounderJiansong Chen2020-07-151-0/+1
* drm/amdgpu/gmc10: add navy_flounder supportJiansong Chen2020-07-151-0/+3
* drm/amdgpu/gfx10: add support for navy_flounder firmwareJiansong Chen2020-07-151-0/+10
* drm/amdgpu: set asic family and ip blocks for navy_flounderJiansong Chen2020-07-151-0/+1
* drm/amdgpu: set fw load type for navy_flounderJiansong Chen2020-07-151-1/+2
* drm/amdgpu: add navy_flounder gpu info firmwareJiansong Chen2020-07-151-0/+4
* drm/amdgpu: add navy_flounder asic typeJiansong Chen2020-07-151-0/+1
* drm/amdgpu: expand to add multiple trap event irq idHuang Rui2020-07-151-26/+41
* drm/amd/sriov skip vcn powergating and dec_ring_testJack Zhang2020-07-152-5/+20
* drm/amdgpu: correct ta header v2 ucode init start addressJohn Clements2020-07-151-1/+3
* drm/amd/sriov porting sriov cap to vcn3.0Jack Zhang2020-07-151-32/+318
* drm/amd/sriov add mmsch_v3 interfaceJack Zhang2020-07-151-0/+130
* drm/amdgpu: optimize rlcg write for gfx_v10Jack Zhang2020-07-151-7/+19
* drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang2020-07-151-1/+8
* drm/amd/powerplay: drop unused code around thermal range settingEvan Quan2020-07-156-113/+3
* drm/amd/powerplay: maximum the code sharing on thermal irq settingEvan Quan2020-07-151-4/+12
* drm/amd/powerplay: sort the call flow on temperature ranges retrievingEvan Quan2020-07-157-20/+41
* drm/amd/powerplay: cache the software_shutdown_tempEvan Quan2020-07-154-0/+13
* drm/amd/powerplay: correct Sienna Cichlid temperature limit settingsEvan Quan2020-07-151-4/+13
* drm/amd/powerplay: correct Navi1X temperature limit settingsEvan Quan2020-07-153-9/+18