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| * drm/v3d: Add a note about OOM vs FLDONE, which may be racing on v3.3.Eric Anholt2019-04-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | We deref v3d->bin_job in the work handler, but v3d->bin_job doesn't actually hold a ref on the job. v2: typo fix FRDONE -> FLDONE Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20190313235211.28995-1-eric@anholt.net Reviewed-by: Dave Emett <david.emett@broadcom.com>
| * drm/v3d: fix a NULL vs error pointer mixupDan Carpenter2019-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | The drm_gem_shmem_create() returns error pointers and v3d_bo_create() is also supposed to return error pointers. Fixes: 40609d4820b2 ("drm/v3d: Use the new shmem helpers to reduce driver boilerplate.") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20190321062731.GC21489@kadam
| * drm/vc4: Make sure to emit a tile coordinates between two MSAA loads.Eric Anholt2019-04-011-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The HW only executes a load once the tile coordinates packet happens, and only tracks one at a time, so by emitting our two MSAA loads back to back we would end up with an undefined color or Z buffer. Fixes dEQP-EGL.functional.render.multi_context.gles2.rgb888_window Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206232550.12012-1-eric@anholt.net
| * drm/syncobj: add timeline signal ioctl for syncobj v5Chunming Zhou2019-04-013-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: individually allocate chain array, since chain node is free independently. v3: all existing points must be already signaled before cpu perform signal operation, so add check condition for that. v4: remove v3 change and add checking to prevent out-of-order v5: unify binary and timeline Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Cc: Tobias Hector <Tobias.Hector@amd.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295792/?series=58813&rev=1
| * drm/syncobj: add transition iotcls between binary and timeline v2Chunming Zhou2019-04-013-0/+78
| | | | | | | | | | | | | | | | | | | | | | we need to import/export timeline point. v2: unify to one transfer ioctl Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295790/?series=58813&rev=1
| * drm/syncobj: use the timeline point in drm_syncobj_find_fence v4Christian König2019-04-011-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | Implement finding the right timeline point in drm_syncobj_find_fence. v2: return -EINVAL when the point is not submitted yet. v3: fix reference counting bug, add flags handling as well v4: add timeout for find fence Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295786/?series=58813&rev=1
| * drm/syncobj: add timeline payload query ioctl v6Chunming Zhou2019-04-013-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | user mode can query timeline payload. v2: check return value of copy_to_user v3: handle querying entry by entry v4: rebase on new chain container, simplify interface v5: query last signaled timeline point, not last point. v6: add unorder point check Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Cc: Tobias Hector <Tobias.Hector@amd.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295784/?series=58813&rev=1
| * drm/syncobj: add support for timeline point wait v8Chunming Zhou2019-04-013-29/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | points array is one-to-one match with syncobjs array. v2: add seperate ioctl for timeline point wait, otherwise break uapi. v3: userspace can specify two kinds waits:: a. Wait for time point to be completed. b. and wait for time point to become available v4: rebase v5: add comment for xxx_WAIT_AVAILABLE v6: rebase and rework on new container v7: drop _WAIT_COMPLETED, it is the default anyway v8: correctly handle garbage collected fences Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Cc: Tobias Hector <Tobias.Hector@amd.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295782/?series=58813&rev=1
| * drm/syncobj: add new drm_syncobj_add_point interface v4Christian König2019-04-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the dma_fence_chain object to create a timeline of fence objects instead of just replacing the existing fence. v2: rebase and cleanup v3: fix garbage collection parameters v4: add unorder point check, print a warn calltrace Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/295780/?series=58813&rev=1
| * drm: fallback to dma_alloc_coherent when memory encryption is activeChristian König2019-04-011-0/+7
| | | | | | | | | | | | | | | | | | We can't just map any randome page we get when memory encryption is active. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.kernel.org/patch/10850833/
| * drm/sun4i: hdmi: add support for ddc-i2c-bus propertyMans Rullgard2019-04-012-3/+38
| | | | | | | | | | | | | | | | | | | | Sometimes it is desirabled to use a separate i2c controller for ddc access. This adds support for the ddc-i2c-bus property of the hdmi-connector node, using the specified controller if provided. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190328130249.19356-1-mans@mansr.com
| * drm/stm: add sleep power managementYannick Fertré2019-04-013-0/+62
| | | | | | | | | | | | | | | | | | Implements system sleep power management ops. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Acked-by: Philippe Cornu <philippe.cornu@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/1553156120-13851-1-git-send-email-yannick.fertre@st.com
| * drm/stm: dw_mipi_dsi-stm: add sleep power managementYannick Fertré2019-04-011-0/+28
| | | | | | | | | | | | | | | | | | Implements system sleep power management ops. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Acked-by: Philippe Cornu <philippe.cornu@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/1553156033-13792-1-git-send-email-yannick.fertre@st.com
| * drm: rockchip: introduce rk3066 hdmiZheng Yang2019-03-316-0/+1117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3066 HDMI TX serves as interface between a LCD Controller and a HDMI bus. A HDMI TX consists of one HDMI transmitter controller and one HDMI transmitter PHY. The interface has three (3) 8-bit data channels which can be configured for a number of bus widths (8/10/12/16/20/24-bit) and different video formats (RGB, YCbCr). Features: HDMI version 1.4a, HDCP revision 1.4 and DVI version 1.0 compliant transmitter. Supports DTV resolutions from 480i to 1080i/p HD. Master I2C interface for a DDC connection. HDMI TX supports multiple power save modes. The HDMI TX input can switch between LCDC0 and LCDC1. (Sound support is not included in this patch) Signed-off-by: Zheng Yang <zhengyang@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20190330095639.14626-2-jbx6244@gmail.com
| * drm/rockchip: vop: Support dithering to RGB666Urja Rannikko2019-03-303-4/+41
| | | | | | | | | | | | | | | | | | | | Splits out the dither register bits and introduces the same config enumerations as in the rockchip kernel tree. Tested to fix the banding on my ASUS C201. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20190318154412.26994-1-urjaman@gmail.com
* | Merge commit 'refs/for-upstream/mali-dp' of git://linux-arm.org/linux-ld ↵Dave Airlie2019-04-0313-30/+1982
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next This pull requests adds initial Mali D71 support into the Arm "komeda" DRM driver. The code has been reviewed at the end of last year, I just been too slow with pushing it into mainline. Since it started baking in linux-next we had a kbuild-bot issue raised and one from Joe Perches on the MAINTAINERS entry, for which I'm including fixes here. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Liviu Dudau <Liviu.Dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190401192833.GW21747@e110455-lin.cambridge.arm.com
| * | arm/komeda: Compile komeda_debugfs_init() only if CONFIG_DEBUG_FS is enabledLiviu Dudau2019-04-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't call this function if CONFIG_DEBUG_FS is not defined, but we should not be compiling it either, as the declaration of the debugfs core functions is not included. Reported by the kbuild test robot. Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add debugfs node "register" for register dumpjames qian wang (Arm Technology China)2019-04-015-0/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a debugfs node "register" and entry function dump_register to dev/pipeline/component to register dump, then user can read "/sys/kernel/debug/komeda/register" to get the register values via these chip function. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> [Added the d71_layer_dump() function that was in a previous commit] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add irq handlingjames qian wang (Arm Technology China)2019-04-016-2/+346
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Added irq_handler/irq_enable/irq_disable to komeda_dev_func, then the Komeda-CORE can control the HW irq via these chip function. 2. Install irq and register irq_handler to system by DRM, so once the IRQ coming, the handling sequence is: komeda_kms_irq_handler(int irq, void *data) /* step 1. call into the CHIP to recognize event */ mdev->funcs->irq_handler(mdev, &evts); /* step 2. notify the crtc to handle the events */ for (i = 0; i < kms->n_crtcs; i++) komeda_crtc_handle_event(&kms->crtcs[i], &evts); v2: - Move get IRQ number into this change. - Enable irq before drm_dev_register. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add komeda_assemble_pipelinesjames qian wang (Arm Technology China)2019-04-013-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | komeda_accemble_pipelines is for: 1. Verifing the component->supported_inputs according to the pipeline->avail_components. 2. Generating component->supported_outputs. v2: Lower the debug message of komeda_component_dump to DRM_DEBUG. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add D71 improc and timing_ctrlrjames qian wang (Arm Technology China)2019-04-013-2/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add and initialize improc and timing_ctrlr according to D71 capablitites v2: Rebase. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add d71 compiz componentjames qian wang (Arm Technology China)2019-04-012-8/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement d71_compiz_init and add compiz component to komeda-CORE v2: Rebase. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add d71 layerjames qian wang (Arm Technology China)2019-04-013-4/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add detailed layer/layer_state definitions 2. Add d71_layer_init to report layer features and capabilities according to D71 layer block. 3. Add d71_layer_updat/disable v2: Rebase. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> [removed d71_layer_dump() from this commit] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| * | drm/komeda: Add d71_enum_resources and d71_cleanupjames qian wang (Arm Technology China)2019-03-217-17/+858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | D71 consists of a number of Register Blocks, every Block controls a specific HW function, every block has a common block_header to represent its type and pipeline information. GCU (Global Control Unit) is the first Block which describe the global information of D71 HW, Like number of block contained and the number of pipeline supported. So the d71_enum_resources parsed GCU and create pipeline according the GCU configuration, and then iterate and detect the blocks that indicated by the GCU and block_header. And this change also added two struct d71_dev/d71_pipeline to extend komeda_dev/komeda_pipeline to add some d71 only members. v2: - Return the specific errno not -1. - Use DRM_DEBUG as default debug msg printer. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
* | | Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2019-04-03205-3668/+14358
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next amdgpu: - Switch to HMM for userptr (reverted until HMM fixes land) - New experimental SMU 11 replacement for powerplay for vega20 (not enabled by default) - Initial RAS support for vega20 - BACO support for vega12 - BACO fixes for vega20 - Rework IH handling for page fault and retry interrupts - Cleanly split CPU and GPU paths for GPUVM updates - Powerplay fixes - XGMI fixes - Rework how DC interacts with atomic for planes - Clean up and simplify DC/Powerplay interfaces - Misc cleanups and bug fixes amdkfd: - Switch to HMM for userptr (reverted until HMM fixes land) - Add initial RAS support - MQD fixes ttm: - Unify DRM_FILE_PAGE_OFFSET handling - Account for kernel allocations in kernel zone only - Misc cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190402170820.22197-1-alexander.deucher@amd.com
| * | | drm/amdgpu/smu11: fix warning on 32bit archesAlex Deucher2019-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] on 32 bit platforms. Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdgpu: use HMM callback to replace mmu notifier"Alex Deucher2019-03-284-72/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 57731a07795ae80790c6ae7d8e7001cdbd6d14c0. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdkfd: avoid HMM change cause circular lock"Alex Deucher2019-03-281-17/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8dd69e69f42397c9b17764a951c44480b340858e. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdgpu: replace get_user_pages with HMM mirror helpers"Alex Deucher2019-03-289-182/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 915d3eecfa23693bac9e54cdacf84fb4efdcc5c4. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdgpu: fix HMM config dependency issue"Alex Deucher2019-03-283-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6b8f7e3dee7883084932bbdfce471a2960c6db5d. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdkfd: support concurrent userptr update for HMM"Alex Deucher2019-03-281-19/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 386a68e78620c793ed1ba9bc5789b90c18be262a. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdgpu: support userptr cross VMAs case with HMM"Alex Deucher2019-03-281-91/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5aeaccca30023c00d982dfa7bfd25b384523460a. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | Revert "drm/amdgpu: more descriptive message if HMM not enabled"Alex Deucher2019-03-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 194f87ddffe26bbbd124c549a9bf12a96a7f2919. This depends on an HMM fix which is not upstream yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/powerplay: update current profile mode only when it's really appliedEvan Quan2019-03-272-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to update current profile mode if the new profile mode does not take effect in fact. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: fix odm output gamma programmingDmytro Laktyushkin2019-03-272-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only top pipe gets output tf programmed. This change makes all odm head pipes get output tf programmed. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Populate macro_tile_size field for dmlJoshua Aberback2019-03-272-40/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a functions to return swizzle types for dml Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: use dc_is_virtual instead of ENUMEric Bernstein2019-03-274-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: 3.2.24Aric Cyr2019-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Pass SDP spliting in parametersNikola Cornij2019-03-276-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pass SDP splitting when setting stream attributes for future use Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Create clock funcsEryk Brol2019-03-272-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create dccg_init and init_clocks for future use Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Clean up old pplib interface functionsFatemeh Darbehani2019-03-274-52/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] set_display_requirement, dcn1_pplib_apply_display_requirements are no longer used and should be removed. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Pass init_data into DCN resource creationHarry Wentland2019-03-275-27/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] The resource constructor currently needs num_virtual_links from init_data but will need access to other items provided by DM. [HOW] Pass init_data into DCN create_resource_pool functions. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: Handle branch device with DFP count = 0 case.Hugo Hu2019-03-273-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When you have a SST branch device the driver, Even no sink device connected, it also send HPD with a valid EDID. Driver will config it to DP sink. Therefore, there're two displays in display setting. DPCD 0x05, DFP_PRESENT = 1 (branch device), DFP_TYPE = 00 (Display Port) [How] Driver determine DPCD 0x05 DFP_PRESENT = 1(branch) as an active dongle And check DFP count. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Hugo Hu <Hugo.Hu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: program default output gammahersen wu2019-03-271-24/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | program default output gamma if no user specific gamma parameters passed. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amd/display: add preferred pipe split logicJun Lei2019-03-274-12/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] existing logic finds "first free pipe from 5 -> 0" to split this will cause certain sequences to require DC to move an MPCC from one tree to another, which is unsupported this leads to blackscreen to mitigate this problem, we will always try to acquire the "preferred" pipe, and each pipe has a unique preferred pipe this means we avoid most of the scenarios where pipe splitting leads to moving MPCC from one tree to another Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amdgpu: don't put the root PD into the relocated listChristian König2019-03-271-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of skipping the root PD while processing the relocated list just never put it on the list in the first place. This avoids walking the list all together when the root PD is the only entry and so also avoids trying to submit a zero sized IB to the SDMA. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amdgpu: drop the ib from the VM update parametersChristian König2019-03-272-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is redundant with the job pointer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amdgpu: move VM table mapping into the backend as wellChristian König2019-03-274-27/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean that up further and also fix another case where the BO wasn't kmapped for CPU based updates. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amdgpu: XGMI pstate switch initial supportshaoyunl2019-03-276-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver vote low to high pstate switch whenever there is an outstanding XGMI mapping request. Driver vote high to low pstate when all the outstanding XGMI mapping is terminated. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/amdgpu: use the new VM backend for clearsChristian König2019-03-271-57/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And remove the existing code when it is unused. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-14 05:09:35 +0000