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* drm/amd/display: Change DSC policy from slices per column to minimum slice ↵Nikola Cornij2019-08-151-39/+32
| | | | | | | | | | | height [why] Minimum slice height is recommended by VESA DSC Spreadsheet user guide Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add HLG support in color moduleVitaly Prosyak2019-08-151-41/+61
| | | | | | | | | | | | [Why & How] Support hlg OETF and EOTF based on BT.2100-2 Follow up is required. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: clean up DML for DCN2xJun Lei2019-08-152-17/+3
| | | | | | | | | | | | | | | [why] Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since DMLv2 has gone through proper validation. v2 can now be used as the default and 1 level of fallback can be removed [how] remove previous workaround implemenation Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: enabling seamless boot sequence for dcn2Martin Leung2019-08-1517-36/+172
| | | | | | | | | | | | | | | | | [Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes [How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock. This is part 2 of 2 for seamless boot NV10 Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix dcn-specific clk_mgr init_clocksMartin Leung2019-08-152-2/+6
| | | | | | | | | | | | | | | | [Why] underflow seen on certain monitor setups caused by making dcnxx_init_hw generic [How] by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr memset in an else statement so both memsets don't get set Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Make init_hw and init_pipes generic for seamless bootMartin Leung2019-08-159-313/+312
| | | | | | | | | | | | | | | | | [Why] For seamless boot the init_hw sequence must be split into actual hardware vs pipes, in order to defer pipe initialization to set mode and skip of pipe-destructive sequences [How] made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit deleted dcn20 specific versions. This is part 1 of a 2 partimplementation of seamless boot Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: 3.2.43Aric Cyr2019-08-151-1/+1
| | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: wait for pending complete when enabling a planeJun Lei2019-08-151-1/+19
| | | | | | | | | | | | | | | | | [why] When planes are enabled, they must be enabled using VSYNC update (not immediate). However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address only. This operation would normally be okay, but if the locking for immediate flip happens to occur before the VUPDATE associated with the initial plane enablement, it will cause HW to hang. [how] HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: refactor gpio to allocate hw_container in constructorSu Sung Chung2019-08-1518-137/+245
| | | | | | | | | | | | | | | [why] if dynamic allocation fails during gpio_open, it will cause crash due to page fault. [how] handle allocation when gpio object gets created and prevent from calling gpio_open if allocation failed Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add work-around option to skip DCN20 clock updatesJaehyun Chung2019-08-152-0/+4
| | | | | | | | | | | | [Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround, and it's corresponding enable flag. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fixup DPP programming sequenceJun Lei2019-08-159-47/+141
| | | | | | | | | | | | | | | | | | | [why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: make firmware info only load once during dc_bios createDmytro Laktyushkin2019-08-1512-79/+36
| | | | | | | | | | | | | | | Currently every time DC wants to access firmware info we make a call into VBIOS. This makes no sense as there is nothing that can change runtime inside fw info and can cause issues when calling unstable bios during bringup. This change eliminate this behavior by only calling bios once for fw info and keeping it stored as part of dc_bios. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Synchronous DisplayPort Link TrainingDavid Galiffi2019-08-157-125/+282
| | | | | | | | | | | | | | | | | | | | | [WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by: David Galiffi <david.galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Improve sharing of HUBBUB register listsJulian Parkin2019-08-151-3/+6
| | | | | | | | | | | Add DCN20 common register list that contains registers shared between DCN20 generations. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add 22, 24, and 26 degammaVitaly Prosyak2019-08-152-46/+75
| | | | | | | | | | | | | [Why & How] Support degamma ROM and RAM based on hardware capabilities. Some refactoring into color module Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Gary Kattan <Gary.Kattan@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix frames_to_insert mathBayan Zabihiyan2019-08-151-10/+17
| | | | | | | | | | | | | | | | | | [Why] The math on deciding on how many "frames to insert" sometimes sent us over the max refresh rate. Also integer overflow can occur if we have high refresh rates. [How] Instead of clipping the frame duration such that it doesn’t go below the min, just remove a frame from the number of frames to insert. + Use unsigned long long for intermediate calculations to prevent integer overflow. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix issue where 252-255 values are clippedAnthony Koo2019-08-151-1/+2
| | | | | | | | | | | | | | | | [Why] When endpoint is at the boundary of a region, such as at 2^0=1 we find that the last segment has a sharp slope and some points are clipped at the top. [How] If end point is 1, which is exactly at the 2^0 region boundary, we need to program an additional region beyond this point. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: reset hdmi tmds rate and data scramble on pipe resetWenjing Liu2019-08-157-1/+49
| | | | | | | | | | | | | [why] hdmi data scramble and tmds rate is not reset during pipe reset. [how] reset hdmi tmds rate and data scramble on pipe reset Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: reset drr programming on pipe resetWenjing Liu2019-08-152-0/+7
| | | | | | | | | | | | | [why] drr is still enabled after driver is unloaded causing black screen [how] disable drr during pipe reset. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DFS reference clock fieldYongqiang Sun2019-08-151-0/+2
| | | | | | | | | Add to clk_mgr_internal struct, for future use. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add PIXEL_RATE control regs for more instancesYongqiang Sun2019-08-151-5/+20
| | | | | | | | | | For use by future ASICs Signed-off-by: Sung Lee <sung.lee@amd.com> Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/scheduler: use job count instead of peekChristian König2019-08-151-2/+2
| | | | | | | | | | | | The spsc_queue_peek function is accessing queue->head which belongs to the consumer thread and shouldn't be accessed by the producer This is fixing a rare race condition when destroying entities. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Monk.liu@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: MODULE_FIRMWARE requires linux/module.hStephen Rothwell2019-08-151-0/+1
| | | | | | | Fixes: 6a7a0bdbfa0c ("drm/amdgpu: add psp_v12_0 for renoir (v2)") Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: fix spelling mistake "unsuported" -> "unsupported"Colin Ian King2019-08-151-1/+1
| | | | | | | | There is a spelling mistake in a pr_err error message. Fix it. Also add a space after a comma to clean up a checkpatch warning. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: implement querying ras error count for mmhubTao Zhou2019-08-153-0/+298
| | | | | | | | get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use exiting amdgpu_ctx_total_num_entities functionKevin Wang2019-08-151-4/+1
| | | | | | | | simplify driver code. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix typo error amdgput -> amdgpuKevin Wang2019-08-151-6/+6
| | | | | | | | | | fix typo error: change function name from "amdgput_ctx_total_num_entities" to "amdgpu_ctx_total_num_entities". Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: fix message of SetHardMinByFreq failed when feature is ↵Kevin Wang2019-08-151-10/+1
| | | | | | | | | | | | | | | | | disabled the direct send message to smc to set hard clokc will failed when smc clock dpm feature is disabled. so use function of smu_set_hard_freq_range to replace it. the function will check feature enablement. eg: when uclk (mclk) dpm feature is disabled on navi10 [  300.675901] amdgpu: [powerplay] failed send message: SetHardMinByFreq(28)    param: 0x00020064 response 0xfffffffb Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add arcturus_is_dpm_running function for arcturusChengming Gui2019-08-151-0/+21
| | | | | | | | add arcturus_is_dpm_running function Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove redundancy debug log about smu unsupported featuresChengming Gui2019-08-151-1/+0
| | | | | | | | | remove redundancy debug log about smu unsupported features Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: simplify and cleanup setting the dma maskChristoph Hellwig2019-08-156-83/+14
| | | | | | | | | | | | Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: simplify and cleanup setting the dma maskChristoph Hellwig2019-08-151-7/+2
| | | | | | | | | | | | Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: handle PCIe root ports with addressing limitationsChristoph Hellwig2019-08-151-1/+1
| | | | | | | | | | | | amdgpu uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: handle PCIe root ports with addressing limitationsChristoph Hellwig2019-08-153-9/+6
| | | | | | | | | | | | | radeon uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Atish Patra <Atish.Patra@wdc.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: flag renoir as experimental for nowAlex Deucher2019-08-121-1/+1
| | | | | | | | | The current code won't likely work on production hw when it ships so leave it as experimental until it's ready. Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: skip mec2 jump table loading for renoirHuang Rui2019-08-121-0/+4
| | | | | | | | | Renoir need not load mec2 jump table with psp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use direct loading on renoir vcn for the momentHuang Rui2019-08-122-6/+12
| | | | | | | | | | PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: set fw default loading by psp for renoirAaron Liu2019-08-121-5/+1
| | | | | | | | | By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: update lbpw for renoirAaron Liu2019-08-121-0/+1
| | | | | | | | | | enable gfx_v9_0_init_lbpw for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable power gating for renoirAaron Liu2019-08-121-0/+1
| | | | | | | | | | enable gfx power gating for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable clock gating for renoirAaron Liu2019-08-122-0/+2
| | | | | | | | | | enable gfx&common clock gating for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN2.0 to Renoir IP blocksLeo Liu2019-08-121-0/+2
| | | | | | | | | Thus enable VCN2.0 for Renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable Doorbell support for Renoir (v2)Leo Liu2019-08-122-0/+25
| | | | | | | | | | | Add VCN range aperture to NBIO 7.0 v2: rebase (Alex) Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable Renoir VCN firmware loadingLeo Liu2019-08-121-0/+8
| | | | | | | | | By adding new Renoir VCN firmware Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add sdma golden settings for renoirHuang Rui2019-08-121-0/+17
| | | | | | | | This patch adds sdma golden settings for renoir asic. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add gfx golden settings for renoir (v2)Huang Rui2019-08-121-0/+26
| | | | | | | | | | | This patch adds gfx golden settings for renoir real asic. v2: update settings (Alex) Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add psp_v12_0 for renoir (v2)Aaron Liu2019-08-127-2/+619
| | | | | | | | | | | | | | 1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: set rlc funcs for renoirAaron Liu2019-08-121-0/+1
| | | | | | | | | | add gfx_v9_0_rlc_funcs for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add asic funcs for renoirAaron Liu2019-08-121-0/+1
| | | | | | | | | | add asic funcs for renoir, init soc15_asic_funcs Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable dce virtual ip module for RenoirAaron Liu2019-08-122-0/+3
| | | | | | | Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 02:55:04 +0000