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path: root/drivers/hwtracing/intel_th/pci.c
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* intel_th: pci: Add Comet Lake supportAlexander Shishkin2019-05-101-0/+5
| | | | | | | | | | | commit e60e9a4b231a20a199d7a61caadc48693c30d695 upstream. This adds support for Intel TH on Comet Lake. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Ice Lake PCH supportAlexander Shishkin2018-09-181-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Ice Lake PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplateAlexander Shishkin2018-03-281-9/+1
| | | | | | | This adds SPDX GPL-2.0 header to the Trace Hub driver and removes the GPLv2 boilerplate text. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Add Lewisburg PCH supportAlexander Shishkin2017-09-221-0/+5
| | | | | | | | This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Cedar Fork PCH supportAlexander Shishkin2017-09-221-0/+5
| | | | | | | | This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: Perform time resync on capture startAlexander Shishkin2017-08-251-3/+53
| | | | | | | | | | | On some devices (TH 2.x devices at the moment), the internal time counter is initially not synchronized to the global crystal clock, so the time stamps it produces will not be useful. In this case, the driver needs to force the time counter resync. This applies the workaround to relevant devices. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Use drvdata for quirksAlexander Shishkin2017-08-251-1/+2
| | | | | | Allow attaching miscellaneous quirk information to devices as drvdata. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Add Cannon Lake PCH-LP supportAlexander Shishkin2017-08-251-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
* intel_th: pci: Add Cannon Lake PCH-H supportAlexander Shishkin2017-08-251-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
* intel_th: pci: Enable bus masteringAlexander Shishkin2017-08-251-0/+2
| | | | | | | The driver forgets to enable bus mastering for the PCI device. Fix this. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Add Gemini Lake supportAlexander Shishkin2017-03-151-0/+5
| | | | | | This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Add Denverton SOC supportAlexander Shishkin2017-03-151-0/+5
| | | | | | This adds Intel(R) Trace Hub PCI ID for Denverton SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* intel_th: pci: Add Kaby Lake PCH-H supportAlexander Shishkin2016-07-141-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
* intel_th: pci: Add Broxton-M SOC supportAlexander Shishkin2016-04-191-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Laurent Fert <laurent.fert@intel.com>
* intel_th: Set root device's drvdata earlyAlexander Shishkin2016-02-201-2/+0
| | | | | | | | | | | Already during the subdevice initialization time, devices will need to reference Intel TH controller descriptor structure. This patch moves setting the drvdata from the pci glue to intel_th core, before subdevices are populated. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Broxton SOC supportAlexander Shishkin2016-02-071-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Broxton SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Apollo Lake SOC supportAlexander Shishkin2016-02-071-0/+5
| | | | | | | This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: Add pci glue layer for Intel(R) Trace HubAlexander Shishkin2015-10-041-0/+86
This patch adds basic support for PCI-based Intel TH devices. It requests 2 bars (configuration registers for the subdevices and STH channel MMIO region) and calls into Intel TH core code to create the bus with subdevices etc. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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