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* iio: adc: remove unused private data assigned with spi_set_drvdata()Alexandru Ardelean2021-06-131-2/+0
| | | | | | | | | | | | | | | | | These were usually used before the conversion to devm_ functions, so that the remove hook would be able to retrieve the pointer and do cleanups on remove. When the conversion happened, they should have been removed, but were omitted. Some drivers were copied from drivers that fit the criteria described above. In any case, in order to prevent more drivers from being used as example (and have spi_set_drvdata() needlessly set), this change removes it from the IIO ADC group. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Link: https://lore.kernel.org/r/20210513111035.77950-1-aardelean@deviqon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* iio: adc: ad9467: add support for AD9265 high-speed ADCMichael Hennerich2020-09-291-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging. Link: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf The driver supports the same register set as the AD9467, so the support for this chip is added to the 'ad9467' driver. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200924080518.96410-4-alexandru.ardelean@analog.com
* iio: adc: ad9467: add support for AD9434 high-speed ADCMichael Hennerich2020-09-291-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port). The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Link: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf The driver supports the same register set as the AD9467, so the support for this chip is added to the 'ad9467' driver. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200924080518.96410-3-alexandru.ardelean@analog.com
* iio: adc: ad9467: wrap a axi-adc chip-info into a ad9467_chip_info typeAlexandru Ardelean2020-09-291-33/+29
| | | | | | | | | | | | | | | There are 2 chip constants that can be added to the chip-info part. The default output-mode and the VREF mask. When adding new chips to this driver, these can be easily omitted, because these also need to be updated in 2 switch statements. However, if adding them in the chip-info constants, they are updated in a single place and propagated in both switch statements. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200924080518.96410-2-alexandru.ardelean@analog.com
* iio: adc: ad9467: return ENODEV vs EINVAL in ad9467_setup()Alexandru Ardelean2020-09-161-1/+1
| | | | | | | | | The proper error code should be ENODEV (vs EINVAL) in case the chip ID isn't recognized. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20200916082221.72851-1-alexandru.ardelean@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* iio: adc: ad9467: refine mismatch vs unknown chip-id messagesAlexandru Ardelean2020-09-161-1/+2
| | | | | | | | | | We should probably print what the expected chip-ID is. We already have that information available, based on the device specified via device-tree. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20200916083128.73729-1-alexandru.ardelean@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* iio: adc: ad9467: add support AD9467 ADCMichael Hennerich2020-04-191-0/+422
The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performanceover wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Since the chip can operate at such high sample-rates (much higher than classical interfaces), it requires that a DMA controller be used to interface directly to the chip and push data into memory. Typically, the AXI ADC IP core is used to interface with it. Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>