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* iommu/vt-d: Fix rwxp flags in SVM device fault callbackDavid Woodhouse2015-10-281-1/+1
| | | | | | | This is the downside of using bitfields in the struct definition, rather than doing all the explicit masking and shifting. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Handle Caching Mode implementations of SVMDavid Woodhouse2015-10-241-5/+18
| | | | | | | | | Not entirely clear why, but it seems we need to reserve PASID zero and flush it when we make a PASID entry present. Quite we we couldn't use the true PASID value, isn't clear. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Fix SVM IOTLB flush handlingDavid Woodhouse2015-10-201-20/+15
| | | | | | | | | | | | | | | Change the 'pages' parameter to 'unsigned long' to avoid overflow. Fix the device-IOTLB flush parameter calculation — the size of the IOTLB flush is indicated by the position of the least significant zero bit in the address field. For example, a value of 0x12345f000 will flush from 0x123440000 to 0x12347ffff (256KiB). Finally, the cap_pgsel_inv() is not relevant to SVM; the spec says that *all* implementations must support page-selective invaliation for "first-level" translations. So don't check for it. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: fix a loop in prq_event_thread()Dan Carpenter2015-10-181-1/+1
| | | | | | | | | There is an extra semi-colon on this if statement so we always break on the first iteration. Fixes: 0204a4960982 ('iommu/vt-d: Add callback to device driver on page faults') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Fix IOTLB flushing for global pagesDavid Woodhouse2015-10-161-10/+17
| | | | | | When flushing kernel-mode PASIDs, we need to flush global pages too. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Fix address shifting in page request handlerDavid Woodhouse2015-10-161-1/+1
| | | | | | | | This really should be VTD_PAGE_SHIFT, not PAGE_SHIFT. Not that we ever really anticipate seeing this used on IA64, but we should get it right anyway. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: shift wrapping bug in prq_event_thread()Dan Carpenter2015-10-151-1/+1
| | | | | | | | | | The "req->addr" variable is a bit field declared as "u64 addr:52;". The "address" variable is a u64. We need to cast "req->addr" to a u64 before the shift or the result is truncated to 52 bits. Fixes: a222a7f0bb6c ('iommu/vt-d: Implement page request handling') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Fix NULL pointer dereference in page request error caseDavid Woodhouse2015-10-151-4/+8
| | | | | | | | | Dan Carpenter pointed out an error path which could lead to us dereferencing the 'svm' pointer after we know it to be NULL because the PASID lookup failed. Fix that, and make it less likely to happen again. Fixes: a222a7f0bb6c ('iommu/vt-d: Implement page request handling') Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Implement SVM_FLAG_SUPERVISOR_MODE for kernel accessDavid Woodhouse2015-10-151-12/+31
| | | | | | | | | | | | | | | | | | | This is only usable for the static 1:1 mapping of physical memory. Any access to vmalloc or module regions will require some way of doing an IOTLB flush. It's theoretically possible to hook into the tlb_flush_kernel_range() function, but that seems like overkill — most of the addresses accessed through a kernel PASID *will* be in the 1:1 mapping. If we really need to allow access to more interesting kernel regions, then the answer will probably be an explicit IOTLB flush call after use, akin to the DMA API's unmap function. In fact, it might be worth introducing that sooner rather than later, and making it just BUG() if the address isn't in the static 1:1 mapping. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Implement SVM_FLAG_PRIVATE_PASID to allocate unique PASIDsDavid Woodhouse2015-10-151-2/+4
| | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Add callback to device driver on page faultsDavid Woodhouse2015-10-151-1/+25
| | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Implement page request handlingDavid Woodhouse2015-10-151-0/+173
| | | | | | Largely based on the driver-mode implementation by Jesse Barnes. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Implement deferred invalidate for SVMDavid Woodhouse2015-10-151-0/+9
| | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Add basic SVM PASID supportDavid Woodhouse2015-10-151-0/+291
| | | | | | | This provides basic PASID support for endpoint devices, tested with a version of the i915 driver. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* iommu/vt-d: Add initial support for PASID tablesDavid Woodhouse2015-10-151-0/+65
Add CONFIG_INTEL_IOMMU_SVM, and allocate PASID tables on supported hardware. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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