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* x86/amd: iommu_set_device_table() must not be __initJan Beulich2012-03-081-1/+1
| | | | | | | | | This function is called from enable_iommus(), which in turn is used from amd_iommu_resume(). Cc: stable@vger.kernel.org Signed-off-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* ARM: OMAP: make iommu subsys_initcall to fix builtin omap3ispOhad Ben-Cohen2012-02-271-1/+2
| | | | | | | | | | | | | | | | | omap3isp depends on omap's iommu and will fail to probe if initialized before it (which always happen if they are builtin). Make omap's iommu subsys_initcall as an interim solution until the probe deferral mechanism is merged. Reported-by: James <angweiyang@gmail.com> Debugged-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: stable <stable@vger.kernel.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/omap: fix NULL pointer dereferenceOhad Ben-Cohen2012-02-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix this: root@omap4430-panda:~# cat /debug/iommu/ducati/mem [ 62.725708] Unable to handle kernel NULL pointer dereference at virtual addre ss 0000001c [ 62.725708] pgd = e6240000 [ 62.737091] [0000001c] *pgd=a7168831, *pte=00000000, *ppte=00000000 [ 62.743682] Internal error: Oops: 17 [#1] SMP [ 62.743682] Modules linked in: omap_iommu_debug omap_iovmm virtio_rpmsg_bus o map_remoteproc remoteproc virtio_ring virtio mailbox_mach mailbox [ 62.743682] CPU: 0 Not tainted (3.3.0-rc1-00265-g382f84e-dirty #682) [ 62.743682] PC is at debug_read_mem+0x5c/0xac [omap_iommu_debug] [ 62.743682] LR is at 0x1004 [ 62.777832] pc : [<bf033178>] lr : [<00001004>] psr: 60000013 [ 62.777832] sp : e72c7f40 ip : c0763c00 fp : 00000001 [ 62.777832] r10: 00000000 r9 : 00000000 r8 : e72c7f80 [ 62.777832] r7 : e6ffdc08 r6 : bed1ac78 r5 : 00001000 r4 : e7276000 [ 62.777832] r3 : e60f3460 r2 : 00000000 r1 : e60f38c0 r0 : 00000000 [ 62.777832] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 62.816375] Control: 10c53c7d Table: a624004a DAC: 00000015 [ 62.816375] Process cat (pid: 1176, stack limit = 0xe72c62f8) [ 62.828369] Stack: (0xe72c7f40 to 0xe72c8000) ... [ 62.884185] [<bf033178>] (debug_read_mem+0x5c/0xac [omap_iommu_debug]) from [<c010e354>] (vfs_read+0xac/0x130) [ 62.884185] [<c010e354>] (vfs_read+0xac/0x130) from [<c010e4a8>] (sys_read+0x40/0x70) [ 62.884185] [<c010e4a8>] (sys_read+0x40/0x70) from [<c0014a00>] (ret_fast_syscall+0x0/0x3c) Fix also its 'echo bla > /debug/iommu/ducati/mem' Oops sibling, too. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/omap: fix erroneous omap-iommu-debug API callsOhad Ben-Cohen2012-02-241-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adapt omap-iommu-debug to the latest omap-iommu API changes, which were introduced by commit fabdbca "iommu/omap: eliminate the public omap_find_iommu_device() method". In a nutshell, iommu users are not expected to provide the omap_iommu handle anymore - instead, iommus are attached using their user's device handle. omap-iommu-debug is a hybrid beast though: it invokes both public and private omap iommu API, so fix it as necessary (otherwise a crash is imminent). Note: omap-iommu-debug is a bit disturbing, as it fiddles with internal omap iommu data and requires exposing API which is otherwise not needed. It should better be more tightly coupled with omap-iommu, to prevent further bit rot and avoid exposing redundant API. Naturally that's out of scope for the -rc cycle, so for now just fix the obvious. Reported-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/msm: Fix error handling in msm_iommu_unmap()Joerg Roedel2012-01-301-6/+1
| | | | | | | | | | | | | | Error handling in msm_iommu_unmap() is broken. On some error conditions retval is set to a non-zero value which causes the function to return 'len' at the end. This hides the error from the user. Zero should be returned in those error cases. Cc: David Brown <davidb@codeaurora.org> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Cc: stable@vger.kernel.org # >= 3.1 Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Acked-by: David Brown <davidb@codeaurora.org>
* iommu/amd: Work around broken IVRS tablesJoerg Roedel2012-01-231-0/+3
| | | | | | | | | | | | On some systems the IVRS table does not contain all PCI devices present in the system. In case a device not present in the IVRS table is translated by the IOMMU no DMA is possible from that device by default. This patch fixes this by removing the DTE entry for every PCI device present in the system and not covered by IVRS. Cc: stable@vger.kernel.org # >= 3.0 Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuLinus Torvalds2012-01-1012-151/+2424
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (53 commits) iommu/amd: Set IOTLB invalidation timeout iommu/amd: Init stats for iommu=pt iommu/amd: Remove unnecessary cache flushes in amd_iommu_resume iommu/amd: Add invalidate-context call-back iommu/amd: Add amd_iommu_device_info() function iommu/amd: Adapt IOMMU driver to PCI register name changes iommu/amd: Add invalid_ppr callback iommu/amd: Implement notifiers for IOMMUv2 iommu/amd: Implement IO page-fault handler iommu/amd: Add routines to bind/unbind a pasid iommu/amd: Implement device aquisition code for IOMMUv2 iommu/amd: Add driver stub for AMD IOMMUv2 support iommu/amd: Add stat counter for IOMMUv2 events iommu/amd: Add device errata handling iommu/amd: Add function to get IOMMUv2 domain for pdev iommu/amd: Implement function to send PPR completions iommu/amd: Implement functions to manage GCR3 table iommu/amd: Implement IOMMUv2 TLB flushing routines iommu/amd: Add support for IOMMUv2 domain mode iommu/amd: Add amd_iommu_domain_direct_map function ...
| * Merge branches 'iommu/page-sizes' and 'iommu/group-id' into nextJoerg Roedel2012-01-093-0/+130
| |\ | | | | | | | | | | | | | | | | | | Conflicts: drivers/iommu/amd_iommu.c drivers/iommu/intel-iommu.c include/linux/iommu.h
| | * iommu: Add option to group multi-function devicesAlex Williamson2011-11-152-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The option iommu=group_mf indicates the that the iommu driver should expose all functions of a multi-function PCI device as the same iommu_device_group. This is useful for disallowing individual functions being exposed as independent devices to userspace as there are often hidden dependencies. Virtual functions are not affected by this option. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * iommu/amd: Implement iommu_device_groupAlex Williamson2011-11-151-0/+13
| | | | | | | | | | | | | | | | | | | | | Just use the amd_iommu_alias_table directly. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * iommu/intel: Implement iommu_device_groupAlex Williamson2011-11-151-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We generally have BDF granularity for devices, so we just need to make sure devices aren't hidden behind PCIe-to-PCI bridges. We can then make up a group number that's simply the concatenated seg|bus|dev|fn so we don't have to track them (not that users should depend on that). Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Acked-By: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * iommu: Add iommu_device_group callback and iommu_group sysfs entryAlex Williamson2011-11-151-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An IOMMU group is a set of devices for which the IOMMU cannot distinguish transactions. For PCI devices, a group often occurs when a PCI bridge is involved. Transactions from any device behind the bridge appear to be sourced from the bridge itself. We leave it to the IOMMU driver to define the grouping restraints for their platform. Using this new interface, the group for a device can be retrieved using the iommu_device_group() callback. Users will compare the value returned against the value returned for other devices to determine whether they are part of the same group. Devices with no group are not translated by the IOMMU. There should be no expectations about the group numbers as they may be arbitrarily assigned by the IOMMU driver and may not be persistent across boots. We also provide a sysfs interface to the group numbers here so that userspace can understand IOMMU dependencies between devices for managing safe, userspace drivers. [Some code changes by Joerg Roedel <joerg.roedel@amd.com>] Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | |
| | \
| *-. \ Merge branches 'iommu/fixes', 'arm/omap' and 'x86/amd' into nextJoerg Roedel2012-01-0912-152/+2295
| |\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/pci/hotplug/acpiphp_glue.c
| | | * | iommu/amd: Set IOTLB invalidation timeoutJoerg Roedel2011-12-222-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To protect the command buffer from hanging when a device does not respond to an IOTLB invalidation, set a timeout of 1s for outstanding IOTLB invalidations. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Init stats for iommu=ptJoerg Roedel2011-12-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IOMMUv2 driver added a few statistic counter which are interesting in the iommu=pt mode too. So initialize the statistic counter for that mode too. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Remove unnecessary cache flushes in amd_iommu_resumeJoerg Roedel2011-12-221-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The caches are already flushed in enable_iommus(), so this flush is not necessary. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add invalidate-context call-backJoerg Roedel2011-12-151-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This call-back is invoked when the task that is bound to a pasid is about to exit. The driver can use it to shutdown all context related to that context in a safe way. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add amd_iommu_device_info() functionJoerg Roedel2011-12-151-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be used to find out which features necessary for IOMMUv2 usage are available on a given device. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Adapt IOMMU driver to PCI register name changesJoerg Roedel2011-12-151-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbolic register names for PCI and PASID changed in PCI code. This patch adapts the AMD IOMMU driver to these changes. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | Merge branch 'iommu/page-sizes' into x86/amdJoerg Roedel2011-12-146-60/+181
| | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/iommu/amd_iommu.c
| | | | * | iommu/core: remove the temporary pgsize settingsOhad Ben-Cohen2011-11-101-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all IOMMU drivers are exporting their supported pgsizes, we can remove the default pgsize settings in register_iommu(). Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/intel: announce supported page sizesOhad Ben-Cohen2011-11-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the IOMMU core know we support arbitrary page sizes (as long as they're an order of 4KiB). This way the IOMMU core will retain the existing behavior we're used to; it will let us map regions that: - their size is an order of 4KiB - they are naturally aligned Note: Intel IOMMU hardware doesn't support arbitrary page sizes, but the driver does (it splits arbitrary-sized mappings into the pages supported by the hardware). To make everything simpler for now, though, this patch effectively tells the IOMMU core to keep giving this driver the same memory regions it did before, so nothing is changed as far as it's concerned. At this point, the page sizes announced remain static within the IOMMU core. To correctly utilize the pgsize-splitting of the IOMMU core by this driver, it seems that some core changes should still be done, because Intel's IOMMU page size capabilities seem to have the potential to be different between different DMA remapping devices. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/amd: announce supported page sizesOhad Ben-Cohen2011-11-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the IOMMU core know we support arbitrary page sizes (as long as they're an order of 4KiB). This way the IOMMU core will retain the existing behavior we're used to; it will let us map regions that: - their size is an order of 4KiB - they are naturally aligned Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/msm: announce supported page sizesOhad Ben-Cohen2011-11-101-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the IOMMU core know we support 4KiB, 64KiB, 1MiB and 16MiB page sizes. This way the IOMMU core can split any arbitrary-sized physically contiguous regions (that it needs to map) as needed. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: David Brown <davidb@codeaurora.org> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/omap: announce supported page sizesOhad Ben-Cohen2011-11-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the IOMMU core know we support 4KiB, 64KiB, 1MiB and 16MiB page sizes. This way the IOMMU core can split any arbitrary-sized physically contiguous regions (that it needs to map) as needed. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/core: split mapping to page sizes as supported by the hardwareOhad Ben-Cohen2011-11-102-25/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When mapping a memory region, split it to page sizes as supported by the iommu hardware. Always prefer bigger pages, when possible, in order to reduce the TLB pressure. The logic to do that is now added to the IOMMU core, so neither the iommu drivers themselves nor users of the IOMMU API have to duplicate it. This allows a more lenient granularity of mappings; traditionally the IOMMU API took 'order' (of a page) as a mapping size, and directly let the low level iommu drivers handle the mapping, but now that the IOMMU core can split arbitrary memory regions into pages, we can remove this limitation, so users don't have to split those regions by themselves. Currently the supported page sizes are advertised once and they then remain static. That works well for OMAP and MSM but it would probably not fly well with intel's hardware, where the page size capabilities seem to have the potential to be different between several DMA remapping devices. register_iommu() currently sets a default pgsize behavior, so we can convert the IOMMU drivers in subsequent patches. After all the drivers are converted, the temporary default settings will be removed. Mainline users of the IOMMU API (kvm and omap-iovmm) are adopted to deal with bytes instead of page order. Many thanks to Joerg Roedel <Joerg.Roedel@amd.com> for significant review! Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: David Brown <davidb@codeaurora.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Cc: KyongHo Cho <pullip.cho@samsung.com> Cc: Hiroshi DOYU <hdoyu@nvidia.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: kvm@vger.kernel.org Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | | * | iommu/core: stop converting bytes to page order back and forthOhad Ben-Cohen2011-11-105-39/+26
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Express sizes in bytes rather than in page order, to eliminate the size->order->size conversions we have whenever the IOMMU API is calling the low level drivers' map/unmap methods. Adopt all existing drivers. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: David Brown <davidb@codeaurora.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Joerg Roedel <Joerg.Roedel@amd.com> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Cc: KyongHo Cho <pullip.cho@samsung.com> Cc: Hiroshi DOYU <hdoyu@nvidia.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add invalid_ppr callbackJoerg Roedel2011-12-141-2/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This callback can be used to change the PRI response code sent to a device when a PPR fault fails. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement notifiers for IOMMUv2Joerg Roedel2011-12-142-11/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pages are not pinned anymore we need notifications when the VMM changes the page-tables. Use mmu_notifiers for that. Also use the task_exit notifier from the profiling subsystem to shutdown all contexts related to this task. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement IO page-fault handlerJoerg Roedel2011-12-121-8/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register the notifier for PPR faults and handle them as necessary. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add routines to bind/unbind a pasidJoerg Roedel2011-12-121-0/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds routines to bind a specific process address-space to a given PASID. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement device aquisition code for IOMMUv2Joerg Roedel2011-12-121-0/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the amd_iommu_init_device() and amd_iommu_free_device() functions which make a device and the IOMMU ready for IOMMUv2 usage. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add driver stub for AMD IOMMUv2 supportJoerg Roedel2011-12-123-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option for the optional driver. Since it is optional it can be compiled as a module and will only be loaded when required by another driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add stat counter for IOMMUv2 eventsJoerg Roedel2011-12-121-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some interesting statistic counters for events when IOMMUv2 is active. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add device errata handlingJoerg Roedel2011-12-122-3/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add infrastructure for errata-handling and handle two known erratas in the IOMMUv2 code. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add function to get IOMMUv2 domain for pdevJoerg Roedel2011-12-123-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMD IOMMUv2 driver needs to get the IOMMUv2 domain associated with a particular device. This patch adds a function to get this information. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement function to send PPR completionsJoerg Roedel2011-12-123-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To send completions for PPR requests this patch adds a function which can be used by the IOMMUv2 driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement functions to manage GCR3 tableJoerg Roedel2011-12-123-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functions necessary to set and clear the GCR3 values associated with a particular PASID in an IOMMUv2 domain. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement IOMMUv2 TLB flushing routinesJoerg Roedel2011-12-123-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions added with this patch allow to manage the IOMMU and the device TLBs for all devices in an IOMMUv2 domain. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add support for IOMMUv2 domain modeJoerg Roedel2011-12-125-5/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for protection domains that implement two-level paging for devices. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add amd_iommu_domain_direct_map functionJoerg Roedel2011-12-122-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be used to switch a domain into paging-mode 0. In this mode all devices can access physical system memory directly without any remapping. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Implement notifier for PPR faultsJoerg Roedel2011-12-123-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a notifer at which a module can attach to get informed about incoming PPR faults. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Put IOMMUv2 capable devices in pt_domainJoerg Roedel2011-12-123-16/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the device starts to use IOMMUv2 features the dma handles need to stay valid. The only sane way to do this is to use a identity mapping for the device and not translate it by the iommu. This is implemented with this patch. Since this lifts the device-isolation there is also a new kernel parameter which allows to disable that feature. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Add iommuv2 flag to struct amd_iommuJoerg Roedel2011-12-123-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In mixed IOMMU setups this flag inidicates whether an IOMMU supports the v2 features or not. This patch also adds a global flag together with a function to query that flag from other code. The flag shows if at least one IOMMUv2 is in the system. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Enable GT mode when supported by IOMMUJoerg Roedel2011-12-122-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature needs to be enabled before IOMMUv2 DTEs can be set up. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Setup PPR log when supported by IOMMUJoerg Roedel2011-12-122-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate and enable a log buffer for peripheral page faults when the IOMMU supports this feature. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Get the maximum number of PASIDs supportedJoerg Roedel2011-12-122-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the number of PASIDs supported by each IOMMU in the system and take the smallest number as the maximum value supported by the IOMMU driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | | * | iommu/amd: Convert dev_table_entry to u64Joerg Roedel2011-12-123-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the contents of 'struct dev_table_entry' to u64 to allow updating the DTE wit 64bit writes as required by the spec. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * | | iommu/omap: be verbose when omap_iommu_iova_to_phys failsOhad Ben-Cohen2011-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An omap_iommu_iova_to_phys failure usually means that iova wasn't mapped. When that happens, it's helpful to know the value of iova, so add it to the error message. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * | | iommu/omap: eliminate the public omap_find_iommu_device() methodOhad Ben-Cohen2011-12-052-43/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eliminate the public omap_find_iommu_device() method, and don't expect clients to provide the omap_iommu handle anymore. Instead, OMAP's iommu driver now utilizes dev_archdata's private iommu extension to be able to access the required iommu information. This way OMAP IOMMU users are now able to use the generic IOMMU API without having to call any omap-specific binding method. Update omap3isp appropriately. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 23:20:03 +0000