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* irqchip/aspeed-scu-ic: Correctly initialise status and enable registersRyan Chen2023-02-051-1/+4
| | | | | | | | | | The status and enable registers are never initialised with sensible default values. Fix those. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> [maz: commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230130085430.635583-1-ryan_chen@aspeedtech.com
* irqchip/aspeed-scu-ic: Fix irq_of_parse_and_map() return valueKrzysztof Kozlowski2022-05-041-2/+2
| | | | | | | | | The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO. Fixes: 04f605906ff0 ("irqchip: Add Aspeed SCU interrupt controller") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220423094227.33148-2-krzysztof.kozlowski@linaro.org
* irqchip/aspeed-scu: Replace update_bits with write_bits.Billy Tsai2021-11-251-2/+2
| | | | | | | | | | | | The interrupt status bits are cleared by writing 1, we should force a write to clear the interrupt without checking if the value has changed. Fixes: 04f605906ff0 ("irqchip: Add Aspeed SCU interrupt controller") Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211124094348.11621-1-billy_tsai@aspeedtech.com Cc: stable@vger.kernel.org
* irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier2021-06-101-4/+2
| | | | | | | | | | | Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
* irqchip: Add Aspeed SCU interrupt controllerEddie James2020-01-201-0/+239
The Aspeed SOCs provide some interrupts through the System Control Unit registers. Add an interrupt controller that provides these interrupts to the system. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/1579123790-6894-3-git-send-email-eajames@linux.ibm.com