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* irqchip/brcmstb-l2: Use _irqsave locking variants in non-interrupt codeDoug Berger2019-03-231-4/+6
| | | | | | | | | | | | | | | | | | commit 33517881ede742107f416533b8c3e4abc56763da upstream. Using the irq_gc_lock/irq_gc_unlock functions in the suspend and resume functions creates the opportunity for a deadlock during suspend, resume, and shutdown. Using the irq_gc_lock_irqsave/ irq_gc_unlock_irqrestore variants prevents this possible deadlock. Cc: stable@vger.kernel.org Fixes: 7f646e92766e2 ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller") Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> [maz: tidied up $SUBJECT] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* irqchip/bcm: Remove hashed address printingJaedon Shin2018-02-161-3/+0
| | | | | | | | | | Since commit ad67b74d2469 ("printk: hash addresses printed with %p") pointers are being hashed when printed. Displaying the virtual memory at bootup time is not helpful. so delete the prints. Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/brcmstb-l2: Add support for the BCM7271 L2 controllerDoug Berger2017-10-191-22/+64
| | | | | | | | | | | | Add the initialization of the generic irq chip for the BCM7271 L2 interrupt controller. This controller only supports level interrupts and uses the "brcm,bcm7271-l2-intc" compatibility string. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/brcmstb-l2: Abstract register accessesDoug Berger2017-10-191-9/+20
| | | | | | | | | | | | | | Added register block offsets to the brcmstb_l2_intc_data structure for the status and mask registers to support reading the active interupts in an abstracted way. It seems like an irq_chip method should have been provided for this, but it's not there yet. Abstracted the implementation of the handler, suspend, and resume functions to not use any hard coded register offsets. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/brcmstb-l2: Remove some processing from the handlerDoug Berger2017-10-191-24/+48
| | | | | | | | | | | | | | | | | | | | | Saving the generic chip pointer in the brcmstb_l2_intc_data prevents the need to call irq_get_domain_generic_chip(). Also don't need to save parent_irq and base there since local variables in the brcmstb_l2_intc_of_init() function are just as good. The handle_edge_irq flow or chained_irq_enter takes care of the acknowledgment of the interrupt so it is redundant to clear it in brcmstb_l2_intc_irq_handle(). irq_linear_revmap() is a fast path equivalent of irq_find_mapping() that is appropriate to use for domain controllers of this type. Defining irq_mask_ack is slightly more efficient than just implementing irq_mask and irq_ack separately. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip: brcmstb-l2: Define an irq_pm_shutdown functionFlorian Fainelli2017-08-071-0/+1
| | | | | | | | | | | | | The Broadcom STB platforms support S5 and we allow specific hardware wake-up events to take us out of this state. Because we were not defining an irq_pm_shutdown() function pointer, we would not be correctly masking non-wakeup events, which would result in spurious wake-ups from sources that were not explicitly configured for wake-up. Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller") Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* treewide: remove redundant #include <linux/kconfig.h>Masahiro Yamada2016-10-111-1/+0
| | | | | | | | | | | | | | | | | | | Kernel source files need not include <linux/kconfig.h> explicitly because the top Makefile forces to include it with: -include $(srctree)/include/linux/kconfig.h This commit removes explicit includes except the following: * arch/s390/include/asm/facilities_src.h * tools/testing/radix-tree/linux/kernel.h These two are used for host programs. Link: http://lkml.kernel.org/r/1473656164-11929-1-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* irqchip/brcmstb-l2: Make of probe function staticBen Dooks2016-06-131-2/+2
| | | | | | | | | | | The probe functions in this driver is not exported or declared so make it static to fix the following warning: drivers/irqchip/irq-brcmstb-l2.c:115:12: warning: symbol 'brcmstb_l2_intc_of_init' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Link: https://lkml.kernel.org/r/1465408940-16414-1-git-send-email-ben.dooks@codethink.co.uk Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* genirq: Remove irq argument from irq flow handlersThomas Gleixner2015-09-161-4/+3
| | | | | | | | | | | | | | Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
* irqchip/brcmstb-l2: Prepare brcmstb_l2_intc_irq_handle for irq argument removalThomas Gleixner2015-07-161-1/+3
| | | | | | | | | | | | The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
* irqchip/brcmstb-l2: Consolidate chained IRQ handler install/removeThomas Gleixner2015-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org
* irqchip: Prepare for local stub header removalJoel Porquet2015-07-111-2/+0
| | | | | | | | | | | | | | | | | The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so the local irqchip.h became an empty shell, which solely includes include/linux/irqchip.h Include the global header in all irqchip drivers instead of the local header, so we can remove it. Signed-off-by: Joel Porquet <joel@porquet.org> Cc: vgupta@synopsys.com Cc: monstr@monstr.eu Cc: ralf@linux-mips.org Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init timeBrian Norris2015-04-011-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Wakeable interrupts might be pending at boot/init time, because wakeup interrupts might have triggered a resume from S5. So don't clear such wakeups. This means that any driver which requests a wakeable interrupt bit should be prepared to handle an interrupt as soon as they call request_irq(). (This is technically already the correct development practice, but some drivers probably expect not to receive interrupts until they have performed some I/O.) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8840/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2014-12-101-15/+26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq core updates from Thomas Gleixner: "This is the first (boring) part of irq updates: - support for big endian I/O accessors in the generic irq chip - cleanup of brcmstb/bcm7120 drivers so they can be reused for non ARM SoCs - the usual pile of fixes and updates for the various ARM irq chips" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip: dw-apb-ictl: Add PM support irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed ARM: orion: convert the irq_reg_{readl,writel} calls to the new API irqchip: atmel-aic: Add missing entry for rm9200 irq fixups irqchip: atmel-aic: Rename at91sam9_aic_irq_fixup for naming consistency irqchip: atmel-aic: Add specific irq fixup function for sam9g45 and sam9rl irqchip: atmel-aic: Add irq fixups for at91sam926x SoCs irqchip: atmel-aic: Add irq fixup for RTT block irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Decouple driver from brcmstb-l2 irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask irqchip: bcm7120-l2: Make sure all register accesses use base+offset irqchip: bcm7120-l2, brcmstb-l2: Remove ARM Kconfig dependency irqchip: bcm7120-l2: Eliminate bad IRQ check irqchip: brcmstb-l2: Eliminate dependency on ARM code genirq: Generic chip: Add big endian I/O accessors ...
| * irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel}Kevin Cernekee2014-11-091-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This effectively converts the __raw_ accessors to the non-__raw_ equivalents. To handle BE, we pass IRQ_GC_BE_IO, similar to what was done in irq-bcm7120-l2.c. Since irq_reg_writel now takes an irq_chip_generic argument, writel must be used for the initial hardware reset in the probe function. But that operation never needs endian swapping, so it's probably not a big deal. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-15-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: brcmstb-l2: Eliminate dependency on ARM codeKevin Cernekee2014-11-091-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | The irq-brcmstb-l2 driver has a single dependency on the ARM code, the do_bad_IRQ macro. Expand this macro in-place so that the driver can be built on non-ARM platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-6-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | irqchip: brcmstb-l2: Fix error handling of irq_of_parse_and_mapDmitry Torokhov2014-11-261-2/+2
|/ | | | | | | | | | | Return value of irq_of_parse_and_map() is unsigned int, with 0 indicating failure, so testing for negative result never works. Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Kevin Cernekee <cernekee@gmail.com> Link: https://lkml.kernel.org/r/20141114221642.GA37468@dtor-ws Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: brcmstb-l2: Level-2 interrupts are edge sensitiveFlorian Fainelli2014-06-211-1/+1
| | | | | | | | | | | The driver was configuring the interrupt handler for the Level-2 interrupts to be "level" triggered while they are in fact "edge" triggered. Fix this by using the correct handler. Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1402337102-19428-1-git-send-email-f.fainelli@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controllerFlorian Fainelli2014-05-271-0/+202
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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