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* irqchip/gic, gic-v3: Prevent GSI to SGI translationsAndre Przywara2022-04-052-0/+12
| | | | | | | | | | | | | | | | | At the moment the GIC IRQ domain translation routine happily converts ACPI table GSI numbers below 16 to GIC SGIs (Software Generated Interrupts aka IPIs). On the Devicetree side we explicitly forbid this translation, actually the function will never return HWIRQs below 16 when using a DT based domain translation. We expect SGIs to be handled in the first part of the function, and any further occurrence should be treated as a firmware bug, so add a check and print to report this explicitly and avoid lengthy debug sessions. Fixes: 64b499d8df40 ("irqchip/gic-v3: Configure SGIs as standard interrupts") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220404110842.2882446-1-andre.przywara@arm.com
* irqchip/gic-v3: Fix GICR_CTLR.RWP pollingMarc Zyngier2022-04-051-4/+4
| | | | | | | | | | | | | | | | | | It turns out that our polling of RWP is totally wrong when checking for it in the redistributors, as we test the *distributor* bit index, whereas it is a different bit number in the RDs... Oopsie boo. This is embarassing. Not only because it is wrong, but also because it took *8 years* to notice the blunder... Just fix the damn thing. Fixes: 021f653791ad ("irqchip: gic-v3: Initial support for GICv3") Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Link: https://lore.kernel.org/r/20220315165034.794482-2-maz@kernel.org
* irqchip/gic-v4: Wait for GICR_VPENDBASER.Dirty to clear before deschedulingMarc Zyngier2022-04-051-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The way KVM drives GICv4.{0,1} is as follows: - vcpu_load() makes the VPE resident, instructing the RD to start scanning for interrupts - just before entering the guest, we check that the RD has finished scanning and that we can start running the vcpu - on preemption, we deschedule the VPE by making it invalid on the RD However, we are preemptible between the first two steps. If it so happens *and* that the RD was still scanning, we nonetheless write to the GICR_VPENDBASER register while Dirty is set, and bad things happen (we're in UNPRED land). This affects both the 4.0 and 4.1 implementations. Make sure Dirty is cleared before performing the deschedule, meaning that its_clear_vpend_valid() becomes a sort of full VPE residency barrier. Reported-by: Jingyi Wang <wangjingyi11@huawei.com> Tested-by: Nianyao Tang <tangnianyao@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Fixes: 57e3cebd022f ("KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty bit") Link: https://lore.kernel.org/r/4aae10ba-b39a-5f84-754b-69c2eb0a2c03@huawei.com
* irqchip/irq-qcom-mpm: fix return value check in qcom_mpm_init()Yang Yingliang2022-04-051-1/+1
| | | | | | | | | | | | If devm_platform_ioremap_resource() fails, it never returns NULL, replace NULL check with IS_ERR(). Fixes: a6199bb514d8 ("irqchip: Add Qualcomm MPM controller driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220316025100.1758413-1-yangyingliang@huawei.com
* irq/qcom-mpm: Fix build error without MAILBOXYueHaibing2022-04-051-0/+1
| | | | | | | | | | | | | | | | If MAILBOX is n, building fails: drivers/irqchip/irq-qcom-mpm.o: In function `mpm_pd_power_off': irq-qcom-mpm.c:(.text+0x174): undefined reference to `mbox_send_message' irq-qcom-mpm.c:(.text+0x174): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `mbox_send_message' Make QCOM_MPM depends on MAILBOX to fix this. Fixes: a6199bb514d8 ("irqchip: Add Qualcomm MPM controller driver") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220317131956.30004-1-yuehaibing@huawei.com
* Merge tag 'asm-generic-5.18' of ↵Linus Torvalds2022-03-232-157/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "There are three sets of updates for 5.18 in the asm-generic tree: - The set_fs()/get_fs() infrastructure gets removed for good. This was already gone from all major architectures, but now we can finally remove it everywhere, which loses some particularly tricky and error-prone code. There is a small merge conflict against a parisc cleanup, the solution is to use their new version. - The nds32 architecture ends its tenure in the Linux kernel. The hardware is still used and the code is in reasonable shape, but the mainline port is not actively maintained any more, as all remaining users are thought to run vendor kernels that would never be updated to a future release. - A series from Masahiro Yamada cleans up some of the uapi header files to pass the compile-time checks" * tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (27 commits) nds32: Remove the architecture uaccess: remove CONFIG_SET_FS ia64: remove CONFIG_SET_FS support sh: remove CONFIG_SET_FS support sparc64: remove CONFIG_SET_FS support lib/test_lockup: fix kernel pointer check for separate address spaces uaccess: generalize access_ok() uaccess: fix type mismatch warnings from access_ok() arm64: simplify access_ok() m68k: fix access_ok for coldfire MIPS: use simpler access_ok() MIPS: Handle address errors for accesses above CPU max virtual user address uaccess: add generic __{get,put}_kernel_nofault nios2: drop access_ok() check from __put_user() x86: use more conventional access_ok() definition x86: remove __range_not_ok() sparc64: add __{get,put}_kernel_nofault() nds32: fix access_ok() checks in get/put_user uaccess: fix nios2 and microblaze get_user_8() sparc64: fix building assembly files ...
| * nds32: Remove the architectureAlan Kao2022-03-072-157/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nds32 architecture, also known as AndeStar V3, is a custom 32-bit RISC target designed by Andes Technologies. Support was added to the kernel in 2016 as the replacement RISC-V based V5 processors were already announced, and maintained by (current or former) Andes employees. As explained by Alan Kao, new customers are now all using RISC-V, and all known nds32 users are already on longterm stable kernels provided by Andes, with no development work going into mainline support any more. While the port is still in a reasonably good shape, it only gets worse over time without active maintainers, so it seems best to remove it before it becomes unusable. As always, if it turns out that there are mainline users after all, and they volunteer to maintain the port in the future, the removal can be reverted. Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/ Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/ Link: https://www.andestech.com/en/products-solutions/andestar-architecture/ Signed-off-by: Alan Kao <alankao@andestech.com> [arnd: rewrite changelog to provide more background] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds2022-03-231-17/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "Updates for IRQ stacks and virtually mapped stack support, and ftrace: - Support for IRQ and vmap'ed stacks This covers all the work related to implementing IRQ stacks and vmap'ed stacks for all 32-bit ARM systems that are currently supported by the Linux kernel, including RiscPC and Footbridge. It has been submitted for review in four different waves: - IRQ stacks support for v7 SMP systems [0] - vmap'ed stacks support for v7 SMP systems[1] - extending support for both IRQ stacks and vmap'ed stacks for all remaining configurations, including v6/v7 SMP multiplatform kernels and uniprocessor configurations including v7-M [2] - fixes and updates in [3] - ftrace fixes and cleanups Make all flavors of ftrace available on all builds, regardless of ISA choice, unwinder choice or compiler [4]: - use ADD not POP where possible - fix a couple of Thumb2 related issues - enable HAVE_FUNCTION_GRAPH_FP_TEST for robustness - enable the graph tracer with the EABI unwinder - avoid clobbering frame pointer registers to make Clang happy - Fixes for the above" [0] https://lore.kernel.org/linux-arm-kernel/20211115084732.3704393-1-ardb@kernel.org/ [1] https://lore.kernel.org/linux-arm-kernel/20211122092816.2865873-1-ardb@kernel.org/ [2] https://lore.kernel.org/linux-arm-kernel/20211206164659.1495084-1-ardb@kernel.org/ [3] https://lore.kernel.org/linux-arm-kernel/20220124174744.1054712-1-ardb@kernel.org/ [4] https://lore.kernel.org/linux-arm-kernel/20220203082204.1176734-1-ardb@kernel.org/ * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (62 commits) ARM: fix building NOMMU ARMv4/v5 kernels ARM: unwind: only permit stack switch when unwinding call_with_stack() ARM: Revert "unwind: dump exception stack from calling frame" ARM: entry: fix unwinder problems caused by IRQ stacks ARM: unwind: set frame.pc correctly for current-thread unwinding ARM: 9184/1: return_address: disable again for CONFIG_ARM_UNWIND=y ARM: 9183/1: unwind: avoid spurious warnings on bogus code addresses Revert "ARM: 9144/1: forbid ftrace with clang and thumb2_kernel" ARM: mach-bcm: disable ftrace in SMC invocation routines ARM: cacheflush: avoid clobbering the frame pointer ARM: kprobes: treat R7 as the frame pointer register in Thumb2 builds ARM: ftrace: enable the graph tracer with the EABI unwinder ARM: unwind: track location of LR value in stack frame ARM: ftrace: enable HAVE_FUNCTION_GRAPH_FP_TEST ARM: ftrace: avoid unnecessary literal loads ARM: ftrace: avoid redundant loads or clobbering IP ARM: ftrace: use trampolines to keep .init.text in branching range ARM: ftrace: use ADD not POP to counter PUSH at entry ARM: ftrace: ensure that ADR takes the Thumb bit into account ARM: make get_current() and __my_cpu_offset() __always_inline ...
| * | ARM: fix building NOMMU ARMv4/v5 kernelsArnd Bergmann2022-03-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The removal of the old-style irq entry broke obscure NOMMU configurations on machines that have an MMU: ld.lld: error: undefined symbol: generic_handle_arch_irq referenced by kernel/entry-armv.o:(__irq_svc) in archive arch/arm/built-in.a A follow-up patch to convert nvic to the generic_handle_arch_irq() could have fixed this by removing the Kconfig conditional, but did it differently. Change the Kconfig logic so ARM machines now unconditionally enable the feature. I have also submitted a patch to remove support for the configurations that broke, but fixing the regression first is a trivial and correct change. Reported-by: kernel test robot <lkp@intel.com> Fixes: 54f481a2308e ("ARM: remove old-style irq entry") Fixes: 52d240871760 ("irqchip: nvic: Use GENERIC_IRQ_MULTI_HANDLER") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
| * | irqchip: nvic: Use GENERIC_IRQ_MULTI_HANDLERVladimir Murzin2021-12-062-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather then restructuring the ARMv7M entrly logic per TODO, just move NVIC to GENERIC_IRQ_MULTI_HANDLER. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
* | | Merge tag 'irqchip-5.18' of ↵Thomas Gleixner2022-03-1420-366/+1272
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: - Add support for the STM32MP13 variant - Move parent device away from struct irq_chip - Remove all instances of non-const strings assigned to struct irq_chip::name, enabling a nice cleanup for VIC and GIC) - Simplify the Qualcomm PDC driver - A bunch of SiFive PLIC cleanups - Add support for a new variant of the Meson GPIO block - Add support for the irqchip side of the Apple M1 PMU - Add support for the Apple M1 Pro/Max AICv2 irqchip - Add support for the Qualcomm MPM wakeup gadget - Move the Xilinx driver over to the generic irqdomain handling - Tiny speedup for IPIs on GICv3 systems - The usual odd cleanups Link: https://lore.kernel.org/all/20220313105142.704579-1-maz@kernel.org
| * \ \ Merge branch irq/qcom-mpm into irq/irqchip-nextMarc Zyngier2022-03-113-0/+470
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/qcom-mpm: : . : Add support for Qualcomm's MPM wakeup controller, courtesy : of Shawn Guo. : . irqchip: Add Qualcomm MPM controller driver dt-bindings: interrupt-controller: Add Qualcomm MPM support Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip: Add Qualcomm MPM controller driverShawn Guo2022-03-113-0/+470
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcomm SoCs based on the RPM architecture have a MSM Power Manager (MPM) in always-on domain. In addition to managing resources during sleep, the hardware also has an interrupt controller that monitors the interrupts when the system is asleep, wakes up the APSS when one of these interrupts occur and replays it to GIC after it becomes operational. It adds an irqchip driver for this interrupt controller, and here are some notes about it. - For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt is defined by SoC, as well as the mapping between MPM_GPIO pin and GPIO number. The former mapping is retrieved from device tree, while the latter is defined in TLMM pinctrl driver. - The power domain (PD) .power_off hook is used to notify RPM that APSS is about to power collapse. This requires MPM PD be the parent PD of CPU cluster. - When SoC gets awake from sleep mode, the driver will receive an interrupt from RPM, so that it can replay interrupt for particular polarity. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220308080534.3384532-3-shawn.guo@linaro.org
| * | | Merge branch irq/aic-v2 into irq/irqchip-nextMarc Zyngier2022-03-111-88/+375
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/aic-v2: : . : Add support for the interrupt controller found is the latest : incarnation of Apple M1 systems, courtesy of Hector Martin. : . irqchip/apple-aic: Add support for AICv2 irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Add Fast IPI support dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/apple-aic: Add support for AICv2Hector Martin2022-03-111-33/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for the new AICv2 hardware block in t6000/t6001 SoCs. It seems these blocks are missing the information required to compute the event register offset in the capability registers, so we specify that in the DT as a second reg entry. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-8-marcan@marcan.st
| | * | | irqchip/apple-aic: Support multiple diesHector Martin2022-03-111-23/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multi-die support in AICv2 uses several sets of IRQ registers. Introduce a die count and compute the register group offset based on the die ID field of the hwirq number, as reported by the hardware. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-7-marcan@marcan.st
| | * | | irqchip/apple-aic: Dynamically compute register offsetsHector Martin2022-03-111-17/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to support AIC variants with different numbers of IRQs based on capability registers. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-6-marcan@marcan.st
| | * | | irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqsHector Martin2022-03-111-32/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to directly use the hardware event number as the hwirq number. Since IRQ events have bit 16 set (type=1), FIQs now move to starting at hwirq number 0. This will become more important once multi-die support is introduced in a later commit. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-5-marcan@marcan.st
| | * | | irqchip/apple-aic: Add Fast IPI supportHector Martin2022-03-111-13/+109
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newer AICv2 present in t600x SoCs does not have legacy IPI support at all. Since t8103 also supports Fast IPIs, implement support for this first. The legacy IPI code is left as a fallback, so it can be potentially used by older SoCs in the future. The vIPI code is shared; only the IPI firing/acking bits change for Fast IPIs. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-4-marcan@marcan.st
| * | | Merge branch irq/aic-pmu into irq/irqchip-nextMarc Zyngier2022-03-101-22/+72
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/aic-pmu: : . : Prefix branch for the M1 PMU support, adding the required : irqchip changes. Shared with the arm64 tree. : . irqchip/apple-aic: Fix cpumask allocation for FIQs irqchip/apple-aic: Move PMU-specific registers to their own include file arm64: dts: apple: Add t8303 PMU nodes arm64: dts: apple: Add t8103 PMU interrupt affinities irqchip/apple-aic: Wire PMU interrupts irqchip/apple-aic: Parse FIQ affinities from device-tree dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts dt-bindings: arm-pmu: Document Apple PMU compatible strings Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/apple-aic: Fix cpumask allocation for FIQsMarc Zyngier2022-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An emparassing typo: allocating a pointer instead of the object pointed to. No harm done, as the pointer is large enough for what we are using the object for, but still... Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220310050238.4478-1-guozhengkui@vivo.com
| | * | | irqchip/apple-aic: Move PMU-specific registers to their own include fileMarc Zyngier2022-02-071-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file. Reviewed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/apple-aic: Wire PMU interruptsMarc Zyngier2022-02-071-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/apple-aic: Parse FIQ affinities from device-treeMarc Zyngier2022-02-071-0/+49
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, parse the affinities kindly provided in the device-tree. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | Merge branch irq/meson-gpio into irq/irqchip-nextMarc Zyngier2022-03-091-16/+90
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/meson-gpio: : . : Expand meson-gpio support to deal with the new Meson-S4 SoC : . irqchip/meson-gpio: Add support for meson s4 SoCs irqchip/meson-gpio: add select trigger type callback irqchip/meson-gpio: support more than 8 channels gpio irq dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/meson-gpio: Add support for meson s4 SoCsQianggui Song2022-03-091-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The meson s4 SoCs support 12 gpio irq lines compared with previous serial chips and have something different, details are as below. IRQ Number: - 80:68 13 pins on bank Z - 67:48 20 pins on bank X - 47:36 12 pins on bank H - 35:24 12 pins on bank D - 23:22 2 pins on bank E - 21:14 8 pins on bank C - 13:0 13 pins on bank B Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> [maz: fixed some W=1 build warnings] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-5-qianggui.song@amlogic.com
| | * | | irqchip/meson-gpio: add select trigger type callbackQianggui Song2022-03-041-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to some chips may use different registers and offset, provide a set trigger type call back and add one for old controller. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-4-qianggui.song@amlogic.com
| | * | | irqchip/meson-gpio: support more than 8 channels gpio irqQianggui Song2022-03-041-9/+12
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current meson gpio irqchip driver only support 8 channels for gpio irq line, later chips may have more then 8 channels, so need to modify code to support more. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-3-qianggui.song@amlogic.com
| * | | Merge branch irq/misc-5.18 into irq/irqchip-nextMarc Zyngier2022-03-043-15/+19
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/misc-5.18: : . : Misc irq chip changes for 5.18 : : - GICv3: Relax ordering of previous stores to only include the ISH domain : : - nvic: Unmap MMIo region on probe failure : : - xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER when used on microblaze : . irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER irqchip/nvic: Release nvic_base upon failure irqchip/gic-v3: Use dsb(ishst) to order writes with ICC_SGI1R_EL1 accesses Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLERMichal Simek2022-03-041-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register the Xilinx driver as the root interrupt controller using the GENERIC_IRQ_MULTI_HANDLER API, instead of the arch-specific hack. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Asserhall <stefan.asserhall@xilinx.com> [maz: repainted commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/e6c6595a81f662bf839cee3109d0fa58a596ea47.1646380284.git.michal.simek@xilinx.com
| | * | | irqchip/nvic: Release nvic_base upon failureSouptick Joarder (HPE)2022-03-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smatch warning was reported as below -> smatch warnings: drivers/irqchip/irq-nvic.c:131 nvic_of_init() warn: 'nvic_base' not released on lines: 97. Release nvic_base upon failure. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220218163303.33344-1-jrdr.linux@gmail.com
| | * | | irqchip/gic-v3: Use dsb(ishst) to order writes with ICC_SGI1R_EL1 accessesBarry Song2022-02-211-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A dsb(ishst) barrier should be enough to order previous writes with the system register generating the SGI, as we only need to guarantee the visibility of data to other CPUs in the inner shareable domain before we send the SGI. A micro-benchmark is written to verify the performance impact on kunpeng920 machine with 2 sockets, each socket has 2 dies, and each die has 24 CPUs, so totally the system has 2 * 2 * 24 = 96 CPUs. ~2% performance improvement can be seen by this benchmark. The code of benchmark module: #include <linux/module.h> #include <linux/timekeeping.h> volatile int data0 ____cacheline_aligned; volatile int data1 ____cacheline_aligned; volatile int data2 ____cacheline_aligned; volatile int data3 ____cacheline_aligned; volatile int data4 ____cacheline_aligned; volatile int data5 ____cacheline_aligned; volatile int data6 ____cacheline_aligned; static void ipi_latency_func(void *val) { } static int __init ipi_latency_init(void) { ktime_t stime, etime, delta; int cpu, i; int start = smp_processor_id(); stime = ktime_get(); for ( i = 0; i < 1000; i++) for (cpu = 0; cpu < 96; cpu++) { data0 = data1 = data2 = data3 = data4 = data5 = data6 = cpu; smp_call_function_single(cpu, ipi_latency_func, NULL, 1); } etime = ktime_get(); delta = ktime_sub(etime, stime); printk("%s ipi from cpu%d to cpu0-95 delta of 1000times:%lld\n", __func__, start, delta); return 0; } module_init(ipi_latency_init); static void ipi_latency_exit(void) { } module_exit(ipi_latency_exit); MODULE_DESCRIPTION("IPI benchmark"); MODULE_LICENSE("GPL"); run the below commands 10 times on both Vanilla and the kernel with this patch: # taskset -c 0 insmod test.ko # rmmod test The result on vanilla: ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126757449 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126784249 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126177703 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127022281 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126184883 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127374585 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:125778089 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126974441 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127357625 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126228184 The result on the kernel with this patch: ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:124467401 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123474209 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123558497 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:122993951 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:122984223 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123323609 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:124507583 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123386963 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123340664 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123285324 Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> [maz: tidied up commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220220061910.6155-1-21cnbao@gmail.com
| * | | Merge branch irq/plic-cleanups into irq/irqchip-nextMarc Zyngier2022-03-041-12/+26
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/plic-cleanups: : . : SiFive PLIC cleanups from Niklas Cassel: : : - Clarify some of the namings in the driver : : - Make sure S-mode interrupts are disabled when running in M-mode : . irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode irqchip/sifive-plic: Improve naming scheme for per context offsets Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel2022-03-021-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When detecting a context for a privilege mode different from the current running privilege mode, we simply skip to the next context register. This means that we never clear the S-mode enable bits when running in M-mode. On canaan k210, a bunch of S-mode interrupts are enabled by the bootrom. These S-mode specific interrupts should never trigger, since we never set the mie.SEIE bit in the parent interrupt controller (riscv-intc). However, we will be able to see the mip.SEIE bit set as pending. This isn't a good default when CONFIG_RISCV_M_MODE is set, since in that case we will never enter a lower privilege mode (e.g. S-mode). Let's clear the S-mode enable bits when running the kernel in M-mode, such that we won't have a interrupt pending bit set, which we will never clear. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220302131544.3166154-3-Niklas.Cassel@wdc.com
| | * | | irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel2022-03-021-7/+7
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLIC supports a fixed number of contexts (15872). Each context has fixed register offsets in PLIC. The number of contexts that we need to initialize depends on the privilege modes supported by each hart. Therefore, this mapping between PLIC context registers to hart privilege modes is platform specific, and is currently supplied via device tree. For example, canaan,k210 has the following mapping: Context0: hart0 M-mode Context1: hart0 S-mode Context2: hart1 M-mode Context3: hart1 S-mode While sifive,fu540 has the following mapping: Context0: hart0 M-mode Context1: hart1 M-mode Context2: hart1 S-mode Because the number of contexts per hart is not fixed, the names ENABLE_PER_HART and CONTEXT_PER_HART for the register offsets are quite confusing and might mislead the reader to think that these are fixed register offsets per hart. Rename the offsets to more clearly highlight that these are per PLIC context and not per hart. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220302131544.3166154-2-Niklas.Cassel@wdc.com
| * | | Merge branch irq/qcom-pdc-cleanup into irq/irqchip-nextMarc Zyngier2022-03-011-109/+28
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/qcom-pdc-cleanup: : . : Spring cleanup for the Qualcomm PDC driver, simplifying its : use of irq domains, replacing open-coded functionnalities with : the core code equivalent, and fixing the dodgy locking. : . irqchip/qcom-pdc: Drop open coded version of __assign_bit() irqchip/qcom-pdc: Fix broken locking irqchip/qcom-pdc: Kill qcom_pdc_translate helper irqchip/qcom-pdc: Kill non-wakeup irqdomain irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQ Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/qcom-pdc: Drop open coded version of __assign_bit()Marc Zyngier2022-03-011-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver uses what looks like an open-coded version of __assign_bit(). Replace it with the real thing. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-6-maz@kernel.org
| | * | | irqchip/qcom-pdc: Fix broken lockingMarc Zyngier2022-03-011-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pdc_enable_intr() serves as a primitive to qcom_pdc_gic_{en,dis}able, and has a raw spinlock for mutual exclusion, which is uses with interruptible primitives. This means that this critical section can itself be interrupted. Should the interrupt also be a PDC interrupt, and the endpoint driver perform an irq_disable() on that interrupt, we end-up in a deadlock. Fix this by using the irqsave/irqrestore variants of the locking primitives. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-5-maz@kernel.org
| | * | | irqchip/qcom-pdc: Kill qcom_pdc_translate helperMarc Zyngier2022-03-011-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qcom_pdc_translate() really is nothing but an open coded version of irq_domain_translate_twocell(). Get rid of it and use the common version instead. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-4-maz@kernel.org
| | * | | irqchip/qcom-pdc: Kill non-wakeup irqdomainMarc Zyngier2022-03-011-74/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A careful look at the way the PDC driver works shows that: - all interrupts are in the same space - all interrupts are treated the same And yet the driver creates two domains based on whether the interrupt gets mapped directly or from the pinctrl code, which is obviously a waste of resources. Kill the non-wakeup domain and unify all the interrupt handling. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224101226.88373-3-maz@kernel.org
| | * | | irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQMarc Zyngier2022-03-011-17/+17
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PDC_NO_PARENT_IRQ is pretty pointless, as all it indicates is that the PDC terminates the interrupt hierarchy. Which is exactly the same as not having a mapping in the GIC space. This is also bad practice to treat the absence of a hwirq as a hwirq itself. Just explicitly use the region mapping pointer, and drop the definition. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-2-maz@kernel.org
| * | | Merge branch irq/print_chip into irq/irqchip-nextMarc Zyngier2022-02-156-99/+137
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/print_chip: : . : Convert irqchip drivers that use the .name field as a topology : description to the .irq_print_chip callback, which allows the : name to be made dymanic. The irq_chip structures are then made : 'const' in order to prevent further abuse. : . irqchip/versatile-fpga: Switch to dynamic chip name output irqchip/ts4800: Switch to dynamic chip name output irqchip/mvebu-pic: Switch to dynamic chip name output irqchip/lpc32xx: Switch to dynamic chip name output irqchip/gic: Switch to dynamic chip name output genirq/debugfs: Use irq_print_chip() when provided by irqchip genirq: Allow irq_chip registration functions to take a const irq_chip irqdomain: Let irq_domain_set_{info,hwirq_and_chip} take a const irq_chip Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/versatile-fpga: Switch to dynamic chip name outputMarc Zyngier2022-02-152-21/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the name output to the relevant callback, which allows us some nice cleanups (mostly owing to the fact that the driver is now DT only. We also drop a random include directive from the ftintc010 driver. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-8-maz@kernel.org
| | * | | irqchip/ts4800: Switch to dynamic chip name outputMarc Zyngier2022-02-151-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-7-maz@kernel.org
| | * | | irqchip/mvebu-pic: Switch to dynamic chip name outputMarc Zyngier2022-02-151-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of overriding the name field, track the corresponding device and use the relevant callback to output its name. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-6-maz@kernel.org
| | * | | irqchip/lpc32xx: Switch to dynamic chip name outputMarc Zyngier2022-02-151-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of overriding the name field with the device name, use the relevant callback. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-5-maz@kernel.org
| | * | | irqchip/gic: Switch to dynamic chip name outputMarc Zyngier2022-02-151-48/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last dynamic aspect of the GIC's irq_chip structure is the name that is associated to it. Move the output of that name to the relevant callback, which allows us to do a bit of cleanup and mark the structures const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-4-maz@kernel.org
| * | | | Merge branch irq/parent_device into irq/irqchip-nextMarc Zyngier2022-02-104-13/+13
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * irq/parent_device: : . : Move irq_chip::parent_device to irq_domain::dev to track the : PM state of the device implementing the irqchip. : . genirq: Kill irq_chip::parent_device pinctrl: starfive: Move PM device over to irq domain pinctrl: npcm: Fix broken references to chip->parent_device gpio: tpmx86: Move PM device over to irq domain gpio: rcar: Move PM device over to irq domain gpio: omap: Move PM device over to irq domain gpio: mt7621: Kill parent_device usage irqchip/imx-intmux: Move PM device over to irq domain irqchip/renesas-irqc: Move PM device over to irq domain irqchip/renesas-intc-irqpin: Move PM device over to irq domain irqchip/gic: Move PM device over to irq domain genirq: Allow the PM device to originate from irq domain Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | irqchip/imx-intmux: Move PM device over to irq domainMarc Zyngier2022-02-091-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the reference to the device over to the irq domain. This allows the irq_chip structure to be directly used instead of taking a copy for each instance. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-6-maz@kernel.org
| | * | | irqchip/renesas-irqc: Move PM device over to irq domainMarc Zyngier2022-02-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the reference to the device over to the irq domain. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-5-maz@kernel.org
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