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* mailbox: arm_mhuv2: Add driverViresh Kumar2020-12-093-0/+1145
| | | | | | | | | | | | | | | | | | | This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Tested-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: cast void pointers to unsigned longMartin Kaiser2020-12-011-6/+6
| | | | | | | | | | | | | | | | | | | | Now that the driver can be enabled by COMPILE_TEST, we see warnings on 64bit platforms when void pointers are cast to unsigned int (and vice versa). warning: cast to smaller integer type 'unsigned int' from 'void *' unsigned int chan = (unsigned int)link->con_priv; ... warning: cast to 'void *' from smaller integer type 'unsigned int' ipcc->controller.chans[i].con_priv = (void *)i; Update these casts to use unsigned long variables, which are the same size as pointers on all platforms. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: remove duplicate error messageMartin Kaiser2020-12-011-3/+0
| | | | | | | | | platform_get_irq_byname already prints an error message if the requested irq was not found. Don't print another message in the driver. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: add COMPILE_TEST dependencyMartin Kaiser2020-12-011-1/+1
| | | | | | | | | This allows compiling the driver on architectures where the hardware is not available. Most other mailbox drivers support this as well. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: arm_mhu_db: Fix mhu_db_shutdown by replacing kfree with devm_kfreeSudeep Holla2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mhu_db_channel info is allocated per channel using devm_kzalloc from mhu_db_mbox_xlate which gets called from mbox_request_channel. However we are releasing the allocated mhu_db_channel info using plain kfree from mhu_db_shutdown which is called from mbox_free_channel. This leads to random crashes when the channel is freed like below one: Unable to handle kernel paging request at virtual address 0080000400000008 [0080000400000008] address between user and kernel address ranges Internal error: Oops: 96000044 [#1] PREEMPT SMP Modules linked in: scmi_module(-) CPU: 1 PID: 2212 Comm: rmmod Not tainted 5.10.0-rc5 #31 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Nov 19 2020 pstate: 20000085 (nzCv daIf -PAN -UAO -TCO BTYPE=--) pc : release_nodes+0x74/0x230 lr : devres_release_all+0x40/0x68 Call trace: release_nodes+0x74/0x230 devres_release_all+0x40/0x68 device_release_driver_internal+0x12c/0x1f8 driver_detach+0x58/0xe8 bus_remove_driver+0x64/0xe0 driver_unregister+0x38/0x68 platform_driver_unregister+0x1c/0x28 scmi_driver_exit+0x38/0x44 [scmi_module] __arm64_sys_delete_module+0x188/0x260 el0_svc_common.constprop.0+0x80/0x1a8 do_el0_svc+0x2c/0x98 el0_sync_handler+0x160/0x168 el0_sync+0x174/0x180 Code: 1400000d eb07009f 54000460 f9400486 (f90004a6) ---[ end trace c55ffd306c140233 ]--- Fix it by replacing kfree with devm_kfree as required. Fixes: 7002ca237b21 ("mailbox: arm_mhu: Add ARM MHU doorbell driver") Reported-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Cristian Marussi <cristian.marussi@arm.com> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2020-10-241-1/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
| * firmware: tegra: Enable BPMP support on Tegra234Thierry Reding2020-09-181-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the BPMP on Tegra234 to avoid relying on Tegra194 being enabled to pull in the needed OF device ID table entry. On simulation platforms the BPMP hasn't booted up yet by the time we probe the BPMP driver and the BPMP hasn't had a chance to mark the doorbell as ringable by the CCPLEX. This corresponding check in the BPMP driver will therefore fail. Work around this by disabling the check on simulation platforms. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | mailbox: avoid timer start from callbackJassi Brar2020-10-161-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the txdone is done by polling, it is possible for msg_submit() to start the timer while txdone_hrtimer() callback is running. If the timer needs recheduling, it could already be enqueued by the time hrtimer_forward_now() is called, leading hrtimer to loudly complain. WARNING: CPU: 3 PID: 74 at kernel/time/hrtimer.c:932 hrtimer_forward+0xc4/0x110 CPU: 3 PID: 74 Comm: kworker/u8:1 Not tainted 5.9.0-rc2-00236-gd3520067d01c-dirty #5 Hardware name: Libre Computer AML-S805X-AC (DT) Workqueue: events_freezable_power_ thermal_zone_device_check pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : hrtimer_forward+0xc4/0x110 lr : txdone_hrtimer+0xf8/0x118 [...] This can be fixed by not starting the timer from the callback path. Which requires the timer reloading as long as any message is queued on the channel, and not just when current tx is not done yet. Fixes: 0cc67945ea59 ("mailbox: switch to hrtimer for tx_complete polling") Reported-by: Da Xue <da@libre.computer> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | maiblox: mediatek: Fix handling of platform_get_irq() errorKrzysztof Kozlowski2020-10-121-5/+3
| | | | | | | | | | | | | | | | | | platform_get_irq() returns -ERRNO on error. In such case casting to u32 and comparing to 0 would pass the check. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: arm_mhu: Add ARM MHU doorbell driverSudeep Holla2020-10-122-1/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt. This patch adds a separate the MHU controller driver for doorbel mode of operation using the extended DT binding to add support the same. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: arm_mhu: Match only if compatible is "arm,mhu"Sudeep Holla2020-10-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | Since we will be soon adding a separate driver based on this ARM MHU driver to support doorbell mode, let us add explicit check to match the default compatible for this driver. This is needed as the probe and match reuses the AMBA device ids currently and don't have any explicit compatible check. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: bcm: convert tasklets to use new tasklet_setup() APIAllen Pais2020-10-121-3/+3
|/ | | | | | | | | | | In preparation for unconditionally passing the struct tasklet_struct pointer to all tasklet callbacks, switch to using the new tasklet_setup() and from_tasklet() to pass the tasklet pointer explicitly. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Allen Pais <allen.lkml@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* iomap: constify ioreadX() iomem argument (as in generic implementation)Krzysztof Kozlowski2020-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch series "iomap: Constify ioreadX() iomem argument", v3. The ioread8/16/32() and others have inconsistent interface among the architectures: some taking address as const, some not. It seems there is nothing really stopping all of them to take pointer to const. This patch (of 4): The ioreadX() and ioreadX_rep() helpers have inconsistent interface. On some architectures void *__iomem address argument is a pointer to const, on some not. Implementations of ioreadX() do not modify the memory under the address so they can be converted to a "const" version for const-safety and consistency among architectures. [krzk@kernel.org: sh: clk: fix assignment from incompatible pointer type for ioreadX()] Link: http://lkml.kernel.org/r/20200723082017.24053-1-krzk@kernel.org [akpm@linux-foundation.org: fix drivers/mailbox/bcm-pdc-mailbox.c] Link: http://lkml.kernel.org/r/202007132209.Rxmv4QyS%25lkp@intel.com Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com> Cc: Helge Deller <deller@gmx.de> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Jon Mason <jdmason@kudzu.us> Cc: Allen Hubbe <allenbh@gmail.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Jason Wang <jasowang@redhat.com> Link: http://lkml.kernel.org/r/20200709072837.5869-1-krzk@kernel.org Link: http://lkml.kernel.org/r/20200709072837.5869-2-krzk@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mailbox: mediatek: cmdq: clear task in channel before shutdownDennis YC Hsieh2020-08-031-0/+38
| | | | | | | | | | Do success callback in channel when shutdown. For those task not finish, callback with error code thus client has chance to cleanup or reset. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: support mt6779 gce platform definitionDennis YC Hsieh2020-08-031-0/+2
| | | | | | | | | | Add gce v4 hardware support with different thread number and shift. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: variablize address shift in platformDennis YC Hsieh2020-08-031-13/+44
| | | | | | | | | | Some gce hardware shift pc and end address in register to support large dram addressing. Implement gce address shift when write or read pc and end register. And add shift bit in platform definition. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add msm8994 apcs compatibleKonrad Dybcio2020-08-031-0/+5
| | | | | | | | | | | MSM8994 has an APCS block similar to 8916, but with a different clock driver due to the former one having 2 clusters. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add sdm660 hmss compatibleKonrad Dybcio2020-08-031-0/+5
| | | | | | | | | | The Qualcomm SDM660 platform has a APCS HMSS GLOBAL block, add the compatible for this. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Mark PM functions as __maybe_unusedNathan Chancellor2020-08-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PM and CONFIG_PM_SLEEP are unset, the following warnings occur: drivers/mailbox/imx-mailbox.c:638:12: warning: 'imx_mu_runtime_resume' defined but not used [-Wunused-function] 638 | static int imx_mu_runtime_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:629:12: warning: 'imx_mu_runtime_suspend' defined but not used [-Wunused-function] 629 | static int imx_mu_runtime_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:611:12: warning: 'imx_mu_resume_noirq' defined but not used [-Wunused-function] 611 | static int imx_mu_resume_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:601:12: warning: 'imx_mu_suspend_noirq' defined but not used [-Wunused-function] 601 | static int imx_mu_suspend_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ Mark these functions as __maybe_unused, which is the standard procedure for PM functions. Fixes: bb2b2624dbe2 ("mailbox: imx: Add runtime PM callback to handle MU clocks") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Put the PCCT table for error pathHanjun Guo2020-08-031-2/+7
| | | | | | | | | | | | | The acpi_get_table() should be coupled with acpi_put_table() if the mapped table is not used at runtime to release the table mapping. In acpi_pcc_probe(), the PCCT table entries will be used as private data for communication chan at runtime, but the table should be put for error path. Signed-off-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-08-032-2/+2
| | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add ipq6018 apcs compatibleSivaprakash Murugesan2020-06-101-0/+5
| | | | | | | | | | | | The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the ipq6018 apcs provides a clock functionality similar to msm8916 but the clock driver is different. Create a child device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add clock driver name in apcs mailbox driver dataSivaprakash Murugesan2020-06-101-18/+38
| | | | | | | | | | | | | | | Some apcs mailbox devices supports a clock driver, the compatible strings of devices supporting clock driver along with the clock driver name are maintained in a separate structure within the mailbox driver. And the clock driver is added based on device match. With increase in number of devices supporting the clock feature move the clock driver name inside the driver data. so that we can use a single API to get the register offset of mailbox driver and clock driver name together, and the clock driver will be added based on the driver data. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flagAnson Huang2020-06-071-2/+7
| | | | | | | | | | | | | | | | | | IPC MU has no power domain assigned and there could be IPC during noirq suspend phase, so IRQF_NO_SUSPEND flag is needed for IPC MU. However, for other MUs, they have power domain assigned and their power will be turned off during noirq suspend phase, but with IRQF_NO_SUSPEND set, their interrupts are NOT disabled even after their power turned off, it will cause system crash when mailbox driver trys to handle pending interrupts but the MU power is already turned off. So, IRQF_NO_SUSPEND flag should ONLY be added to IPC MU which has power domain managed by SCU, then all other MUs' pending interrupts after noirq suspend phase will be handled after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add runtime PM callback to handle MU clocksAnson Huang2020-06-071-3/+29
| | | | | | | | | | | | | | | | | | | | | | Some of i.MX8M SoCs have MU clock, they need to be managed in runtime to make sure the MU clock can be off in runtime, add runtime PM callback to handle MU clock. And on i.MX8MP, the MU clock is combined with power domain and runtime PM is enabled for the clock driver, during noirq suspend/resume phase, runtime PM is disabled by device suspend, but the MU context save/restore needs to enable MU clock for register access, calling clock prepare/enable will trigger runtime resume failure and lead to system suspend failed. Actually, the MU context save/restore is ONLY necessary for SCU IPC MU, other MUs especially on i.MX8MP platforms which have MU clock assigned, they need to runtime request/free mailbox channel in the consumer driver, so no need to save/restore MU context for them, hence it can avoid this issue, so the MU context save/restore is ONLY applied to i.MX platforms MU instance without clock present. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add context save/restore for suspend/resumeDong Aisheng2020-06-071-0/+35
| | | | | | | | | | | | | | | | | For "mem" mode suspend on i.MX8 SoCs, MU settings could be lost because its power is off, so save/restore is needed for MU settings during suspend/resume. However, the restore can ONLY be done when MU settings are actually lost, for the scenario of settings NOT lost in "freeze" mode suspend, since there could be still IPC going on multiple CPUs, restoring the MU settings could overwrite the TIE by mistake and cause system freeze, so need to make sure ONLY restore the MU settings when it is powered off, Anson fixes this by checking whether restore is actually needed when resume. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Add support for Qualcomm IPCCManivannan Sadhasivam2020-05-303-0/+298
| | | | | | | | | | | | | | | | | | | | | | Add support for the Inter-Processor Communication Controller (IPCC) block from Qualcomm that coordinates the interrupts (inbound & outbound) for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1 (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS). This driver is modeled as an irqchip+mailbox driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [mani: moved to mailbox, added static mbox channels and cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: zynqmp-ipi: Fix NULL vs IS_ERR() check in zynqmp_ipi_mbox_probe()Wei Yongjun2020-05-301-12/+8
| | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). So we should check whether the return value of devm_ioremap() is NULL instead of IS_ERR. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx-mailbox: fix scu msg header size checkPeng Fan2020-05-301-5/+9
| | | | | | | | | | | | The i.MX8 SCU message header size is the number of "u32" elements, not "u8", so fix the check. Reported-by: coverity-bot <keescook+coverity-bot@chromium.org> Addresses-Coverity-ID: 1461658 ("Memory - corruptions") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sprd: Add Spreadtrum mailbox driverBaolin Wang2020-05-303-0/+371
| | | | | | | | | The Spreadtrum mailbox controller supports 8 channels to communicate with MCUs, and it contains 2 different parts: inbox and outbox, which are used to send and receive messages by IRQ mode. Signed-off-by: Baolin Wang <baolin.wang@unisoc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: ZynqMP IPI: Delete an error message in zynqmp_ipi_probe()Markus Elfring2020-05-301-3/+2
| | | | | | | | | | | The function platform_get_irq can log an error already. Thus omit a redundant message for the exception handling in the calling function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Disable the clock on devm_mbox_controller_register() failureFabio Estevam2020-05-301-1/+3
| | | | | | | | | | | | devm_mbox_controller_register() may fail, and in the case of failure the priv->clk clock that was previously enabled, should be disabled. Fixes: 2bb7005696e2 ("mailbox: Add support for i.MX messaging unit") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> [Jassi: fixed merge/am conflict] Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Fix return in imx_mu_scu_xlate()Dan Carpenter2020-05-301-1/+1
| | | | | | | | | This called from mbox_request_channel(). The caller is expecting error pointers and not NULL so this "return NULL;" will lead to an Oops. Fixes: 0a67003b1985 ("mailbox: imx: add SCU MU support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Support runtime PMAnson Huang2020-05-301-1/+26
| | | | | | | | | | | | | | | | | | | | | Some power hungry sub-systems like VPU has its own MUs which also use mailbox driver, current mailbox driver uses platform driver model and MU's power will be ON after driver probed and left ON there, it may cause the whole sub-system can NOT enter lower power mode, take VPU driver for example, it has runtime PM support, but due to its MU always ON, the VPU sub-system will be always ON and consume many power during kernel idle. To save power in kernel idle, mailbox driver needs to support runtime PM in order to power off MU when it is unused. However, the runtime suspend/resume can ONLY be implemented in mailbox's .shutdown/.startup callback, so its consumer needs to call mbox_request_channel()/mbox_free_channel() in consumer driver's runtime PM callback, then the MU's power will be ON/OFF along with consumer's runtime PM status. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: make pcc_mbox_driver staticJason Yan2020-05-301-1/+1
| | | | | | | | | | | Fix the following sparse warning: drivers/mailbox/pcc.c:571:24: warning: symbol 'pcc_mbox_driver' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: add SCU MU supportPeng Fan2020-03-191-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A cores from hardware design, and could not be reused for other purpose. Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples", Passing short messages: Transmit register(s) can be used to pass short messages from one to four words in length. For example, when a four-word message is desired, only one of the registers needs to have its corresponding interrupt enable bit set at the receiver side; the message’s first three words are written to the registers whose interrupt is masked, and the fourth word is written to the other register (which triggers an interrupt at the receiver side). i.MX8/8X SCU firmware IPC is an implementation of passing short messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX and four RX to support IPC to SCU firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SCU MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg larger than 4 u32 words. - Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: restructure code to make easy for new MUPeng Fan2020-03-191-54/+83
| | | | | | | | | | | | | | | | Add imx_mu_generic_tx for data send and imx_mu_generic_rx for interrupt data receive. Pack original mu chans related code into imx_mu_init_generic Add tx/rx/init hooks into imx_mu_dcfg With these, it will be a bit easy to introduce i.MX8/8X SCU type MU dedicated to communicate with SCU. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mediatek: remove implementation related to atomic_execBibby Hsieh2020-03-191-68/+8
| | | | | | | | | | | After implement flush, client can flush the executing command buffer or abort the still waiting for event command buffer, so controller do not need to implement atomic_exe feature. remove it. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mediatek: implement flush functionBibby Hsieh2020-03-191-0/+52
| | | | | | | | | | | For client driver which need to reorganize the command buffer, it could use this function to flush the send command buffer. If the channel doesn't be started (usually in waiting for event), this function will abort it directly. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* maillbox: bcm-flexrm-mailbox: handle cmpl_pool dma allocation failureRayagonda Kokatanur2020-03-191-0/+2
| | | | | | | | | Handle 'cmpl_pool' dma memory allocation failure. Fixes: a9a9da47f8e6 ("mailbox: no need to check return value of debugfs_create functions") Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Tyler Hicks <tyhicks@linux.microsoft.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sun6i-msgbox: Add a new mailbox driverSamuel Holland2020-03-193-0/+337
| | | | | | | | | | | | | Allwinner sun6i, sun8i, sun9i, and sun50i SoCs contain a hardware message box used for communication between the ARM CPUs and the ARISC management coprocessor. This mailbox contains 8 unidirectional 4-message FIFOs. Add a driver for it, so it can be used with the Linux mailbox framework. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: bcm-pdc: Use scnprintf() for avoiding potential buffer overflowTakashi Iwai2020-03-191-10/+10
| | | | | | | | | Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox:armada-37xx-rwtm:remove duplicate print in armada_37xx_mbox_probe()Tang Bin2020-03-191-6/+2
| | | | | | | | | In this function,we don't need dev_err() message because when something goes wrong,platform_get_irq() and devm_platform_ioremap_resource() have print an error message itself, so we should remove duplicate dev_err(). Signed-off-by: Tang Bin <tangbin@cmss.chinamobile.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resourceYangtao Li2020-01-081-4/+1
| | | | | | | Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* Merge tag 'mailbox-v5.5' of ↵Linus Torvalds2019-12-014-51/+62
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - omap : misc - catch error returned from pm_runtime_put_sync - hisi : misc - drop .owner from platform_driver - stm : change how wakeup is handled - imx : fix - bailout on error and nuke correct irq - imx : add support for imx7ulp platform * tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: add support for imx v1 mu dt-bindings: mailbox: imx-mu: add imx7ulp MU support mailbox: imx: Clear the right interrupts at shutdown mailbox: imx: Fix Tx doorbell shutdown path mailbox: stm32-ipcc: Update wakeup management mailbox: no need to set .owner platform_driver_register mailbox/omap: Handle if CONFIG_PM is disabled
| * mailbox: imx: add support for imx v1 muRichard Zhu2019-11-301-17/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: imx: Clear the right interrupts at shutdownDaniel Baluta2019-11-301-2/+13
| | | | | | | | | | | | | | | | | | | | | | Make sure to only clear enabled interrupts keeping count of the connection type. Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: imx: Fix Tx doorbell shutdown pathDaniel Baluta2019-11-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tx doorbell is handled by txdb_tasklet and doesn't have an associated IRQ. Anyhow, imx_mu_shutdown ignores this and tries to free an IRQ that wasn't requested for Tx DB resulting in the following warning: [ 1.967644] Trying to free already-free IRQ 26 [ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358 [ 1.980024] Modules linked in: [ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G [ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT) [ 1.998668] Workqueue: events deferred_probe_work_func [ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 2.008607] pc : __free_irq+0xc0/0x358 [ 2.012364] lr : __free_irq+0xc0/0x358 [ 2.016111] sp : ffff00001179b7e0 [ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018 [ 2.024736] x27: ffff000011233000 x26: 0000000000000004 [ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4 [ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588 [ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400 [ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff [ 2.051320] x17: 0000000000000000 x16: 0000000000000000 [ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517 [ 2.061953] x13: ffff00001179b525 x12: ffff000011142000 [ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970 [ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194 [ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09 [ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000 [ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff [ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000 [ 2.099173] Call trace: [ 2.101618] __free_irq+0xc0/0x358 [ 2.105021] free_irq+0x38/0x98 [ 2.108170] imx_mu_shutdown+0x90/0xb0 [ 2.111921] mbox_free_channel.part.2+0x24/0xb8 [ 2.116453] mbox_free_channel+0x18/0x28 This bug is present from the beginning of times. Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: stm32-ipcc: Update wakeup managementFabien Dessenne2019-11-301-29/+7
| | | | | | | | | | | | | | | | | | | | | | The wakeup specific IRQ management is no more needed to wake up the stm32 platform. A relationship has been established between the EXTI and the RX IRQ, just need to declare the EXTI interrupt instead of the IPCC RX IRQ. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: no need to set .owner platform_driver_registerTian Tao2019-11-261-1/+0
| | | | | | | | | | | | | | the platform_driver_register will set the .owner to THIS_MODULE Signed-off-by: Tian Tao <tiantao6@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 00:25:57 +0000