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* memory: brcmstb_dpfe: add separate entry for compile testKrzysztof Kozlowski2020-08-171-1/+1
| | | | | | | | Add separate entry for Broadcom STB DPFE driver, enabled by default on ARCH_BRCMSTB. This allows compile testing. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'mtd/for-5.9' of ↵Linus Torvalds2020-08-091-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD core changes: - Spelling - http to https updates NAND core changes: - Drop useless 'depends on' in Kconfig - Add an extra level in the Kconfig hierarchy - Trivial spellings - Dynamic allocation of the interface configurations - Dropping the default ONFI timing mode - Various cleanup (types, structures, naming, comments) - Hide the chip->data_interface indirection - Add the generic rb-gpios property - Add the ->choose_interface_config() hook - Introduce nand_choose_best_sdr_timings() - Use default values for tPROG_max and tBERS_max - Avoid redefining tR_max and tCCS_min - Add a helper to find the closest ONFI mode - bcm63xx MTD parsers: simplify CFE detection Raw NAND controller drivers changes: - fsl-upm: Deprecation of specific DT properties - fsl_upm: Driver rework and cleanup in favor of ->exec_op() - Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use - brcmnand: ECC error handling on EDU transfers - brcmnand: Don't default to EDU transfers - qcom: Set BAM mode only if not set already - qcom: Avoid write to unavailable register - gpio: Driver rework in favor of ->exec_op() - tango: ->exec_op() conversion - mtk: ->exec_op() conversion Raw NAND chip drivers changes: - toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4, TC58NVG0S3E, and TC58TEG5DCLTA00 - hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC SPI NOR core changes: - Disable Quad Mode in spi_nor_restore(). - Don't abort BFPT parsing when QER reserved value is used. - Add support/update capabilities for few flashes. - Drop s70fl01gs flash: it does not support RDSR(05h) which is critical for erase/write. - Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts during the release cycle. SPI NOR controller drivers changes: - Move the cadence-quadspi driver to spi-mem. The series was taken through the SPI tree. Merge it also in spi-nor/next to avoid conflicts during the release cycle. - intel-spi: - Add new PCI IDs. - Ignore the Write Disable command, the controller doesn't support it. - Fix performance regression" * tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (79 commits) MTD: pfow.h: drop a duplicated word MTD: mtd-abi.h: drop a duplicated word mtd: rawnand: omap_elm: Replace HTTP links with HTTPS ones mtd: Replace HTTP links with HTTPS ones mtd: hyperbus: Replace HTTP links with HTTPS ones mtd: revert "spi-nor: intel: provide a range for poll_timout" mtd: spi-nor: update read capabilities for w25q64 and s25fl064k mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g mtd: spi-nor: macronix: Add support for mx66u2g45g mtd: spi-nor: intel-spi: Simulate WRDI command mtd: spi-nor: Disable the flash quad mode in spi_nor_restore() mtd: spi-nor: Add capability to disable flash quad mode mtd: spi-nor: spansion: Remove s70fl01gs from flash_info mtd: spi-nor: sfdp: do not make invalid quad enable fatal dt-bindings: mtd: fsl-upm-nand: Deprecate chip-delay and fsl, upm-wait-flags mtd: rawnand: stm32_fmc2: get resources from parent node mtd: rawnand: stm32_fmc2: use regmap APIs memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation dt-bindings: mtd: update STM32 FMC2 NAND controller documentation ...
| * memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driverChristophe Kerello2020-07-071-0/+1
| | | | | | | | | | | | | | | | | | The driver adds the support for the STMicroelectronics FMC2 EBI controller found on STM32MP SOCs. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591975362-22009-5-git-send-email-christophe.kerello@st.com
* | memory: add Renesas RPC-IF driverSergei Shtylyov2020-07-011-0/+1
|/ | | | | | | | | | | | | Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash device depending on the contents of the device tree subnode. It also provides the absract "back end" device APIs that can be used by the "front end" SPI/MTD drivers to talk to the real hardware. Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
* memory: Add Baikal-T1 L2-cache Control Block driverSerge Semin2020-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | Baikal-T1 SoC provides a way to tune the MIPS P5600 CM2 L2-cache performance up. It can be done by changing the L2-RAM Data/Tag/WS latencies in a dedicated register exposed by the system controller. The driver added by this commit provides a dts properties-based and sysfs-based interface for it. The device DT node is supposed to be a child of Baikal-T1 System Controller node. Link: https://lore.kernel.org/r/20200526125928.17096-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'kbuild-v5.3-2' of ↵Linus Torvalds2019-07-201-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull more Kbuild updates from Masahiro Yamada: - match the directory structure of the linux-libc-dev package to that of Debian-based distributions - fix incorrect include/config/auto.conf generation when Kconfig creates it along with the .config file - remove misleading $(AS) from documents - clean up precious tag files by distclean instead of mrproper - add a new coccinelle patch for devm_platform_ioremap_resource migration - refactor module-related scripts to read modules.order instead of $(MODVERDIR)/*.mod files to get the list of created modules - remove MODVERDIR - update list of header compile-test - add -fcf-protection=none flag to avoid conflict with the retpoline flags when CONFIG_RETPOLINE=y - misc cleanups * tag 'kbuild-v5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (25 commits) kbuild: add -fcf-protection=none when using retpoline flags kbuild: update compile-test header list for v5.3-rc1 kbuild: split out *.mod out of {single,multi}-used-m rules kbuild: remove 'prepare1' target kbuild: remove the first line of *.mod files kbuild: create *.mod with full directory path and remove MODVERDIR kbuild: export_report: read modules.order instead of .tmp_versions/*.mod kbuild: modpost: read modules.order instead of $(MODVERDIR)/*.mod kbuild: modsign: read modules.order instead of $(MODVERDIR)/*.mod kbuild: modinst: read modules.order instead of $(MODVERDIR)/*.mod scsi: remove pointless $(MODVERDIR)/$(obj)/53c700.ver kbuild: remove duplication from modules.order in sub-directories kbuild: get rid of kernel/ prefix from in-tree modules.{order,builtin} kbuild: do not create empty modules.order in the prepare stage coccinelle: api: add devm_platform_ioremap_resource script kbuild: compile-test headers listed in header-test-m as well kbuild: remove unused hostcc-option kbuild: remove tag files by distclean instead of mrproper kbuild: add --hash-style= and --build-id unconditionally kbuild: get rid of misleading $(AS) from documents ...
| * memory: ti-emif-sram: move driver-specific asm-offset.h to drivers/memory/Masahiro Yamada2019-07-171-2/+3
| | | | | | | | | | | | | | | | | | <generated/ti-emif-asm-offsets.h> is only generated and included by drivers/memory/, so it does not need to reside in the globally visible include/generated/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
* | memory: move jedec_ddr_data.c from lib/ to drivers/memory/Masahiro Yamada2019-06-171-0/+1
|/ | | | | | | | | | | | | | jedec_ddr_data.c exports 3 symbols, and all of them are only referenced from drivers/memory/{emif.c,of_memory.c} drivers/memory/ is a better location than lib/. I removed the Kconfig prompt "JEDEC DDR data" because it is only select'ed by TI_EMIF, and there is no other user. There is no good reason in making it a user-configurable CONFIG option. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* memory: squash drivers/memory/Makefile.asm-offsetsMasahiro Yamada2019-04-081-2/+5
| | | | | | | | | drivers/memory/Makefile.asm-offsets is small enough, and included from a single place. Squash it into drivers/memory/Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* memory: pl353: Add driver for arm pl353 static memory controllerNaga Sureshkumar Relli2018-12-131-0/+1
| | | | | | | | | Add driver for arm pl353 static memory controller. This controller is used in Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* memory: tegra: Squash tegra20-mc into common tegra-mc driverDmitry Osipenko2018-04-301-1/+0
| | | | | | | | | | | | | | | | | Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Note that this currently doesn't report the value of MC_GART_ERROR_REQ because it is located within the GART register area and cannot be safely accessed from the MC driver (this happens to work only by accident). The proper solution is to integrate the GART driver with the MC driver, much like is done for the Tegra SMMU, but that is an invasive change and will be part of a separate patch series. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: ti-emif-sram: introduce relocatable suspend/resume handlersDave Gerlach2017-12-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain SoCs like Texas Instruments AM335x and AM437x require parts of the EMIF PM code to run late in the suspend sequence from SRAM, such as saving and restoring the EMIF context and placing the memory into self-refresh. One requirement for these SoCs to suspend and enter its lowest power mode, called DeepSleep0, is that the PER power domain must be shut off. Because the EMIF (DDR Controller) resides within this power domain, it will lose context during a suspend operation, so we must save it so we can restore once we resume. However, we cannot execute this code from external memory, as it is not available at this point, so the code must be executed late in the suspend path from SRAM. This patch introduces a ti-emif-sram driver that includes several functions written in ARM ASM that are relocatable so the PM SRAM code can use them. It also allocates a region of writable SRAM to be used by the code running in the executable region of SRAM to save and restore the EMIF context. It can export a table containing the absolute addresses of the available PM functions so that other SRAM code can branch to them. This code is required for suspend/resume on AM335x and AM437x to work. In addition to this, to be able to share data structures between C and the ti-emif-sram-pm assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing emif-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2017-11-161-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "This branch contains platform-related driver updates for ARM and ARM64, these are the areas that bring the changes: New drivers: - driver support for Renesas R-Car V3M (R8A77970) - power management support for Amlogic GX - a new driver for the Tegra BPMP thermal sensor - a new bus driver for Technologic Systems NBUS Changes for subsystems that prefer to merge through arm-soc: - the usual updates for reset controller drivers from Philipp Zabel, with five added drivers for SoCs in the arc, meson, socfpa, uniphier and mediatek families - updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla, Heiner Kallweit and Lorenzo Pieralisi Changes specific to some ARM-based SoC - the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on ARM as well - several changes for power management on Broadcom SoCs - various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek - minor Cleanups for Samsung, TI OMAP SoCs" [ NOTE! This doesn't work without the previous ARM SoC device-tree pull, because the R8A77970 driver is missing a header file that came from that pull. The fact that this got merged afterwards only fixes it at this point, and bisection of that driver will fail if/when you walk into the history of that driver. - Linus ] * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits) soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader bus: add driver for the Technologic Systems NBUS memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg() soc: qcom: remove unused label soc: amlogic: gx pm domain: add PM and OF dependencies drivers/firmware: psci_checker: Add missing destroy_timer_on_stack() dt-bindings: power: add amlogic meson power domain bindings soc: amlogic: add Meson GX VPU Domains driver soc: qcom: Remote filesystem memory driver dt-binding: soc: qcom: Add binding for rmtfs memory of: reserved_mem: Accessor for acquiring reserved_mem of/platform: Generalize /reserved-memory handling soc: mediatek: pwrap: fix fatal compiler error soc: mediatek: pwrap: fix compiler errors arm64: mediatek: cleanup message for platform selection soc: Allow test-building of MediaTek drivers soc: mediatek: place Kconfig for all SoC drivers under menu soc: mediatek: pwrap: add support for MT7622 SoC soc: mediatek: pwrap: add common way for setup CS timing extenstion soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap ..
| * memory: brcmstb: Add driver for DPFEMarkus Mayer2017-09-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | This driver allows access to DRAM properties, such as the refresh rate, via the Broadcom STB DDR PHY Front End (DPFE). The refresh rate can be used as indirect indicator of the DRAM temperature. The driver also allows setting of the sampling interval. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: davinci: add support for da8xx DDR2/mDDR controllerBartosz Golaszewski2016-11-141-0/+1
| | | | | | | | | | | Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* memory: add Atmel EBI (External Bus Interface) driverBoris Brezillon2016-06-021-0/+1
| | | | | | | | | | | | | | | The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
* memory: Add support for Exynos SROM driverPankaj Dubey2016-04-181-0/+1
| | | | | | | | | | | | | This patch adds Exynos SROM controller driver which will handle save restore of SROM registers during S2R. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [p.fedin@samsung.com: tested on SMDK5410] Tested-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org> [k.kozlowski: Minor COMPILE_TEST adjustments in Kconfig entries] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
* memory: mediatek: Add SMI driverYong Wu2016-02-251-0/+1
| | | | | | | | | | | | | This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: add ARM PL172 MultiPort Memory Controller driverJoachim Eastwood2015-07-171-0/+1
| | | | | | | | | | | | | | This driver makes it possible to configure the static memory chip selects on the ARM PL172 MultiPort Memory Controller from a set of properties in DT. Configuration of dynamic memory is not supported and is left to the boot loader. The intended usage is to setup timing and configuration for static memory devices like NAND and NOR Flash before they are probed by a driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCsAlex Smith2015-03-261-0/+1
| | | | | | | | | | | | | | | | Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780 and later SoCs. The primary function of this driver is to configure parameters, such as timings, for external memory devices using data supplied in the device tree. Devices connected to the NEMC are represented in the DT as children of the NEMC node, the driver uses optional properties specified in these child nodes to configure the parameters of each bank. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'omap-gpmc-for-linus' of ↵Linus Torvalds2014-12-091-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC/OMAP GPMC driver cleanup and move from Arnd Bergmann: "The GPMC driver has traditionally been considered a part of the OMAP platform code and tightly interweaved with some of the boards. With this cleanup, it has finally come to the point where it makes sense to move it out of arch/arm into drivers/memory, where we already have other drivers for similar hardware. The cleanups are still ongoing, with the goal of eventually having a standalone driver that does not require an interface to architecture code. This is a separate branch because of dependencies on multiple other branches, and to keep the drivers changes separate from the normal cleanups" * tag 'omap-gpmc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: memory: gpmc: Move omap gpmc code to live under drivers ARM: OMAP2+: Move GPMC initcall to devices.c ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header ARM: OMAP2+: Remove unnecesary include in GPMC driver ARM: OMAP2+: Drop board file for 3430sdp ARM: OMAP2+: Drop board file for ti8168evm ARM: OMAP2+: Drop legacy code for gpmc-smc91x.c ARM: OMAP2+: Require proper GPMC timings for devices ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file ARM: OMAP2+: Fix support for multiple devices on a GPMC chip select ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child() ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()
| * memory: gpmc: Move omap gpmc code to live under driversTony Lindgren2014-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | memory: Add NVIDIA Tegra memory controller supportThierry Reding2014-12-041-1/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'at91-drivers-for-3.17' of ↵Nicolas Ferre2014-08-251-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux Pull AT91 reset, poweroff and ram drivers from Maxime Ripard: "This tag holds the various new drivers introduced to move code that used to be in mach-at91 over to the proper frameworks. These files are the reboot and poweroff code for all AT91 SoCs but the RM9200, and the ram controller driver is not doing much at the time, except for grabing the RAM clock in order to leave it always enabled." Conflicts: arch/arm/mach-at91/Kconfig
| * memory: add a driver for atmel ram controllersAlexandre Belloni2014-07-151-0/+1
| | | | | | | | | | | | | | | | | | | | Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks to run. This driver handle those clocks. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | memory: Freescale CoreNet Coherency Fabric error reporting driverScott Wood2014-07-291-0/+1
|/ | | | | | | | | | | The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
* memory: ti-aemif: introduce AEMIF driverIvan Khoronzhuk2014-02-281-0/+1
| | | | | | | | | | | | | | | | | | | Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* driver/memory:Move Freescale IFC driver to a common driverPrabhakar Kushwaha2014-02-181-0/+1
| | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drivers: memory: Introduce Marvell EBU Device Bus driverEzequiel Garcia2013-05-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: fix build when CONFIG_OF && !CONFIG_DDRStephen Warren2012-09-051-0/+2
| | | | | | | | | | | | | | | | | | | | Commit e6b42eb "memory: emif: add device tree support to emif driver" added drivers/memory/of_memory.c, which references tables defined in lib/jedec_ddr_data.c. of_memory.c is compiled when CONFIG_OF, whereas jedec_ddr_data.c is compiled when CONFIG_DDR. This breaks the build when CONFIG_OF is defined but not CONFIG_DDR: drivers/built-in.o: In function `of_get_ddr_timings': drivers/memory/of_memory.c:138: undefined reference to `lpddr2_jedec_timings' drivers/built-in.o: In function `of_get_min_tck': drivers/memory/of_memory.c:62: undefined reference to `lpddr2_jedec_min_tck' make: *** [vmlinux] Error 1 To solve this, only compile of_memory.c when CONFIG_OF && CONFIG_DDR, otherwise, stub out the functions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: add device tree support to emif driverAneesh V2012-09-041-0/+1
| | | | | | | | | | | | | | | Device tree support for the EMIF driver. LPDDR2 generic timings extraction from device is managed using couple of helper functions which can be used by other memory controller drivers. Reviewed-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: tegra30: Add Tegra Memory Controller(MC) driverHiroshi DOYU2012-05-101-0/+1
| | | | | | | | | Tegra Memory Controller(MC) driver for Tegra30 Added to support MC General interrupts, mainly for IOMMU(SMMU). Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: tegra20: Add Tegra Memory Controller(MC) driverHiroshi DOYU2012-05-101-0/+1
| | | | | | | | | Tegra Memory Controller(MC) driver for Tegra20 Added to support MC General interrupts, mainly for IOMMU(GART). Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: add basic infrastructure for EMIF driverAneesh V2012-05-021-0/+5
EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>