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* memory: tegra: Correct tegra210_mc_clients def valuesNicolin Chen2020-10-271-14/+14
| | | | | | | | | | Some def values are mismatched with Tegra X1 TRM, probably because being copied from tegra124.c file. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201008003746.25659-3-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* memory: tegra: Correct la.reg address of seswrNicolin Chen2020-10-271-1/+1
| | | | | | | | | | | | According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2020-10-245-25/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
| * memory: tegra: Convert to DEFINE_SHOW_ATTRIBUTEQinglang Miao2020-09-201-13/+1
| | | | | | | | | | | | | | | | Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Link: https://lore.kernel.org/r/20200917125114.103598-1-miaoqinglang@huawei.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * memory: tegra: Delete duplicated argument to '|' in function ↵Ye Bin2020-09-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | tegra210_emc_r21021_periodic_compensation In function tegra210_emc_r21021_periodic_compensation when calculate emc_cfg EMC_CFG_DRAM_CLKSTOP_PD is duplicated. Signed-off-by: Ye Bin <yebin10@huawei.com> Link: https://lore.kernel.org/r/20200903021542.315195-1-yebin10@huawei.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * memory: tegra: Remove GPU from DRM IOMMU groupThierry Reding2020-09-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group") added the GPU to the DRM IOMMU group, which doesn't make any sense. This causes problems when Nouveau tries to attach to the SMMU and causes it to fall back to using the DMA API. Remove the GPU from the DRM groups to restore the old behaviour. The GPU should always have its own IOMMU domain to make sure it can map buffers into contiguous chunks (for big page support) without getting in the way of mappings from the DRM group. Cc: <stable@vger.kernel.org> Fixes: 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group") Reported-by: Matias Zuniga <matias.nicolas.zc@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200901153248.1831263-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * memory: tegra186-emc: Simplify with dev_err_probe()Krzysztof Kozlowski2020-09-021-8/+2
| | | | | | | | | | | | | | | | Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200828153747.22358-2-krzk@kernel.org
| * memory: tegra: Correct shift value of apewNicolin Chen2020-08-201-1/+1
| | | | | | | | | | | | | | | | | | According to Tegra X1 (Tegra210) TRM, the APEW field is between [23:16] so the shift bit for apew should be 16 accordingly. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200818095121.13645-1-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * memory: tegra: tegra210-emc: fix indentationKrzysztof Kozlowski2020-08-171-1/+1
| | | | | | | | | | | | | | Use tabs instead of spaces for indentation. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-25-krzk@kernel.org
* | memory: tegra: Correct num_tlb_lines for tegra210Nicolin Chen2020-09-181-1/+1
|/ | | | | | | | | | | According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines should be 48 (0x30) rather than 32 (0x20). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200917113155.13438-3-nicoleotsuka@gmail.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: tegra: Add Tegra132 compatible string matchThierry Reding2020-07-151-0/+1
| | | | | | | | | | Ensure that the driver will bind against the Tegra132 instantiation of the external memory controller. While the two are roughly the same from a capability perspective, they do require some incompatible changes to the programming sequences and therefore need separate compatible strings. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Fix KCONFIG variables for Tegra186 and Tegra194Jon Hunter2020-07-141-2/+2
| | | | | | | | | | | | | | Commit a127e690b051 ("memory: tegra: Add support for the Tegra194 memory controller") and commit 4e04b88633ae ("memory: tegra: Only include support for enabled SoCs") incorrectly added the KCONFIG variables CONFIG_ARCH_TEGRA186_SOC and CONFIG_ARCH_TEGRA194_SOC to the Tegra EMC driver. These KCONFIG variables do not exist and prevent the EMC driver from being probed on Tegra186 and Tegra194. These KCONFIG variable names are simply missing one underscore and so fix this by adding the necessary underscore to the variable names. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Delete some dead codeDan Carpenter2020-06-221-5/+0
| | | | | | | | | | The debugfs_create_dir() function never returns NULL and anyway the correct behavior is to ignore errors in this situation. The debugfs_create_file() will become a no-op if "emc->debugfs.root" is an error pointer. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Avoid unused function warningsArnd Bergmann2020-06-221-2/+2
| | | | | | | | | | | | | | | | | | The suspend/resume functions have no callers depending on configuration, so they must be marked __maybe_unused to avoid these harmless warnings: drivers/memory/tegra/tegra186.c:1578:12: error: 'tegra186_mc_resume' defined but not used [-Werror=unused-function] 1578 | static int tegra186_mc_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~ drivers/memory/tegra/tegra186.c:1573:12: error: 'tegra186_mc_suspend' defined but not used [-Werror=unused-function] 1573 | static int tegra186_mc_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ Fixes: 177602b00641 ("memory: tegra: Add system sleep support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Drop <linux/clk-provider.h>Geert Uytterhoeven2020-06-222-2/+0
| | | | | | | | | | The Tegra EMC scaling support code is not a clock provider, but merely a clock consumer, and thus does not need to include <linux/clk-provider.h>. Fixes: 0bf368c5b2cf ("memory: tegra: Add EMC scaling support code for Tegra210") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Fix an error handling path in tegra186_emc_probe()Christophe JAILLET2020-06-221-5/+11
| | | | | | | | | | | | The call to tegra_bpmp_get() must be balanced by a call to tegra_bpmp_put() in case of error, as already done in the remove function. Add an error handling path and corresponding goto. Fixes: 52d15dd23f0b ("memory: tegra: Support DVFS on Tegra186 and later") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko2020-06-221-72/+44
| | | | | | | | | | | | | | The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko2020-06-221-17/+11
| | | | | | | | | | | | | | The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Support derated timings on Tegra210Thierry Reding2020-06-224-13/+363
| | | | | | | | | | | Derated timings are used to ensure that the memory chips keep operating correctly at high temperatures. This adds code to support polling of the chip operating state when high temperatures are measured on the chip and change the refresh mode accordingly. Under very high temperatures, the driver will switch to the derated tables to ensure proper operation of the memory chips. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Add EMC scaling sequence code for Tegra210Joseph Lo2020-06-224-1/+1875
| | | | | | | | | | | | | | | This patch includes the sequence for clock tuning and the dynamic training mechanism for the clock above 800MHz. And historically there have been different sequences to change the EMC clock. The sequence to be used is specified in the EMC table. However, for the currently supported upstreaming platform, only the most recent sequence is used. So only support that in this patch. Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Add EMC scaling support code for Tegra210Joseph Lo2020-06-227-0/+2828
| | | | | | | | | | | | | | | | | | | | | | | | This is the initial patch for Tegra210 EMC frequency scaling. It has the code to program various aspects of the EMC that are standardized, but it does not yet include the specific programming sequence needed for clock scaling. The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 need to perform training of the RAM before it can be used. Firmware will perform this training during early boot and pass a table of supported frequencies to the kernel via device tree. For the frequencies above 800 MHz, periodic retraining is needed to compensate for changes in timing. This periodic training will have to be performed until the frequency drops back to or below 800 MHz. This driver provides helpers used during this runtime retraining that will be used by the sequence specific code in a follow-up patch. Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Make debugfs permissions human-readableDmitry Osipenko2020-06-223-9/+9
| | | | | | | | Replace the symbolic permissions with octals in order to make them readable. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Correct debugfs clk rate-range on Tegra124Dmitry Osipenko2020-03-111-0/+5
| | | | | | | | | | Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 6b9acd935546 ("memory: tegra: Refashion EMC debugfs interface on Tegra124") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Correct debugfs clk rate-range on Tegra30Dmitry Osipenko2020-03-111-0/+5
| | | | | | | | | | Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Correct debugfs clk rate-range on Tegra20Dmitry Osipenko2020-03-111-0/+5
| | | | | | | | | | Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra30-emc: Correct error message for timed out auto calibrationDmitry Osipenko2020-01-101-2/+1
| | | | | | | The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra30-emc: Firm up hardware programming sequenceDmitry Osipenko2020-01-101-61/+89
| | | | | | | | | | | | | | | | | Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra30-emc: Firm up suspend/resume sequenceDmitry Osipenko2020-01-101-18/+20
| | | | | | | | | The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Correct reset value of xusb_hostrNicolin Chen2020-01-101-1/+1
| | | | | | | | According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Add support for the Tegra194 memory controllerThierry Reding2020-01-093-0/+953
| | | | | | | | The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Only include support for enabled SoCsThierry Reding2020-01-092-0/+8
| | | | | | | The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Support DVFS on Tegra186 and laterThierry Reding2020-01-093-3/+304
| | | | | | | | | | | | | Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Add system sleep supportThierry Reding2020-01-091-0/+19
| | | | | | | | Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Extract memory client SID programmingThierry Reding2020-01-091-22/+27
| | | | | | | Move programming of the memory client to SID mapping into a separate function so that it can be reused from multiple call sites. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Add per-SoC data for Tegra186Thierry Reding2020-01-091-10/+19
| | | | | | | Instead of hard-coding the memory client table, use per-SoC data in preparation for adding support for other SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186Thierry Reding2020-01-091-4/+10
| | | | | | This is just for consistency with the rest of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Implement EMC debugfs interface on Tegra30Thierry Reding2020-01-091-0/+173
| | | | | | | | A common debugfs interface is already available on Tegra20, Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Implement EMC debugfs interface on Tegra20Thierry Reding2020-01-091-0/+175
| | | | | | | | A common debugfs interface is already available on Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra20 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Refashion EMC debugfs interface on Tegra124Thierry Reding2020-01-091-42/+143
| | | | | | | | | | The current debugfs interface is only partially useful. While it allows listing supported frequencies and testing individual clock rates, it is limited in that it can't be used to restrict the range of frequencies that the driver is allowed to set. This is something we may want to use to test adaptive scaling once that's implemented. Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra30-emc: Fix panic on suspendDmitry Osipenko2019-11-181-1/+1
| | | | | | | | | | | | Trying to suspend driver results in a crash if timings aren't available in device-tree. Reported-by: Jon Hunter <jonathanh@nvidia.com> Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Consolidate registers definition into common headerDmitry Osipenko2019-11-114-74/+47
| | | | | | | | | The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Ensure timing control debug features are disabledDmitry Osipenko2019-11-112-0/+5
| | | | | | | | | | Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Introduce Tegra30 EMC driverDmitry Osipenko2019-11-116-14/+1310
| | | | | | | | | | | | Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Do not handle error from wait_for_completion_timeout()Dmitry Osipenko2019-11-111-5/+1
| | | | | | | | Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Increase handshake timeout on Tegra20Dmitry Osipenko2019-11-111-1/+1
| | | | | | | | | | | Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Print a brief info message about EMC timingsDmitry Osipenko2019-11-111-0/+7
| | | | | | | | | | During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Pre-configure debug register on Tegra20Dmitry Osipenko2019-11-111-1/+16
| | | | | | | | | | The driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Include io.h instead of iopoll.hDmitry Osipenko2019-11-111-1/+1
| | | | | | | | | The register polling code was gone, but the included header change was missed. Fix it up for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Adapt for Tegra20 clock driver changesDmitry Osipenko2019-11-111-2/+48
| | | | | | | | | Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra clock driver API. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* memory: tegra: Don't set EMC rate to maximum on probe for Tegra20Dmitry Osipenko2019-11-111-77/+1
| | | | | | | | | | | | | The memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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