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* mmc: pxamci: fix again read-only gpio detection polarityRobert Jarzmik2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | commit 41c89159a6ae5472d39ed8bded5b3b4e07a37944 upstream. The commit fixing the conversion of pxamci to slot-gpio API fixed the inverted the logic of the read-only gpio. Unfortunately, the commit was tested on a non-inverted gpio, and not on the inverted one. And the fix did work partially, by luck. This is the remaining missing part of the fix, trivial but still necessary. Fixes: Fixes: 26d49fe71953 ("mmc: pxamci: fix read-only gpio detection polarity") Reported-by: Andrea Adami <andrea.adami@gmail.com> Tested-by: Andrea Adami <andrea.adami@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci-acpi: Fix card detect race for Intel BXT/APLAdrian Hunter2016-03-031-0/+30
| | | | | | | | | | | | | | | | | | | | commit 6a645dd87a5a506779810d7d9935c25fc2ef4687 upstream. Intel BXT/APL use a card detect GPIO however the host controller will not enable bus power unless it's card detect also reflects the presence of a card. Unfortunately those 2 things race which can result in commands not starting, after which the controller does nothing and there is a 10 second wait for the driver's 10-second timer to timeout. That is fixed by having the driver look also at the present state register to determine if the card is present. Consequently, provide a 'get_cd' mmc host operation for BXT/APL that does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: mmci: fix an ages old detection errorLinus Walleij2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | commit 0bcb7efdff63564e80fe84dd36a9fbdfbf6697a4 upstream. commit 4956e10903fd ("ARM: 6244/1: mmci: add variant data and default MCICLOCK support") added variant data for ARM, U300 and Ux500 variants. The Nomadik NHK8815/8820 variant was erroneously labeled as a U300 variant, and when the proper Nomadik variant was later introduced in commit 34fd421349ff ("ARM: 7378/1: mmci: add support for the Nomadik MMCI variant") this was not fixes. Let's say this fixes the latter commit as there was no proper Nomadik support until then. Fixes: 34fd421349ff ("ARM: 7378/1: mmci: add support for the Nomadik...") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci: Fix sdhci_runtime_pm_bus_on/off()Adrian Hunter2016-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | commit 5c671c410c8704800f4f1673b6f572137e7e6ddd upstream. sdhci has a legacy facility to prevent runtime suspend if the bus power is on. This is needed in cases where the power to the card is dependent on the bus power. It is controlled by a pair of functions: sdhci_runtime_pm_bus_on() and sdhci_runtime_pm_bus_off(). These functions use a boolean variable 'bus_on' to ensure changes are always paired. There is an additional check for 'runtime_suspended' which is the problem. In fact, its use is ill-conceived as the only requirement for the logic is that 'on' and 'off' are paired, which is actually broken by the check, for example if the bus power is turned on during runtime resume. So remove the check. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci: Fix DMA descriptor with zero data lengthAdrian Hunter2016-03-031-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 347ea32dc118326c4f2636928239a29d192cc9b8 upstream. SDHCI has built-in DMA called ADMA2. ADMA2 uses a descriptor table to define DMA scatter-gather. Each desciptor can specify a data length up to 65536 bytes, however the length field is only 16-bits so zero means 65536. Consequently, putting zero when the size is zero must not be allowed. This patch fixes one case where zero data length could be set inadvertently. The problem happens because unaligned data gets split and the code did not consider that the remaining aligned portion might be zero length. That case really only happens for SDIO because SD and eMMC cards transfer blocks that are invariably sector- aligned. For SDIO, access to function registers is done by data transfer (CMD53) when the register is bigger than 1 byte. Generally registers are 4 bytes but 2-byte registers are possible. So DMA of 4 bytes or less can happen. When 32-bit DMA is used, the data alignment must be 4, so 4-byte transfers won't casue a problem, but a 2-byte transfer could. However with the introduction of 64-bit DMA, the data alignment for 64-bit DMA was made 8 bytes, so all 4-byte transfers not on 8-byte boundaries get "split" into a 4-byte chunk and a 0-byte chunk, thereby hitting the bug. In fact, a closer look at the SDHCI specs indicates that only the descriptor table requires 8-byte alignment for 64-bit DMA. That will be dealt with in a separate patch, but the potential for a 2-byte access remains, so this fix is needed anyway. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci-pci: Do not default to 33 Ohm driver strength for Intel SPTAdrian Hunter2016-03-031-1/+1
| | | | | | | | | | | | | | | | commit 1ca896856281d3f1ad4f6f7d4e32e2943452de23 upstream. In some cases, the stronger 33 Ohm driver strength must not be used so it is not a suitable default. Change it to the standard default 50 Ohm value. The patch applies to v4.2+ except the file name changed. It is drivers/mmc/host/sdhci-pci.c prior to v.4.4. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: usdhi6rol0: handle NULL data in timeoutRabin Vincent2016-03-031-1/+2
| | | | | | | | | | | | | | | | commit 05caee939f8d58d81e962071da85761e1e3a4c73 upstream. Commit bb08a7d489bd ("mmc: usdhi6rol0: fix NULL pointer deref in debug print") fixed one NULL pointer dereference but unfortunately introduced another. "data" may be NULL if this is a command timeout for a command without any data, so we should only use it if we're actually waiting for data. Fixes: bb08a7d489bd ("mmc: usdhi6rol0: fix NULL pointer deref in debug print") Signed-off-by: Rabin Vincent <rabin.vincent@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: MMC_GOLDFISH should depend on HAS_DMAGeert Uytterhoeven2015-11-091-0/+1
| | | | | | | | | | | | | | If NO_DMA=y: ERROR: dma_unmap_sg [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_alloc_coherent [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_map_sg [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_free_coherent [drivers/mmc/host/android-goldfish.ko] undefined! Add a dependency on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mediatek: Preinitialize delay_phase in get_best_delay()Geert Uytterhoeven2015-11-091-1/+1
| | | | | | | | | | | | drivers/mmc/host/mtk-sd.c: In function ‘get_best_delay’: drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.start’ is used uninitialized in this function drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.maxlen’ is used uninitialized in this function If delay is zero, these fields are indeed not initialized. Let the compiler preinitialize the whole struct to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: pxamci: fix read-only gpio detection polarityRobert Jarzmik2015-11-091-1/+1
| | | | | | | | | | The commit converting pxamci to slot-gpio API inverted the logic of the read-only gpio. Fix it by inverting the logic again. Fixes: fd546ee6a7dc ("mmc: pxamci: fix card detect with slot-gpio API") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Merge tag 'spi-v4.4' of ↵Linus Torvalds2015-11-051-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "Quite a lot of activity in SPI this cycle, almost all of it in drivers with a few minor improvements and tweaks in the core. - Updates to pxa2xx to support Intel Broxton and multiple chip selects. - Support for big endian in the bcm63xx driver. - Multiple slave support for the mt8173 - New driver for the auxiliary SPI controller in bcm2835 SoCs. - Support for Layerscale SoCs in the Freescale DSPI driver" * tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits) spi: pxa2xx: Rework self-initiated platform data creation for non-ACPI spi: pxa2xx: Add support for Intel Broxton spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals spi: pxa2xx: Add output control for multiple Intel LPSS chip selects spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific spi: Add DSPI support for layerscape family spi: ti-qspi: improve ->remove() callback spi/spi-xilinx: Fix race condition on last word read spi: Drop owner assignment from spi_drivers spi: Add THIS_MODULE to spi_driver in SPI core spi: Setup the master controller driver before setting the chipselect spi: dw: replace magic constant by DW_SPI_DR spi: mediatek: mt8173 spi multiple devices support spi: mediatek: handle controller_data in mtk_spi_setup spi: mediatek: remove mtk_spi_config spi: mediatek: Update document devicetree bindings to support multiple devices spi: fix kernel-doc warnings about missing return desc in spi.c spi: fix kernel-doc warnings about missing return desc in spi.h spi: pxa2xx: Align a few defines spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select ...
| *-. Merge remote-tracking branches 'spi/topic/omap-100k', ↵Mark Brown2015-11-041-1/+0
| |\ \ | | | | | | | | | | | | 'spi/topic/omap-uwire', 'spi/topic/owner', 'spi/topic/pxa' and 'spi/topic/pxa2xx' into spi-next
| | | * spi: Drop owner assignment from spi_driversAndrew F. Davis2015-10-281-1/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | An spi_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | mmc: dw_mmc: fix the wrong setting for UHS-DDR50 modeJaehoon Chung2015-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When card is running with DDR mode, dwmmc needs to set DDR_REG bit at UHS_REG register. Before this patch, dwmmc controller doesn't consider this. If this patch is not applied, CRC or other error shoulds be occurred. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl registerJaehoon Chung2015-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to DesignWare DoC file, CardThreshold bit should be bit[27:16]. So it's correct to use (0xFFF << 16), not (0x1FFF << 16). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: NULL dereference in error messageDan Carpenter2015-10-291-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The "host->dms->ch" pointer is NULL here so we can't use it to print the error message. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: add HS400 supportChaotian Jing2015-10-271-5/+244
| | | | | | | | | | | | | | | | | | | | | add HS400 mode and tune support Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mmc: extend the mmc_send_tuning()Chaotian Jing2015-10-277-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc_execute_tuning() has already prepared the opcode, there is no need to prepare it again at mmc_send_tuning(), and, there is a BUG of mmc_send_tuning() to determine the opcode by bus width, assume eMMC was running at HS200, 4bit mode, then the mmc_send_tuning() will overwrite the opcode from CMD21 to CMD19, then got error. in addition, extend an argument of "cmd_error" to allow getting if there was cmd error when tune response. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> [Ulf: Rebased patch] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: add implement of ops->hw_reset()Chaotian Jing2015-10-271-0/+11
| | | | | | | | | | | | | | | | | | | | | add implement of ops->hw_reset() for eMMC Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: fix got GPD checksum error interrupt when data transferChaotian Jing2015-10-271-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Even if we only use one gpd, we need alloc 2 gpd and make the gpd->next pointer to the second gpd, or may get gpd checksum error, this was checked by hardware Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: change the argument "ddr" to "timing"Chaotian Jing2015-10-271-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | use the ios->timing directly is better It can reflect current timing and do settings by timing Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: make cmd_ints_mask to constChaotian Jing2015-10-271-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | cmd_ints_mask and data_ints_mask are constant value, so make it to const Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2Lokesh Vutla2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable omap_hsmmc for Keystone 2 architecture which reuses the HSMMC IP found on OMAP platforms. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllersAdrian Hunter2015-10-261-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add ACPI HIDs for Intel host controllers including one supporting HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: Add more PCI IDs for Intel controllersAdrian Hunter2015-10-262-0/+54
| | | | | | | | | | | | | | | | | | | | | Add PCI IDs for Intel host controllers Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: use macro for HCON register operationsShawn Lin2015-10-262-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add some macros for HCON register operations to make code more readable. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: Add external dma interface supportShawn Lin2015-10-264-62/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DesignWare MMC Controller can supports two types of DMA mode: external dma and internal dma. We get a RK312x platform integrated dw_mmc and ARM pl330 dma controller. This patch add edmac ops to support these platforms. I've tested it on RK31xx platform with edmac mode and RK3288 platform with idmac mode. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-esdhc: avoid writing power control registeryangbo lu2015-10-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The eSDHC doesn't have a standard power control register, so when writing this register in stack we should do nothing to avoid incorrect operation. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: android-goldfish: Allow compiling the driver with COMPILE_TESTLuis de Bethencourt2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver depends on GOLDFISH but there isn't a build dependency so it's a good idea to allow the driver to always be built when the COMPILE_TEST option is enabled. That way, the driver can be built with a config generated by make allyesconfig and check if a patch would break the build. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc-rockchip: MMC tuning with the clock phase frameworkAlexandru M Stan2015-10-261-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm will try 1 degree increments, since there's no way to tell what resolution the underlying phase code uses. As an added bonus, doing many tunings yields better results since some tests are run more than once (ex: if the underlying driver uses 45 degree increments, the tuning code will try the same angle more than once). It will then construct a list of good phase ranges (even ranges that cross 360/0), will pick the biggest range then it will set the sample_clk to the middle of that range. We do not touch ciu_drive (and by extension define default-drive-phase). Drive phase is mostly used to define minimum hold times, while one could write some code to determine what phase meets the minimum hold time (ex 10 degrees) this will not work with the current clock phase framework (which floors angles, so we'll get 0 deg, and there's no way to know what resolution the floors happen at). We assume that the default drive angles set by the hardware are good enough. If a device has device specific code (like exynos) then that will still take precedence, otherwise this new code will execute. If the device wants to tune, but has no sample_clk defined we'll return EIO with an error message. Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: Use mmc_regulator_set_vqmmc in start_signal_voltage_switchDouglas Anderson2015-10-261-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've introduced a new helper in the MMC core: mmc_regulator_set_vqmmc(). Let's use this in dw_mmc. Using this new helper has some advantages: 1. We get the mmc_regulator_set_vqmmc() behavior of trying to match VQMMC and VMMC when the signal voltage is 3.3V. This ensures max compatibility. 2. We get rid of a few more warnings when probing unsupported voltages. 3. We get rid of some non-dw_mmc specific code in dw_mmc. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-esdhc: add quirk SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for ls1021ayangbo lu2015-10-261-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: kconfig: reconfigure MMC_SDHCI_OF_ESDHC optionyangbo lu2015-10-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale eSDHC driver now supports both little-endian and big-endian mode eSDHC IPs for ARM and PPC. So, MMC_SDHCI_OF_ESDHC option needs to be reconfigured. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-esdhc: support both BE and LE host controlleryangbo lu2015-10-262-112/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support little endian eSDHC controller, we redefine both BE and LE IO accessors. In the new accessors, use ioread*/iowrite* instead of in_be32/out_be32 and will select accessors according to endian mode in probe function. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: Add another PCI ID for an Intel eMMC host controllerAdrian Hunter2015-10-262-0/+9
| | | | | | | | | | | | | | | | | | | | | Add another PCI ID for an Intel eMMC host controller. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: fix simple_return.cocci warningskbuild test robot2015-10-261-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/mmc/host/sdhci-pci-core.c:447:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: Make sdhci_pci_o2_fujin2_pci_init() staticBen Hutchings2015-10-262-3/+1
| | | | | | | | | | | | | | | | | | | | | It has no external callers. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: Build o2micro support in the same moduleBen Hutchings2015-10-263-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci-pci-o2micro.c contains no initialisation and its functions are only called from shdci-pci.c, so there is no reason for it to be a separate module, let alone or for it to always be built-in. - Rename sdhci-pci.c to sdhci-pci-core.c so that the sdhci-pci module can be built from multiple source files - Add sdhci-pci-o2micro.c to it - Remove redundant exports Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sirf: fix the capbility to support DDR50Weijun Yang2015-10-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to hardware spec, validate DDR50 mode for SDXC. Signed-off-by: Weijun Yang <york.yang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: enable tuning for DDR50Weijun Yang2015-10-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | CMD19 tuning is also available for DDR50 mode. Signed-off-by: Weijun Yang <york.yang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sunxi: Add card busy detectionHans de Goede2015-10-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some sdio wifi modules have not been working reliable with the sunxi-mmc host code. This turns out to be caused by starting new io-rw commands while the card signals that it is still busy processing a previous command. This commit adds card-busy detection to the sunxi-mmc driver which together with recent core changes to check card-busy before starting io-rw commands fixes the wifi reliability issues on the Cubietruck and other sunxi boards using sdio wifi. Reported-by: Eugene K <sigintmailru@gmail.com> Suggested-by: Eugene K <sigintmailru@gmail.com> Cc: Eugene K <sigintmailru@gmail.com> Cc: Arend van Spriel <arend@broadcom.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pltfm: enable interrupt mode to detect card for ls1021aYangbo Lu2015-10-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable interrupt mode to detect card instead of polling mode for ls1021a by removing the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data transferring performance and avoid the call trace caused by polling card status sometime. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: Add MMC_CAP_RUNTIME_RESUME supportChaotian Jing2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add MMC_CAP_RUNTIME_RESUME support to save resume time Drop unnecessary SDC_ARG write Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: omap: Fix module autoload for OF platform driverLuis de Bethencourt2015-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: moxart: Fix module autoload for OF platform driverLuis de Bethencourt2015-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pltfm: Use of_property_read_u32 instead of open-coding itTobias Klauser2015-10-261-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use of_property_read_u32 instead of of_get_property with return value checks and endianness conversion. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mmc_spi: Export OF module alias informationJavier Martinez Canillas2015-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drivers needs to export the OF id table and this be built into the module or udev won't have the necessary information to autoload the driver module when the device is registered via OF. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-at91: remove a line of dead codeDan Carpenter2015-10-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The goto is correct and the unreachable "return -EINVAL" should be removed. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: call sdhci_init() before request irqHaibo Chen2015-10-261-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci_init() will clear all irqs and set the needed irqs. So logically sdhci_init() should be called before request irq. If not, some irqs may be triggled and handled wrongly. Take the following into consideration, after request irq, if SDIO card interrupt enabled, a sd card in the sd slot will trigger a mass of interrupt(SDHCI_INT_CARD_INT), because at this time, the vmmc-regulator still not restore, no voltage supply for the sd card, so the pin of data0~data3 change and keep low, interrupt(SDHCI_INT_CARD_INT) will rise up ceaselessly. Due to we already reguest irq, system will be busy in handling this endless irq, can't response to other event. So we should call sdhci_init() before request irq in sd resume. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-bcm-kona: fix logic to check for 8-bit data widthJavier Martinez Canillas2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver prints if the data width is 8-bit but it's using a binary OR instead of a binary AND so it will always report as "is_8bit=Y" regardless of the flags in host->mmc->caps. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 13:54:40 +0000