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* mmc: dw_mmc: fix the spamming log messageJaehoon Chung2016-09-222-5/+12
| | | | | | | | | | | When there is no Card which is set to "broken-cd", it's displayed a clock information continuously. Because it's polling for detecting card. This patch is fixed this problem. Fixes: 65257a0deed5 ("mmc: dw_mmc: remove UBSAN warning in dw_mci_setup_bus()") Reported-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap: Initialize dma_slave_config to avoid random data in it's fieldsPeter Ujfalusi2016-09-141-8/+10
| | | | | | | | | It is wrong to use uninitialized dma_slave_config and configure only certain fields as the DMAengine driver might look at non initialized (random data) fields and tries to interpret it. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: Initialize dma_slave_config to avoid random dataPeter Ujfalusi2016-09-141-8/+8
| | | | | | | | | It is wrong to use uninitialized dma_slave_config and configure only certain fields as the DMAengine driver might look at non initialized (random data) fields and tries to interpret it. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-st: Handle interconnect clockLee Jones2016-09-121-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some ST platforms contain interconnect (ICN) clocks which must be handed correctly in order to obtain full functionality of a given IP. In this case, if the ICN clocks are not handled properly by the ST SDHCI driver MMC will break and the following output can be observed: [ 13.916949] mmc0: Timeout waiting for hardware interrupt. [ 13.922349] sdhci: =========== REGISTER DUMP (mmc0)=========== [ 13.928175] sdhci: Sys addr: 0x00000000 | Version: 0x00001002 [ 13.933999] sdhci: Blk size: 0x00007040 | Blk cnt: 0x00000001 [ 13.939825] sdhci: Argument: 0x00fffff0 | Trn mode: 0x00000013 [ 13.945650] sdhci: Present: 0x1fff0206 | Host ctl: 0x00000011 [ 13.951475] sdhci: Power: 0x0000000f | Blk gap: 0x00000080 [ 13.957300] sdhci: Wake-up: 0x00000000 | Clock: 0x00003f07 [ 13.963126] sdhci: Timeout: 0x00000004 | Int stat: 0x00000000 [ 13.968952] sdhci: Int enab: 0x02ff008b | Sig enab: 0x02ff008b [ 13.974777] sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 [ 13.980602] sdhci: Caps: 0x21ed3281 | Caps_1: 0x00000000 [ 13.986428] sdhci: Cmd: 0x0000063a | Max curr: 0x00000000 [ 13.992252] sdhci: Host ctl2: 0x00000000 [ 13.996166] sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x7c048200 [ 14.001990] sdhci: =========================================== [ 14.009802] mmc0: Got data interrupt 0x02000000 even though no data operation was in progress. A decent point was raised about minimising the use of a local variable that we 'could' do without. I've chosen consistency over the possibility of reducing the local variable count by 1. Thinking that it's more important for the code to be grouped and authoured in a similar manner/style for greater maintainability/readability. Cc: stable@vger.kernel.org Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: fix use-after-free of struct requestAdrian Hunter2016-08-252-3/+5
| | | | | | | | | | | | We call mmc_req_is_special() after having processed a request, but it could be freed after that. Check that ahead of time, and use the cached value. Reported-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Fixes: c2df40dfb8c0 ("drivers: use req op accessor") Signed-off-by: Jens Axboe <axboe@fb.com>
* block: Fix secure eraseAdrian Hunter2016-08-163-2/+6
| | | | | | | | | | Commit 288dab8a35a0 ("block: add a separate operation type for secure erase") split REQ_OP_SECURE_ERASE from REQ_OP_DISCARD without considering all the places REQ_OP_DISCARD was being used to mean either. Fix those. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 288dab8a35a0 ("block: add a separate operation type for secure erase") Signed-off-by: Jens Axboe <axboe@fb.com>
* Merge tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmcLinus Torvalds2016-07-3151-941/+1788
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MMC updates from Ulf Hansson: "MMC core: - A couple of changes to improve the support for erase/discard/trim cmds - Add eMMC HS400 enhanced strobe support - Show OCR and DSR registers in SYSFS for MMC/SD cards - Correct and improve busy detection logic for MMC switch (CMD6) cmds - Disable HPI cmds for certain broken Hynix eMMC cards - Allow MMC hosts to specify non-support for SD and MMC cmds - Some minor additional fixes MMC host: - sdhci: Re-works, fixes and clean-ups - sdhci: Add HW auto re-tuning support - sdhci: Re-factor code to prepare for adding support for eMMC CMDQ - sdhci-esdhc-imx: Fixes and clean-ups - sdhci-esdhc-imx: Update system PM support - sdhci-esdhc-imx: Enable HW auto re-tuning - sdhci-bcm2835: Remove driver as sdhci-iproc is used instead - sdhci-brcmstb: Add new driver for Broadcom BRCMSTB SoCs - sdhci-msm: Add support for UHS cards - sdhci-tegra: Improve support for UHS cards - sdhci-of-arasan: Update phy support for Rockchip SoCs - sdhci-of-arasan: Deploy enhanced strobe support - dw_mmc: Some fixes and clean-ups - dw_mmc: Enable support for erase/discard/trim cmds - dw_mmc: Enable CMD23 support - mediatek: Some fixes related to the eMMC HS400 support - sh_mmcif: Improve support for HW busy detection - rtsx_pci: Enable support for erase/discard/trim cmds" * tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmc: (135 commits) mmc: rtsx_pci: Remove deprecated create_singlethread_workqueue mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests mmc: rtsx_pci: Use the provided busy timeout from the mmc core mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPS mmc: sdhci-pltfm: Convert to use the SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pltfm: Make sdhci_pltfm_suspend|resume() static mmc: sdhci-esdhc-imx: Use common sdhci_suspend|resume_host() mmc: sdhci-esdhc-imx: Assign system PM ops within #ifdef CONFIG_PM_SLEEP mmc: sdhci-sirf: Remove non needed #ifdef CONFIG_PM* for dev_pm_ops mmc: sdhci-s3c: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-pxav3: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-of-esdhc: Simplify code by using SIMPLE_DEV_PM_OPS mmc: sdhci-acpi: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pci-core: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: Change the max discard sectors and erase response when HW busy detect phy: rockchip-emmc: Wait even longer for the DLL to lock phy: rockchip-emmc: Be tolerant to card clock of 0 in power on mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes mmc: sdhci-msm: Add support for UHS cards mmc: sdhci-msm: Add set_uhs_signaling() implementation ...
| * mmc: rtsx_pci: Remove deprecated create_singlethread_workqueueBhaktipriya Shridhar2016-07-291-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workqueue "workq" provides support for sd/mmc async request, which makes next request do dma_map_sg() while previous request transferring data. The workqueue has a single workitem(&host->work) and hence doesn't require ordering. Also, it is not being used on a memory reclaim path. Hence, the singlethreaded workqueue has been replaced with the use of system_wq. System workqueues have been able to handle high level of concurrency for a long time now and hence it's not required to have a singlethreaded workqueue just to gain concurrency. Unlike a dedicated per-cpu workqueue created with create_singlethread_workqueue(), system_wq allows multiple work items to overlap executions even on the same CPU; however, a per-cpu workqueue doesn't have any CPU locality or global ordering guarantee unless the target CPU is explicitly specified and thus the increase of local concurrency shouldn't make any difference. Work item has been flushed in rtsx_pci_sdmmc_drv_remove() to ensure that there are no pending tasks while disconnecting the driver. Signed-off-by: Bhaktipriya Shridhar <bhaktipriya96@gmail.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requestsUlf Hansson2016-07-291-1/+1
| | | | | | | | | | | | Cc: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Mauro Santos <registo.mailling@gmail.com>
| * mmc: rtsx_pci: Use the provided busy timeout from the mmc coreUlf Hansson2016-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The rtsx_pci driver is using a fixed 3s timeout for R1B responses, which in some cases isn't suffient. For example, erase/discard requests may require longer timeouts. Instead of always using a fixed timeout, let's use the per request calculated busy timeout from the mmc core. Cc: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Mauro Santos <registo.mailling@gmail.com>
| * mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPSUlf Hansson2016-07-299-9/+8
| | | | | | | | | | | | | | Due to previous changes this define has no longer a purpose. Instead move the sdhci-pltfm drivers over to use the exported struct sdhci_pltfm_pmops. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-pltfm: Convert to use the SET_SYSTEM_SLEEP_PM_OPSUlf Hansson2016-07-292-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | Move the system PM callbacks within #ifdef CONFIG_PM_SLEEP as to avoid them being build when not used. This also allows us to use the SET_SYSTEM_SLEEP_PM_OPS macro which simplifies the code. Within this context it also makes sense to move the declaration of the struct sdhci_pltfm_pmops, outside the #ifdef CONFIG_PM as the SET_SYSTEM_SLEEP_PM_OPS deals with this. This further simplifies the code. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-pltfm: Make sdhci_pltfm_suspend|resume() staticUlf Hansson2016-07-292-6/+2
| | | | | | | | | | | | There are no users left of these exported APIs, so let's make them static. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: Use common sdhci_suspend|resume_host()Ulf Hansson2016-07-291-2/+4
| | | | | | | | | | | | | | | | To prepare to make the sdhci_pltfm_suspend|resume() static functions, move sdhci-esdhc-imx over to use the sdhci_suspend|resume_host(). Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
| * mmc: sdhci-esdhc-imx: Assign system PM ops within #ifdef CONFIG_PM_SLEEPUlf Hansson2016-07-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The system PM callbacks isn't used unless CONFIG_PM_SLEEP is set, thus it triggers a compiler warning about unused functions. Avoid this by changing from CONFIG_PM to CONFIG_PM_SLEEP. Reported-by: Arnd Bergmann <arnd@arndb.de> Fixes: b70d0b3b5b29 ("mmc: sdhci-esdhc-imx: add esdhc specific suspend resume callback") Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
| * mmc: sdhci-sirf: Remove non needed #ifdef CONFIG_PM* for dev_pm_opsUlf Hansson2016-07-271-3/+1
| | | | | | | | | | | | | | | | | | The SIMPLE_DEV_PM_OPS macro deals with the CONFIG_PM options when assigning the PM callbacks, thus it's not needed to control this when using the macro. By removing the non needed #ifdef, the code becomes a bit cleaner. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-s3c: Remove non needed #ifdef CONFIG_PM for dev_pm_opsUlf Hansson2016-07-271-8/+1
| | | | | | | | | | | | | | | | | | As the SET_SYSTEM_SLEEP_PM_OPS and the SET_RUNTIME_PM_OPS macro deals with the CONFIG_PM options when assigning the callbacks, it becomes redundant to control this when declaring the struct dev_pm_ops. Instead let's always declare it as it simplifies the code. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-pxav3: Remove non needed #ifdef CONFIG_PM for dev_pm_opsUlf Hansson2016-07-271-8/+1
| | | | | | | | | | | | | | | | | | As the SET_SYSTEM_SLEEP_PM_OPS and the SET_RUNTIME_PM_OPS macro deals with the CONFIG_PM options when assigning the callbacks, it becomes redundant to control this when declaring the struct dev_pm_ops. Instead let's always declare it as it simplifies the code. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-esdhc: Simplify code by using SIMPLE_DEV_PM_OPSUlf Hansson2016-07-271-10/+6
| | | | | | | | | | | | | | Let's use the SIMPLE_DEV_PM_OPS macro when declaring/assigning the system PM callbacks, as the code gets simplified. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-acpi: Simplify code by using SET_SYSTEM_SLEEP_PM_OPSUlf Hansson2016-07-271-7/+1
| | | | | | | | | | | | | | By using the SET_SYSTEM_SLEEP_PM_OPS when assigning the system PM callbacks, we can remove some #ifdefs so code becomes a bit cleaner. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-pci-core: Simplify code by using SET_SYSTEM_SLEEP_PM_OPSUlf Hansson2016-07-271-11/+5
| | | | | | | | | | | | | | Convert to define the system PM callbacks to be build for CONFIG_PM_SLEEP and use the SET_SYSTEM_SLEEP_PM_OPS. In this way the code becomes cleaner. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: Change the max discard sectors and erase response when HW busy detectBaolin Wang2016-07-251-10/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When mmc host HW supports busy signalling (using R1B as response), don't use the host->max_busy_timeout as the limitation when deciding the max discard sectors, which we inform the generic BLOCK layer about. Instead, let's use at least one preferred erase size as the max discard sectors. In cases when the host controller supports HW busy signalling and the timeout for the erase operation doesn't exceed the max_busy_timeout, we keep the R1B response, otherwise we prevent the host from doing HW busy detection by converting to a R1 response. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changesDouglas Anderson2016-07-251-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac0d5f245e1 ("mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes"), resolving conflicts with other patches that have come after. It appears that on some boards / with some eMMC devices that the patch is causing problems. Presumably turning the phy off and on again at the wrong time while initially setting up the card is confusing the card, the host, or the PHY. We have lots of power cycles while initially setting up the card because the main sdhci driver often turns off the clock by clearing SDHCI_CLOCK_CARD_EN and then calls host->ops->set_clock() to set the clock again. With all of those, we ended up with lots of power cycles. Presumably the arguments made in the original patch still hold. That is, whenever the card clock is turned off and on again (or changed) we really should wait for the DLL to lock again. However, perhaps it's really not that critical for the lower speeds. It's possible that the right answer here is: * Whenever set_clock() is called we should double-check that the DLL is locked. * Whenever set_clock() is called and we're actually changing clocks we should do a power cycle around that. * When we're doing a power cycle just because the clock changed, we probably shouldn't do quite as many things (maybe don't need to recalibarate, etc). Unfortunately the interaction between SDHCI and the PHY is extremely limited because of the limited PHY API. The PHY does have a reference to the card clock and could theoretically register for notifications, except that our clock is query only (it uses CLK_GET_RATE_NOCACHE) and so can't really be notified about updates. I believe we would need a major redesign of clock handling in SDHCI core to do better than that, or we would need to make our one fake notifications. :( Let's hope that we can eventually get more information from Arasan on how all this should be handled before doing tons more work. Until then, let's get back to a known working state. Note that the rest of the patches in the 150 MHz series should still work fine even without this one. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-msm: Add support for UHS cardsGeorgi Djakov2016-07-251-0/+66
| | | | | | | | | | | | | | | | | | | | Enabling support for ultra high speed mode cards requires some voltage switching and interaction with the PMIC via a special power IRQ. Add support for this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-msm: Add set_uhs_signaling() implementationRitesh Harjani2016-07-251-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow UHS mode to work properly, we need to implement a Qualcomm specific set_uhs_signaling() callback function. This function differs from the sdhci_set_uhs_signaling() in that we need check the clock rate and enable UHS timing only if the frequency is above 100MHz. This patch resolves the mmc_select_hs200 timeouts noticed after merging commit a5c1f3e55c99 ("mmc: mmc: do not use CMD13 to get status after speed mode switch") mmc0: mmc_select_hs200 failed, error -110 mmc0: error -110 whilst initialising MMC card mmc0: Reset 0x1 never completed. sdhci: =========== REGISTER DUMP (mmc0)=========== sdhci: Sys addr: 0x00000000 | Version: 0x00002e02 sdhci: Blk size: 0x00004000 | Blk cnt: 0x00000000 sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 sdhci: Present: 0x01f80000 | Host ctl: 0x00000000 sdhci: Power: 0x00000000 | Blk gap: 0x00000000 sdhci: Wake-up: 0x00000000 | Clock: 0x00000003 sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000 sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 sdhci: Caps: 0x322dc8b2 | Caps_1: 0x00008007 sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 sdhci: Host ctl2: 0x00000000 sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 sdhci: =========================================== Fixes: a5c1f3e55c99 ("mmc: mmc: do not use CMD13 to get status after...") Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-msm: Do not reset the controller if no card in the slotGeorgi Djakov2016-07-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The controller does not clear the "reset bit" when it is reset without a card in the slot. Because of this, the following error message is seen while booting with no plugged SD card. mmc1: Reset 0x1 never completed. Add the SDHCI_QUIRK_NO_CARD_NO_RESET quirk to avoid this. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: tegra: Only advertise UHS modes if IO regulator is presentJon Hunter2016-07-251-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support UHS modes for Tegra an external regulator must be present to adjust the IO voltage accordingly. Even if the regulator is not present but the host supports the UHS modes and the device supports the UHS modes, then we will attempt to switch to a high-speed mode. Without an external regulator, Tegra will fail to switch to the high-speed mode. It has been found that with some SD cards, that once it has been switch to operate at a high-speed mode, all subsequent commands issues to the card will fail and so it will not be possible to switch back to a non high-speed mode and so the SD card initialisation will fail. The SDHCI core does not require that the host have an external regulator when switching to UHS modes and therefore, the Tegra SDHCI host controller should only advertise the UHS modes as being supported if the regulator for the IO voltage is present. Fortunately, Tegra has a vendor specific register which can be used to control which modes are advertised via the SDHCI_CAPABILITIES register. Hence, if there is no IO voltage regulator available for the Tegra SDHCI host, then don't advertise the UHS modes. Note that if the regulator is not available, we also don't advertise that the SDHCI is compatible with v3.0 of the SDHCI specification because this will read the SDHCI_CAPABILITIES_1 register which will enable other UHS modes. This fixes commit 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") which enables UHS mode without checking if the board can support them. Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Request regulators before reading capabilitiesJon Hunter2016-07-251-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The capabilities of the SDHCI host controller are read early during the SDHCI host initialisation in sdhci_setup_host() and before any regulators for the host have been requested. This means that if the host supports some high-speed modes (according to its capabilities register), but the board cannot because the appropriate voltage regulator is not available, then the host cannot easily override the capabilities that are supported. To allow a SDHCI host controller to determine if it can support UHS high speed modes via the presence of the MMC regulators, request the regulators before reading the capabilities of the host controller. This will allow the SDHCI host to use the 'reset' callback to take the appropriate action (set flags, configure registers, etc) before the capabilities register(s) are read. Please note that some SDHCI hosts, such as the Tegra SDHCI host, has the ability to mask bits in the capabilities register to prevent certain capabilities from being advertised. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * sdhci-pci: Use MRFLD as abbreviation of MerrifieldAndy Shevchenko2016-07-252-10/+10
| | | | | | | | | | | | | | | | | | Everywhere else in the code MRFLD abbreviation is used for Intel Merrifield. Do the same for sdhci-pci. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: clear tuning bits during driver probeDong Aisheng2016-07-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning bits like FBCLK_SEL, SMP_CLK_SEL and DLY_CELL which affects timing may have already been set by ROM if booting from SD3.0 mode like SDR104. Let's clear it first during driver probe before doing the new card enumeration to avoid working on the wrong timing. Note that tuning bits are dynamical settings which may need to be kept during MMC_PM_KEEP_POWER suspend, so we did not put them into hwinit function. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhci-imx: re-initialize hw state after resumeDong Aisheng2016-07-251-5/+2
| | | | | | | | | | | | | | | | | | | | sdhci_esdhc_imx_hwinit() includes all basic hw intialization. Calling it after resume to re-initialize hw in case its state is already lost in low power mode. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: move tuning static configuration into hwinit functionDong Aisheng2016-07-251-18/+18
| | | | | | | | | | | | | | | | | | | | Move tuning static configuration into basic hwinit function. Tuning configuration may also be lost in low power mode, so need restore in hwinit(). Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: factor out hw related initialization into functionDong Aisheng2016-07-251-32/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Move all hw related static initializations into a separate function which helps concentrate the hw related initialization code. And that function could also be called by other places later as a basic hw state restore. e.g. suspend/resume where the hw state is possible to lost due to low power mode. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: fix strobe DLL lock wrong clock issueDong Aisheng2016-07-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | When enable DDR, the clock factor definition is changed. e.g. original 200Mhz will become 100Mhz once MIX_CTRL_DDREN bit is set So we need to update the clock setting then the strobe dll can lock the correct clock rate. Additionally we also need disable the clock before locking strobe dll. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: enable hw auto retuning for MAN_TUNINGDong Aisheng2016-07-251-3/+8
| | | | | | | | | | | | | | | | | | | | Indicating hw auto retuning support for mx6qdl in the fake caps_1 register and enable auto retuning in post_tuning process after tuning completes. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: enable hw auto retuning for STD_TUNINGDong Aisheng2016-07-251-0/+3
| | | | | | | | | | | | | | | | | | Enable HW auto retuning when set SDHCI_CTRL_EXEC_TUNING and clear it when clear SDHCI_CTRL_TUNED_CLK. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: add standard hw auto retuning supportDong Aisheng2016-07-252-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If HW supports SDHCI_TUNING_MODE_3 which is auto retuning, we won't retune during runtime suspend and resume, instead we use Re-tuning Request signaled via SDHCI_INT_RETUNE interrupt to do retuning and hw auto retuning during data transfer to guarantee the signal sample window correction. This can avoid a mass of repeatedly retuning during small file system data access and improve the performance. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: support setting tuning start pointDong Aisheng2016-07-251-3/+11
| | | | | | | | | | | | | | | | | | | | The delay cells of some SoCs may have less delay per one cell, for such SoCs, user could set the start delay cell point to bypass the first a few meaningless tuning commands. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhci-imx: disable DLL delay line settings explicitlyDong Aisheng2016-07-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Disable DLL delay line settings explicitly during driver initialization in case ROM/uBoot had set an invalid delay. e.g. MX6DL ROM has set the default delay line(DLLCTRL) to 0x1000021, the uSDHC clock timing will become marginal when works on DDR mode due to default delay and will possibly see CRC errors in case the board is not perfectly designed on the eMMC chip layout. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: restore watermark level setting after resumeDong Aisheng2016-07-251-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we config the watermark_level register only in probe. This will cause the mmc write operation timeout issue after system resume back in LPSR mode. Because in LPSR mode, after system resume back, the watermark_level register(0x44) changes to 0x08000880, which set the write watermark level as 0, and set the read watermark level as 128. This value is incorrect. This patch restores the setting of watermark level register after system resume back. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: add esdhc specific suspend resume callbackDong Aisheng2016-07-251-1/+11
| | | | | | | | | | | | | | | | | | It will be used for platform specific suspend/resume state save/restore work for some low power mode like Mega/Fast or LPSR mode. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-esdhc-imx: remove SDHCI_QUIRK_BROKEN_TIMEOUT_VALDong Aisheng2016-07-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | The driver has already implemented the private .set_timeout() callback for common SDHCI code to do correct timeout value setting, it does not need call sdhci_calc_timeout(), so this quirk actually is not working. Remove it now. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: using common mmc_regulator_set_vqmmc()Dong Aisheng2016-07-251-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to use the more robust common mmc_regulator_set_vqmmc() function in MMC core which set the target voltage as close as possible to target voltage. We did not re-factor the whole sdhci_start_signal_voltage_switch() cause we want to keep the original signal switch order between host and card to avoid potential break. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-pci: Convert to use managed functions pcim_* and devm_*Andy Shevchenko2016-07-251-31/+11
| | | | | | | | | | | | | | | | | | This makes the error handling much more simpler than open-coding everything and in addition makes the probe function smaller an tidier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: core: Extend sysfs with DSR registerBojan Prtvar2016-07-252-0/+34
| | | | | | | | | | | | | | | | Export DSR register through sysfs same as we did for the CID, CSD and OCR registers. Signed-off-by: Bojan Prtvar <prtvar.b@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: rockchip: unset the MMC_CAP_ERASE flagJaehoon Chung2016-07-251-4/+4
| | | | | | | | | | | | | | | | | | In dw_mmc.c, it's enabled by default. It doesn't need to set MMC_CAP_ERASE in rockchip anymore. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: set to MMC_CAP_ERASE by defaultJaehoon Chung2016-07-251-0/+6
| | | | | | | | | | | | | | | | | | This flag needs to use the trim/discard/erase commands. dwmmc controller enables this flag by default. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: core: expose MMC_CAP2_NO_* to dtShawn Lin2016-07-251-0/+6
| | | | | | | | | | | | | | | | | | The reason for why we expose these to dt is that some of the controller is unable to send special cmd type due to the hw limitation. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: core: Extend sysfs with OCR registerBojan Prtvar2016-07-252-0/+4
| | | | | | | | | | | | | | | | | | Registers CID and CSD are already exported through sysfs so let's make this interface complete by adding missing OCR register. Signed-off-by: Bojan Prtvar <prtvar.b@gmail.com> Reviewed-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-iproc: Use defines instead of magic numbersStefan Wahren2016-07-251-2/+11
| | | | | | | | | | | | | | | | | | | | | | The capabilities in iproc platform data are magic numbers. So replace them with the proper capability defines to make it readable. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 19:47:06 +0000