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| * mtd: rawnand: denali: use bool type instead of int where appropriateMasahiro Yamada2019-04-182-13/+14
| | | | | | | | | | | | | | | | | | | | Use 'bool' type for the following boolean parameters. - write (write or read?) - dma_avail (DMA engine available or not?) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: switch over to ->exec_op() from legacy hooksMasahiro Yamada2019-04-181-108/+143
| | | | | | | | | | | | | | Implement ->exec_op(), and remove the deprecated hooks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: remove unneeded casts in denali_{read, write}_pioMasahiro Yamada2019-04-181-7/+5
| | | | | | | | | | | | | | | | | | Since (u32 *) can accept an opaque pointer, the explicit casting from (void *) to (u32 *) is redundant. Change the function argument type to remove the casts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: refactor raw page accessorsMasahiro Yamada2019-04-182-265/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Denali IP adopts the syndrome page layout (payload and ECC are interleaved). The *_page_raw() and *_oob() callbacks are complicated because they must hide the underlying layout used by the hardware, and always return contiguous in-band and out-of-band data. The Denali IP cannot reuse nand_{read,write}_page_raw_syndrome() in nand_base.c because its hardware ECC engine skips some of first bytes in OOB. That is why this driver implements specially-crafted *_page_raw() and *_oob() hooks. Currently, similar code is duplicated to reorganize the data layout. For example, denali_read_page_raw() and denali_write_page_raw() look almost the same. The complexity is partly due to the DMA transfer used for better performance of *_page_raw() accessors. On second thought, we do not need to care about their performance because MTD_OPS_RAW is rarely used. Let's focus on code cleanups rather than the performance. This commit removes the internal buffer for DMA, and factors out as much code as possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: use more nand_chip pointers for internal functionsMasahiro Yamada2019-04-181-27/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | With the recent refactoring, the NAND driver hooks now take a pointer to nand_chip. Add to_denali() in order to convert (struct nand_chip *) to (struct denali_nand_info *) directly. It is more useful than the current mtd_to_denali(). I changed some helper functions to take (struct nand_chip *). This will avoid pointer conversion back and forth, and ease further development. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: atmel: Fix spelling mistake in error messageMiquel Raynal2019-04-181-1/+1
| | | | | | | | | | | | | | | | | | Wrong copy/paste from the previous block, the error message should refer to #size-cells instead of #address-cells. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * mtd: rawnand: fsl_elbc: Make SW ECC workMarek Behún2019-04-181-18/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Move the code that choses ECC into _attach_chip, which is executed only after the chip->ecc.* properties were loaded from device-tree. This way we know which ECC method was chosen by the device-tree and can set methods appropriately. The chip->ecc.*page methods should be set to fsl_elbc_*page only in HW ECC mode. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: fsl_elbc: Implement RNDOUT commandMarek Behún2019-04-181-0/+9
| | | | | | | | | | | | | | This is needed for SW ECC. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: fsl_elbc: Cosmetic moveMarek Behún2019-04-181-73/+73
| | | | | | | | | | | | | | | | Move the fsl_elbc_attach_chip function after the definitions of fsl_elbc_read_page and friends in preparation for the next patch. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: fix build dependencyAnders Roxell2019-04-182-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling CONFIG_MTD_NAND_ECC_SW_BCH as a module, the MTD_NAND_ECC_SW_BCH depends on MTD_NAND, but the module controlled by MTD_NAND links against the module controlled by MTD_NAND_ECC_SW_BCH. This leads to the following link failure. aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_cleanup': ../drivers/mtd/nand/raw/nand_base.c:5886: undefined reference to `nand_bch_free' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5886:(.text+0x9928): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_free' aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_set_ecc_soft_ops': ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093:(.text+0xe914): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094:(.text+0xe934): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148: undefined reference to `nand_bch_init' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148:(.text+0xebbc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_init' Rework CONFIG_MTD_NAND_ECC_SW_BCH from tristate to bool, and then link the nand_bch.o file into nand.ko if its enabled. Fixes: 51ef1d0b2095 ("mtd: nand: Clarify Kconfig entry for software BCH ECC algorithm") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: nand: Remove useless line in KconfigMiquel Raynal2019-04-181-1/+0
| | | | | | | | | | | | | | Prepare changes that will lay in this file to better express what is NAND related and what is not in menuconfig. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Clarify Kconfig entry MTD_NANDMiquel Raynal2019-04-182-4/+4
| | | | | | | | | | | | | | | | MTD_NAND is large and encloses much more than what the symbol is actually used for: raw NAND. Clarify the symbol by naming it MTD_RAW_NAND instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Change Kconfig titles and re-order a bit the listMiquel Raynal2019-04-182-177/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This list is a mess, while some items should probably not be in the raw/ sub-directory, others are definitely at the right place but not with the right description. Write uniform titles and group IPs by vendor. NAND controllers will appear under the list named "Raw/parallel NAND flash controllers" while the other drivers will appear under "Misc". Software ECC engines will later be moved out of the raw/ directory. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: nand: Clarify Kconfig entry for software Hamming ECC entriesMiquel Raynal2019-04-183-8/+7
| | | | | | | | | | | | | | | | | | | | The software Hamming ECC correction implementation is referred as MTD_NAND_ECC which is too generic. Rename it MTD_NAND_ECC_SW_HAMMING. Also rename MTD_NAND_ECC_SMC which is an SMC quirk in the Hamming implementation as MTD_NAND_ECC_SW_HAMMING_SMC. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: nand: Clarify Kconfig entry for software BCH ECC algorithmMiquel Raynal2019-04-184-11/+6
| | | | | | | | | | | | | | There is no point in having two distinct entries, merge them and rename the symbol for more clarity: MTD_NAND_ECC_SW_BCH Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Get rid of chip->ecc_{strength,step}_dsBoris Brezillon2019-04-0814-77/+81
| | | | | | | | | | | | | | | | | | | | | | | | nand_device embeds a nand_ecc_req object which contains the minimum strength and step-size required by the NAND device. Drop the chip->ecc_{strength,step}_ds fields and use chip->base.eccreq.{strength,step_size} instead. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Get rid of chip->numchipsBoris Brezillon2019-04-088-25/+17
| | | | | | | | | | | | | | | | The same information is provided by nanddev_ntargets(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Get rid of chip->chipsizeBoris Brezillon2019-04-0812-34/+38
| | | | | | | | | | | | | | | | | | The target size can now be returned by nanddev_get_targetsize(). Get rid of the chip->chipsize field and use this helper instead. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Get rid of chip->bits_per_cellBoris Brezillon2019-04-085-8/+2
| | | | | | | | | | | | | | | | | | | | Now that we inherit from nand_device, we can use nand_device->memorg.bits_per_cell instead of having our own field at the nand_chip level. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Use nanddev_mtd_max_bad_blocks()Boris Brezillon2019-04-082-40/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | nanddev_mtd_max_bad_blocks() is implemented by the generic NAND layer and is already doing what we need. Reuse this function instead of having our own implementation. While at it, get rid of the ->max_bb_per_die and ->blocks_per_die fields which are now unused. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Move all page cache related fields to a sub-structBoris Brezillon2019-04-081-14/+14
| | | | | | | | | | | | | | | | | | | | Looking at the field names it's hard to tell what ->data_buf, ->pagebuf and ->pagebuf_bitflips are for. Clarify that by moving those fields in a sub-struct named pagecache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Provide a helper to get chip->data_bufBoris Brezillon2019-04-087-49/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | We plan to move cache related fields to a pagecache struct in nand_chip but some drivers access ->pagebuf directly to invalidate the cache before they start using ->data_buf. Let's provide an helper that returns a pointer to ->data_buf after invalidating the cache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Initialize the nand_device objectBoris Brezillon2019-04-082-7/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to use some of the nanddev_xxx() helpers, we need to initialize the nand_device object embedded in nand_chip using nanddev_init(). This requires implementing nand_ops. We also drop useless mtd->xxx initialization when they're already taken case of by nanddev_init(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: Fill memorg during detectionBoris Brezillon2019-04-0811-44/+175
| | | | | | | | | | | | | | | | | | | | If we want to use the generic NAND layer, we need to have the memorg struct appropriately filled. Patch the detection code to fill this struct. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: spinand: Implement mtd->_max_bad_blocksBoris Brezillon2019-04-081-0/+1
| | | | | | | | | | | | | | | | We just have to use nanddev_mtd_max_bad_blocks(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: nand: Add max_bad_eraseblocks_per_lun info to memorgBoris Brezillon2019-04-086-15/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND datasheets usually give the maximum number of bad blocks per LUN and this number can be used to help upper layers decide how much blocks they should reserve for bad block handling. Add a max_bad_eraseblocks_per_lun to the nand_memory_organization struct and update the NAND_MEMORG() macro (and its users) accordingly. We also provide a default mtd->_max_bad_blocks() implementation. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * mtd: rawnand: meson: set oob layout opsLiang Yang2019-04-081-0/+2
| | | | | | | | | | | | | | | | | | | | Specify the oob layout operation to avoid no oob scheme defined for some nand flash. Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Liang Yang <liang.yang@amlogic.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: vf610: Avoid a potential NULL pointer dereferenceAditya Pakki2019-04-081-0/+3
| | | | | | | | | | | | | | | | | | of_match_device can return NULL if there is no matching device. Avoid a potential NULL pointer dereference by checking for the return value and passing the error upstream. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Move BBTs out of ECC areaPaul Cercueil2019-04-081-0/+7
| | | | | | | | | | | | | | | | The generic layout for BBT markers will most likely overlap with our ECC bytes in the OOB, so move the BBT markers outside the OOB area. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Add ooblayout for the Qi Ben NanonotePaul Cercueil2019-04-081-1/+40
| | | | | | | | | | | | | | | | The Ben Nanonote from Qi Hardware expects a specific OOB layout on its NAND. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Add support for the JZ4725BPaul Cercueil2019-04-084-1/+353
| | | | | | | | | | | | | | | | | | | | | | The boot ROM of the JZ4725B SoC expects a specific OOB layout on the NAND, so we use it unconditionally in the ingenic-nand driver. Also add the jz4725b-bch driver to support the JZ4725B-specific BCH hardware. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Add support for the JZ4740Paul Cercueil2019-04-084-11/+245
| | | | | | | | | | | | | | | | | | Add support for probing the ingenic-nand driver on the JZ4740 SoC from Ingenic, and the jz4740-ecc driver to support the JZ4740-specific ECC hardware. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Make use of ecc-engine propertyPaul Cercueil2019-04-081-3/+10
| | | | | | | | | | | | | | | | Use the 'ecc-engine' standard property instead of the custom 'ingenic,bch-controller' custom property, which is now deprecated. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Separate top-level and SoC specific codePaul Cercueil2019-04-087-203/+310
| | | | | | | | | | | | | | | | | | | | The ingenic-nand driver uses an API provided by the jz4780-bch driver. This makes it difficult to support other SoCs in the jz4780-bch driver. To work around this, we separate the API functions from the SoC-specific code, so that these API functions are SoC-agnostic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Rename jz4780_bch_init to jz4780_bch_resetPaul Cercueil2019-03-211-4/+5
| | | | | | | | | | | | | | | | | | The jz4780_bch_init name was confusing, as it suggested that its content should be executed once at init time, whereas what the function really does is reset the hardware for a new ECC operation. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Rename jz4780_nand driver to ingenic_nandPaul Cercueil2019-03-212-74/+74
| | | | | | | | | | | | | | | | | | The jz4780_nand driver will be modified to handle all the Ingenic JZ47xx SoCs that the upstream Linux kernel supports (JZ4740, JZ4725B, JZ4770, JZ4780), so it makes sense to rename it. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: ingenic: Use SPDX license notifiersPaul Cercueil2019-03-213-12/+3
| | | | | | | | | | | | | | | | Use SPDX license notifiers instead of GPLv2 license text in the headers. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Move drivers for Ingenic SoCs to subfolderPaul Cercueil2019-03-218-15/+17
| | | | | | | | | | | | | | | | Before adding support for more SoCs and seeing the number of files for these drivers grow, we move them to their own subfolder to keep it tidy. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: meson: fix a potential memory leak in meson_nfc_read_bufMartin Blumenstingl2019-03-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | meson_nfc_dma_buffer_setup() is called with the "info" buffer which is allocated a few lines before using kzalloc(). If meson_nfc_dma_buffer_setup() fails we need to free the allocated "info" buffer instead of only freeing it upon success. Fixes: 8fae856c53500a ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: meson: add missing ENOMEM check in meson_nfc_read_buf()Martin Blumenstingl2019-03-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | kzalloc() can return NULL if memory could not be allocated. Check the return value of the kzalloc() call in meson_nfc_read_buf() to make it consistent with other memory allocations within the meson_nand driver. Fixes: 8fae856c53500a ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: atmel: switch to SPDX license identifiersTudor Ambarus2019-03-213-13/+3
| | | | | | | | | | | | | | | | Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: atmel: add sam9x60 nand controller supportTudor Ambarus2019-03-211-12/+74
| | | | | | | | | | | | | | | | | | | | | | The sam9x60 board defines the CCFG_EBICSA register under SFR, and not as a MATRIX register, as previous boards do. NAND Flash I/Os are connected to D16–D23, thus SFR_CCFG_EBICSA.NFD0_ON_D16 is set to 1. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: atmel: add generic name for EBICSA regmapTudor Ambarus2019-03-211-11/+17
| | | | | | | | | | | | | | | | | | | | The sam9x60 board defines the CCFG_EBICSA register under SFR, and not as a MATRIX register, as previous boards do. Add a more generic name for the EBICSA regmap, as a prerequisite for sam9x60 nand controller support. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Mark expected switch fall-throughsGustavo A. R. Silva2019-03-214-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warning: drivers/mtd/nand/raw/diskonchip.c: In function ‘doc_probe’: ./include/linux/printk.h:303:2: warning: this statement may fall through [-Wimplicit-fallthrough=] printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/diskonchip.c:1479:4: note: in expansion of macro ‘pr_err’ pr_err("DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); ^~~~~~ drivers/mtd/nand/raw/diskonchip.c:1480:3: note: here default: ^~~~~~~ drivers/mtd/nand/raw/nandsim.c: In function ‘ns_init_module’: drivers/mtd/nand/raw/nandsim.c:2254:22: warning: this statement may fall through [-Wimplicit-fallthrough=] chip->bbt_options |= NAND_BBT_NO_OOB; drivers/mtd/nand/raw/nandsim.c:2255:2: note: here case 1: ^~~~ drivers/mtd/nand/raw/nuc900_nand.c: In function ‘nuc900_nand_command_lp’: ./arch/x86/include/asm/io.h:91:22: warning: this statement may fall through [-Wimplicit-fallthrough=] #define __raw_writel __writel drivers/mtd/nand/raw/nuc900_nand.c:52:2: note: in expansion of macro ‘__raw_writel’ __raw_writel((val), (dev)->reg + REG_SMCMD) ^~~~~~~~~~~~ drivers/mtd/nand/raw/nuc900_nand.c:196:3: note: in expansion of macro ‘write_cmd_reg’ write_cmd_reg(nand, NAND_CMD_READSTART); ^~~~~~~~~~~~~ drivers/mtd/nand/raw/nuc900_nand.c:197:2: note: here default: ^~~~~~~ drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_restore’: drivers/mtd/nand/raw/omap_elm.c:512:4: warning: this statement may fall through [-Wimplicit-fallthrough=] elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ regs->elm_syndrome_fragment_4[i]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:514:3: note: here case BCH8_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c:517:4: warning: this statement may fall through [-Wimplicit-fallthrough=] elm_write_reg(info, ELM_SYNDROME_FRAGMENT_2 + offset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ regs->elm_syndrome_fragment_2[i]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:519:3: note: here case BCH4_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_save’: drivers/mtd/nand/raw/omap_elm.c:466:37: warning: this statement may fall through [-Wimplicit-fallthrough=] regs->elm_syndrome_fragment_4[i] = elm_read_reg(info, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ELM_SYNDROME_FRAGMENT_4 + offset); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:468:3: note: here case BCH8_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c:471:37: warning: this statement may fall through [-Wimplicit-fallthrough=] regs->elm_syndrome_fragment_2[i] = elm_read_reg(info, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ELM_SYNDROME_FRAGMENT_2 + offset); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:473:3: note: here case BCH4_ECC: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: gpmi: Introduce GPMI_IS_MXS() macroFabio Estevam2019-03-213-5/+4
| | | | | | | | | | | | | | | | Introduce a GPMI_IS_MXS() macro to take into account the cases when mx23 or mx28 are used, which helps readability. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: spinand: Use the spi-mem dirmap APIBoris Brezillon2019-03-211-84/+84
| | | | | | | | | | | | | | | | | | | | Make use of the spi-mem direct mapping API to let advanced controllers optimize read/write operations when they support direct mapping. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Stefan Roese <sr@denx.de>
* | Merge tag 'arm64-mmiowb' of ↵Linus Torvalds2019-05-062-3/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull mmiowb removal from Will Deacon: "Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb()) Remove mmiowb() from the kernel memory barrier API and instead, for architectures that need it, hide the barrier inside spin_unlock() when MMIO has been performed inside the critical section. The only relatively recent changes have been addressing review comments on the documentation, which is in a much better shape thanks to the efforts of Ben and Ingo. I was initially planning to split this into two pull requests so that you could run the coccinelle script yourself, however it's been plain sailing in linux-next so I've just included the whole lot here to keep things simple" * tag 'arm64-mmiowb' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (23 commits) docs/memory-barriers.txt: Update I/O section to be clearer about CPU vs thread docs/memory-barriers.txt: Fix style, spacing and grammar in I/O section arch: Remove dummy mmiowb() definitions from arch code net/ethernet/silan/sc92031: Remove stale comment about mmiowb() i40iw: Redefine i40iw_mmiowb() to do nothing scsi/qla1280: Remove stale comment about mmiowb() drivers: Remove explicit invocations of mmiowb() drivers: Remove useless trailing comments from mmiowb() invocations Documentation: Kill all references to mmiowb() riscv/mmiowb: Hook up mmwiob() implementation to asm-generic code powerpc/mmiowb: Hook up mmwiob() implementation to asm-generic code ia64/mmiowb: Add unconditional mmiowb() to arch_spin_unlock() mips/mmiowb: Add unconditional mmiowb() to arch_spin_unlock() sh/mmiowb: Add unconditional mmiowb() to arch_spin_unlock() m68k/io: Remove useless definition of mmiowb() nds32/io: Remove useless definition of mmiowb() x86/io: Remove useless definition of mmiowb() arm64/io: Remove useless definition of mmiowb() ARM/io: Remove useless definition of mmiowb() mmiowb: Hook up mmiowb helpers to spinlocks and generic I/O accessors ...
| * | drivers: Remove explicit invocations of mmiowb()Will Deacon2019-04-082-3/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* / mtd: rawnand: marvell: Clean the controller state before each operationMiquel Raynal2019-04-251-6/+6
|/ | | | | | | | | | | | | | | | Since the migration of the driver to stop using the legacy ->select_chip() hook, there is nothing deselecting the target anymore, thus the selection is not forced at the next access. Ensure the ND_RUN bit and the interrupts are always in a clean state. Cc: Daniel Mack <daniel@zonque.org> Cc: stable@vger.kernel.org Fixes: b25251414f6e00 ("mtd: rawnand: marvell: Stop implementing ->select_chip()") Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at>
* Merge tag 'mtd/for-5.1' of git://git.infradead.org/linux-mtdLinus Torvalds2019-03-0422-553/+4243
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Boris Brezillon: "Core MTD changes: - Use struct_size() where appropriate - mtd_{read,write}() as wrappers around mtd_{read,write}_oob() - Fix misuse of PTR_ERR() in docg3 - Coding style improvements in mtdcore.c SPI NOR changes: Core changes: - Add support of octal mode I/O transfer - Add a bunch of SPI NOR entries to the flash_info table SPI NOR controller driver changes: - cadence-quadspi: * Add support for Octal SPI controller * write upto 8-bytes data in STIG mode - mtk-quadspi: * rename config to a common one * add SNOR_HWCAPS_READ to spi_nor_hwcaps mask - Add Tudor as SPI-NOR co-maintainer NAND changes: NAND core changes: - Fourth batch of fixes/cleanup to the raw NAND core impacting various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2). - Check the return code of nand_reset() and nand_readid_op(). - Remove ->legacy.erase and single_erase(). - Simplify the locking. - Several implicit fall through annotations. Raw NAND controllers drivers changes: - Fix various possible object reference leaks (MTK, JZ4780, Atmel) - ST: * Add support for STM32 FMC2 NAND flash controller - Meson: * Add support for Amlogic NAND flash controller - Denali: * Several cleanup patches - Sunxi: * Several cleanup patches - FSMC: * Disable NAND on remove() * Reset NAND timings on resume() SPI-NAND drivers changes: - Toshiba: * Add support for all Toshiba products. - Macronix: * Fix ECC status read. - Gigadevice: * Add support for GD5F1GQ4UExxG" * tag 'mtd/for-5.1' of git://git.infradead.org/linux-mtd: (64 commits) mtd: spi-nor: Fix wrong abbreviation HWCPAS mtd: spi-nor: cadence-quadspi: fix spelling mistake: "Couldnt't" -> "Couldn't" mtd: spi-nor: Add support for en25qh64 mtd: spi-nor: Add support for MX25V8035F mtd: spi-nor: Add support for EN25Q80A mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1 mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode mtd: spi-nor: Add support for mx25u3235f mtd: rawnand: denali_dt: remove single anonymous clock support mtd: rawnand: mtk: fix possible object reference leak mtd: rawnand: jz4780: fix possible object reference leak mtd: rawnand: atmel: fix possible object reference leak mtd: rawnand: fsmc: Disable NAND on remove() mtd: rawnand: fsmc: Reset NAND timings on resume() mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG mtd: rawnand: denali: remove unused dma_addr field from denali_nand_info mtd: rawnand: denali: remove unused function argument 'raw' mtd: rawnand: denali: remove unneeded denali_reset_irq() call ...
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