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* Merge tag 'mtd/for-6.4' of ↵Linus Torvalds2023-04-251-7/+29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "Core MTD changes: - dt-bindings: Drop unneeded quotes - mtdblock: Tolerate corrected bit-flips - Use of_property_read_bool() for boolean properties - Avoid magic values - Avoid printing error messages on probe deferrals - Prepare mtd_otp_nvmem_add() to handle -EPROBE_DEFER - Fix error path for nvmem provider - Fix nvmem error reporting - Provide unique name for nvmem device MTD device changes: - lpddr_cmds: Remove unused words variable - bcm63xxpart: Remove MODULE_LICENSE in non-modules SPI NOR core changes: - Introduce Read While Write support for flashes featuring several banks - Set the 4-Byte Address Mode method based on SFDP data - Allow post_sfdp hook to return errors - Parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: - macronix: Add support for mx25uw51245g with RWW - spansion: - Determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - Enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - Add support for s25hl02gt and s25hs02gt Raw NAND core changes: - Convert to platform remove callback returning void - Fix spelling mistake waifunc() -> waitfunc() Raw NAND controller driver changes: - imx: Remove unused is_imx51_nfc and imx53_nfc functions - omap2: Drop obsolete dependency on COMPILE_TEST - orion: Use devm_platform_ioremap_resource() - qcom: - Use of_property_present() for testing DT property presence - Use devm_platform_get_and_ioremap_resource() - stm32_fmc2: Depends on ARCH_STM32 instead of MACH_STM32MP157 - tmio: Remove reference to config MTD_NAND_TMIO in the parsers Raw NAND manufacturer driver changes: - hynix: Fix up bit 0 of sdr_timing_mode SPI-NAND changes: - Add support for ESMT F50x1G41LB" * tag 'mtd/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (55 commits) mtd: nand: Convert to platform remove callback returning void mtd: onenand: omap2: Drop obsolete dependency on COMPILE_TEST mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gt mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for multi-chip device support mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip device support mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device mtd: spi-nor: Extract volatile register offset from SCCR map mtd: spi-nor: Allow post_sfdp hook to return errors mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_size mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256T mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER flash mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash mtd: spi-nor: spansion: Determine current address mode mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode() mtd: spi-nor: core: Update flash's current address mode when changing address mode mtd: spi-nor: Stop exporting spi_nor_restore() mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP data mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr public mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode ...
| * mtd: spi-nor: Extract volatile register offset from SCCR mapTakahiro Kuwano2023-04-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In use of multi-chip devices, we need to access registers in each die for configuration and status check. The number of dice in the device and volatile register offsets for each die are essential to iterate register access ops. The volatile register offset for the first die resides in the 1st DWORD of SCCR map. Allocate the table and copy the offset value. The table may be allocated when the SCCR map for multi-chip is parsed. Since we cannot assume SCCR parse is always in ahead of SCCR multi-chip, we need to check if the table is already allocated or not. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/e2cc39ad6e0e02dd8288c4def9bb201a3f564425.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: Allow post_sfdp hook to return errorsTudor Ambarus2023-04-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Multi die flashes like s25hl02gt need to determine the page_size at run-time by querying a configuration register for each die. Since the number of dice is determined in an optional SFDP table, SCCR MC, the page size configuration must be done in the post_sfdp hook. Allow post_sfdp to return errors, as reading the configuration register might return errors. Link: https://lore.kernel.org/r/924ab710f128448ec62537cfbb377336e390043c.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER ↵Takahiro Kuwano2023-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. A new SNOR_F_ECC flag is introduced to determine if the part has on-die ECC and if it has, MTD_BIT_WRITEABLE is unset. In vendor specific driver, a common cypress_nor_ecc_init() helper is added. This helper takes care for ECC related initialization for SEMPER flash family by setting up params->writesize and SNOR_F_ECC. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode()Tudor Ambarus2023-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Make the method public, as it will be used as a last resort to enable 4byte address mode when we can't determine the address mode at runtime. Update the addr_nbytes and current address mode while exiting the 4byte address mode too, as it may be used in the future by manufacturer drivers. No functional change. spi_nor_restore didn't update the address mode nbytes, but updating them now doesn't harm as the method is called in the driver's remove and shutdown paths. Link: https://lore.kernel.org/r/20230331074606.3559258-10-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr publicTudor Ambarus2023-04-041-0/+1
| | | | | | | | | | | | | | | | | | This method can be retrieved at BFPT parsing time. The method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-6-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_modeTudor Ambarus2023-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | Rename method to spi_nor_set_4byte_addr_mode_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(31) and BIT(23). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: core: Update name and description of ↵Tudor Ambarus2023-04-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | micron_st_nor_set_4byte_addr_mode Rename method to spi_nor_set_4byte_addr_mode_wren_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: core: Move generic method to core - ↵Tudor Ambarus2023-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | micron_st_nor_set_4byte_addr_mode This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Move the method to core. Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: Add a RWW flagMiquel Raynal2023-03-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a new (no SFDP) flag for the feature that we are about to support: Read While Write. This means, if the chip has several banks and supports RWW, once a page of data to write has been transferred into the chip's internal SRAM, another read operation happening on a different bank can be performed during the tPROG delay. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-7-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: Reorder the preparation vs. locking stepsMiquel Raynal2023-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ->prepare()/->unprepare() hooks are now legacy, we no longer accept new drivers supporting them. The only remaining controllers using them acquires a per-chip mutex, which should not interfere with the rest of the operation done in the core. As a result, we should be safe to reorganize these helpers to first perform the preparation, before acquiring the core locks. This is necessary in order to be able to improve the locking mechanism in the core (coming next). No side effects are expected. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-4-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: Add a macro to define more banksMiquel Raynal2023-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Most of the chips on the market only feature a single bank. However, new chips may support more than a single bank, with the possibility to parallelize some operations. Let's introduce an INFOB() macro which also takes a n_bank parameter. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20230328154105.448540-3-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
| * mtd: spi-nor: Introduce the concept of bankMiquel Raynal2023-03-291-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI NOR chips are made of pages, which gathered in small groups make (erase) sectors. Sectors, gathered together, make banks inside the chip. Until now, there was only one bank per device supported, but we are about to introduce support for new chips featuring several banks (up to 4 so far) where different operations may happen in parallel. Let's allow describing these additional bank parameters, and let's do this independently of any other value (like the number of sectors) with an absolute value. By default we consider that all chips have a single bank. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20230328154105.448540-2-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
* | mtd: spi-nor: fix memory leak when using debugfs_lookup()Greg Kroah-Hartman2023-03-061-0/+2
|/ | | | | | | | | | | | | | | | | When calling debugfs_lookup() the result must have dput() called on it, otherwise the memory will leak over time. To solve this, remove the lookup and create the directory on the first device found, and then remove it when the module is unloaded. Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: Pratyush Yadav <pratyush@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230208160230.2179905-1-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: Fix shift-out-of-bounds in spi_nor_set_erase_typeLouis Rannou2023-02-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | spi_nor_set_erase_type() was used either to set or to mask out an erase type. When we used it to mask out an erase type a shift-out-of-bounds was hit: UBSAN: shift-out-of-bounds in drivers/mtd/spi-nor/core.c:2237:24 shift exponent 4294967295 is too large for 32-bit type 'int' The setting of the size_{shift, mask} and of the opcode are unnecessary when the erase size is zero, as throughout the code just the erase size is considered to determine whether an erase type is supported or not. Setting the opcode to 0xFF was wrong too as nobody guarantees that 0xFF is an unused opcode. Thus when masking out an erase type, just set the erase size to zero. This will fix the shift-out-of-bounds. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Reported-by: Alexander Stein <Alexander.Stein@tq-group.com> Signed-off-by: Louis Rannou <lrannou@baylibre.com> Tested-by: Alexander Stein <Alexander.Stein@tq-group.com> Link: https://lore.kernel.org/r/20230203070754.50677-1-tudor.ambarus@linaro.org [ta: refine changes, new commit message, fix compilation error] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
* mtd: spi-nor: Create macros to define chip IDs and geometriesMiquel Raynal2023-01-261-23/+20
| | | | | | | | | | | | | | | | | | The INFO() macro defines an ID array and a couple of geometry properties. Right now all its lines are duplicated twice because of the INFO6() macro (for extended IDs) and soon as well we will need to add a geometry parameter to include the number of banks. In order to limit the code duplication, let's create a number of intermediate macros which will facilitate defining high-level INFOX() macros. There is no functional change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20221215081241.407098-2-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
* mtd: spi-nor: add SFDP fixups for Quad Page ProgramSudip Mukherjee2022-11-221-0/+2
| | | | | | | | | | | SFDP table of some flash chips do not advertise support of Quad Input Page Program even though it has support. Use flags and add hardware cap for these chips. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> [tudor.ambarus@microchip.com: move pp setting in spi_nor_init_default_params] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220920184808.44876-2-sudip.mukherjee@sifive.com
* mtd: spi-nor: add generic flash driverMichael Walle2022-11-211-0/+1
| | | | | | | | | | | | | Our SFDP parsing is everything we need to support all basic operations of a flash device. If the flash isn't found in our in-kernel flash database, gracefully fall back to a driver described solely by its SFDP tables. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20220810220654.1297699-7-michael@walle.cc
* mtd: spi-nor: move function declaration out of sfdp.hMichael Walle2022-11-211-0/+2
| | | | | | | | | | sfdp.h should only contain constants related to the JEDEC SFDP specification(s). Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20220810220654.1297699-5-michael@walle.cc
* mtd: spi-nor: core: Track flash's internal address modeTudor Ambarus2022-07-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to track the flash's internal address mode as there are flashes that can operate with 4B opcodes but unfortunately do not have a 4B opcode correspondent for all the 3B opcodes. Such an example is the Infineon Semper chips which provide 4B opcodes for read/program/erase but do not provide 4B opcodes for Read/Write Any Register. These registers are indexed by address and require the internal address mode of the flash before Read/Write Any Register opcodes are issued. 4B opcodes are preferred over changing the flash's address mode to 4byte, as set_4byte_addr_mode could be done in a non-volatile way and could break the boot sequence. Thus we need to track the flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. Track flash's internal address mode. addr_mode_nbytes is discovered when parsing BFPT. For the BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method that queries the flash's internal address mode at run-time (works for Winbond). If a run-time querying can not be accomplished or if SFDP is not defined at all, but the address mode is volatile and resets to a default known value at boot, one can change the default addr_mode_nbytes value of 3 by introducing a flash_info flag. If the address mode can not be queried, discovered and it is configured via a non-volatile register, we may introduce a dt property, but it will harm the generic approach of the jedec,spi-nor compatible. All this complexity is not needed now, so let it for future development. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220725092505.446315-6-tudor.ambarus@microchip.com
* mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing timeTudor Ambarus2022-07-281-0/+2
| | | | | | | | | | | | | | At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by callers. The caller will then decide if SFDP params should be used and more importantly when they should be used. Clean the code flow and don't initialize nor->addr_nbytes at SFDP parsing time. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-4-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytesTudor Ambarus2022-07-281-1/+1
| | | | | | | | | | The maximum number of address bytes in SPI NOR is 4. Shrink the storage size of the flash_info's addr_nbytes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-3-tudor.ambarus@microchip.com
* mtd: spi-nor: s/addr_width/addr_nbytesTudor Ambarus2022-07-281-6/+6
| | | | | | | | | | | | Address width was an unfortunate name, as it means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR framework. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com
* mtd: spi-nor: move SECT_4K_PMC special handlingMichael Walle2022-06-271-2/+0
| | | | | | | | | | | The SECT_4K_PMC flag will set a device specific opcode for the 4k sector erase. Instead of handling it in the core, we can move it to a late_init(). In that late init, loop over all erase types, look for the 4k size and replace the opcode. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220418112650.2791459-1-michael@walle.cc
* mtd: spi-nor: expose internal parameters via debugfsMichael Walle2022-05-091-0/+7
| | | | | | | | | | | | | There is no way to gather all information to verify support for a new flash chip. Also if you want to convert an existing flash chip to the new SFDP parsing, there is not enough information to determine if the flash will work like before. To ease this development, expose internal parameters via the debugfs. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429102018.2361038-2-michael@walle.cc
* mtd: spi-nor: export spi_nor_hwcaps_pp2cmd()Michael Walle2022-05-091-0/+1
| | | | | | | | | The function will also be used by the debugfs module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429102018.2361038-1-michael@walle.cc
* mtd: spi-nor: move spi_nor_write_ear() to winbond moduleMichael Walle2022-05-021-7/+0
| | | | | | | | | | | | | The "Extended Address Register" is winbond specific. If the flash is larger than 16MiB and is used in 3 byte address mode, it is used to set the remaining address bits. Move the write_ear() function, the opcode macros and the spimem op template into the winbond module and rename them accordingly. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429100153.2338501-1-michael@walle.cc
* mtd: spi-nor: amend the rdsr dummy cycles documentationMichael Walle2022-04-291-2/+3
| | | | | | | | | | The rdsr dummy cycles are only used by the 8d-8d-8d mode. Mention that in the documentation. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220418112837.2792242-1-michael@walle.cc
* mtd: spi-nor: Introduce templates for SPI NOR operationsTudor Ambarus2022-04-271-0/+102
| | | | | | | | | | | Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220420103427.47867-10-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Add helpers to read/write any registerTudor Ambarus2022-04-271-0/+4
| | | | | | | | | | | | | | | There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-7-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Introduce method for RDID opTudor Ambarus2022-04-271-0/+9
| | | | | | | | | | | | | RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-5-tudor.ambarus@microchip.com
* mtd: spi-nor: renumber flagsMichael Walle2022-02-251-14/+14
| | | | | | | | | As we have deleted some flag, lets renumber them so there are no holes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-33-michael@walle.cc
* mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flagMichael Walle2022-02-251-3/+0
| | | | | | | | | | | Now that all functions using that flag are local to the spansion module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-30-michael@walle.cc
* mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flagMichael Walle2022-02-251-3/+0
| | | | | | | | | | | Now that all functions using that flag are local to the micron module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-26-michael@walle.cc
* mtd: spi-nor: move all xilinx specifics into xilinx.cMichael Walle2022-02-251-18/+0
| | | | | | | | | | | Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
* mtd: spi-nor: guard _page_size parameter in S3AN_INFO()Michael Walle2022-02-251-2/+2
| | | | | | | | | | The _page_size marco parameter was missing parentheses around it. Add them. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-21-michael@walle.cc
* mtd: spi-nor: export more functions to be used in vendor modulesMichael Walle2022-02-251-0/+6
| | | | | | | | | | We will move vendor specific code into the vendor modules and thus we will have to export these functions so they can be called. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-20-michael@walle.cc
* mtd: spi-nor: allow a flash to define its own ready() functionMichael Walle2022-02-251-0/+4
| | | | | | | | | | | | | Xilinx and Micron flashes have their own implementation of the spi_nor_ready() function. At the moment, the core will figure out which one to call according to some flags. Lay the foundation to make it possible that a flash can register its own ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-19-michael@walle.cc
* mtd: spi-nor: slightly refactor the spi_nor_setup()Michael Walle2022-02-251-4/+4
| | | | | | | | | | | | | Instead of always using a function pointer (and initializing it to our default), just call the default function if the flash didn't set its own one. That will make the call flow easier to follow. Also mark the parameter as optional now. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-18-michael@walle.cc
* mtd: spi-nor: Rework the flash_info flagsTudor Ambarus2021-12-071-84/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clarify for what the flash_info flags are used for. Split them in four categories and a bool: 1/ FLAGS: flags that indicate support that is not defined by the JESD216 standard in its SFDP tables. 2/ NO_SFDP_FLAGS: these flags are used when the flash does not define the SFDP tables. These flags indicate support that can be discovered via SFDP. Used together with SPI_NOR_SKIP_SFDP flag. 3/ FIXUP_FLAGS: flags that indicate support that can be discovered via SFDP ideally, but can not be discovered for this particular flash because the SFDP table that indicates this support is not defined by the flash. In case the table for this support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. 4/ MFR_FLAGS: manufacturer private flags. Used in the manufacturer fixup hooks to differentiate support between flashes of the same manufacturer. 5/ PARSE_SFDP: sets info->parse_sfdp to true. All flash_info entries that support SFDP should be converted to set info->parse_sfdp to true. SPI NOR flashes that statically declare one of the SPI_NOR_{DUAL, QUAD, OCTAL, OCTAL_DTR}_READ flags and do not support the RDSFDP command are gratuiously receiving the RDSFDP command in the attempt of parsing the SFDP tables. It is not desirable to issue commands that are not supported, so introduce PARSE_SFDP to help on this situation. New flash additions/updates should be declared/updated to use either PARSE_SFDP or SPI_NOR_SKIP_SFDP. Once all the flash_info entries are converted to use SPI_NOR_SKIP_SFDP or PARSE_SFDP, we can get rid of the SPI_NOR_SKIP_SFDP flag and use just the bool nor->info->parse_sfdp to determine whether to parse SFDP or not. SPI_NOR_SKIP_SFDP flag is kept just as a way to differentiate whether a flash is converted to the new flags logic or not. Support that can be discovered when parsing SFDP should not be duplicated by explicit flags at flash declaration. All the flash parameters will be discovered when parsing SFDP. Sometimes manufacturers wrongly define some fields in the SFDP tables. If that's the case, SFDP data can be amended with the fixups() hooks. It is not common, but if the SFDP tables are entirely wrong, and it does not worth the hassle to tweak the SFDP parameters by using the fixups hooks, or if the flash does not define the SFDP tables at all, then statically init the flash with the SPI_NOR_SKIP_SFDP flag and specify the rest of flash capabilities with the flash info flags. With time, we want to convert all flashes to use PARSE_SFDP and stop triggering the SFDP parsing with the SPI_NOR_{DUAL, QUAD, OCTAL*}_READ flags. Getting rid of the SPI_NOR_{OCTAL, OCTAL_DTR}_READ trigger is easily achievable, the rest are a long term goal. Manufacturer specific flags like USE_CLSR, USE_FSR, SPI_NOR_XSR_RDY, will be removed in a future series. No functional changes intended in this patch. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-7-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Introduce flash_info mfr_flagsTudor Ambarus2021-12-071-1/+9
| | | | | | | | | | | Used in the manufacturer fixup hooks to differentiate support between flashes of the same manufacturer. Not used in the SPI NOR core. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-6-tudor.ambarus@microchip.com
* mtd: spi-nor: Introduce spi_nor_set_mtd_info()Tudor Ambarus2021-12-071-2/+2
| | | | | | | | | | | | | | | | | | Used to init all the mtd_info fields. Move the mtd_info init the last thing in the spi_nor_scan(), so that we avoid superfluous initialization of the mtd_info fields in case of errors. While here use common naming scheme for functions that are setting mtd_info fields: s/spi_nor_register_locking_ops/spi_nor_set_mtd_locking_ops s/spi_nor_otp_init/spi_nor_set_mtd_otp_ops The functions names are self explanatory, get rid of the comment for the OTP function. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-4-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Introduce the late_init() hookTudor Ambarus2021-11-171-0/+4
| | | | | | | | | | | | | | | | | | | | | Flash parameters init is done in a spaghetti way right now. There is the init based on the flash_info data, then there is the default_init() hook, then SFDP init, an intermediary post_bft(), then post_sfdp() and a spi_nor_late_init_params(). Each method can overwrite previuosly initialized parameters. We want to separate what is SFDP and non-SFDP specific. late_init() will replace the default_init() hook and will be used only to initialize flash parameters that are not declared in the JESD216 SFDP standard, or where SFDP tables are not defined at all. We cut a member in the chain of initializing parameters by getting rid of the default_init() hook, and we make it clear that everything that is in late_init() is not covered by the SFDP tables defined by the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211029172633.886453-6-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Use container_of to get the pointer to struct spi_norTudor Ambarus2021-11-171-2/+2
| | | | | | | | | | | | "struct mtd_info mtd" is member of "struct spi_nor", there's no need to use "mtd->priv". Get the pointer to the containing struct spi_nor by using container_of. While here, make the function inline and get rid of the __maybe_unused. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211029172633.886453-3-tudor.ambarus@microchip.com
* mtd: spi-nor: core: Fix spi_nor_flash_parameter otp descriptionTudor Ambarus2021-11-171-2/+1
| | | | | | | | | | Update the description of the otp member of the struct spi_nor_flash_parameter. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20211029172633.886453-2-tudor.ambarus@microchip.com
* mtd: spi-nor: add initial sysfs supportMichael Walle2021-06-151-0/+2
| | | | | | | | | | | Add support to show the manufacturer, the partname and JEDEC identifier as well as to dump the SFDP table. Not all flashes list their SFDP table contents in their datasheet. So having that is useful. It might also be helpful in bug reports from users. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* mtd: spi-nor: sfdp: save a copy of the SFDP dataMichael Walle2021-06-151-0/+10
| | | | | | | | | | | Due to possible mode switching to 8D-8D-8D, it might not be possible to read the SFDP after the initial probe. To be able to dump the SFDP via sysfs afterwards, make a complete copy of it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
* mtd: spi-nor: otp: implement erase for Winbond and similar flashesMichael Walle2021-06-091-0/+4
| | | | | | | | | | | | | Winbond flashes with OTP support provide a command to erase the OTP data. This might come in handy during development. This was tested with a Winbond W25Q32JW on a LS1028A SoC with the NXP FSPI controller. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: core: Constify buf in mtd_write_user_prot_reg()Tudor Ambarus2021-04-161-2/+4
| | | | | | | | | | | | | | The write buffer comes from user and should be const. Constify write buffer in mtd core and across all _write_user_prot_reg() users. cfi_cmdset_{0001, 0002} and onenand_base will pay the cost of an explicit cast to discard the const qualifier since the beginning, since they are using an otp_op_t function prototype that is used for both reads and writes. mtd_dataflash and SPI NOR will benefit of the const buffer because they are using different paths for writes and reads. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210403060931.7119-1-tudor.ambarus@microchip.com
* mtd: spi-nor: implement OTP support for Winbond and similar flashesMichael Walle2021-04-021-0/+6
| | | | | | | | | | | | | | | | | | Use the new OTP ops to implement OTP access on Winbond flashes. Most Winbond flashes provides up to four different OTP regions ("Security Registers"). Winbond devices use a special opcode to read and write to the OTP regions, just like the RDSFDP opcode. In fact, it seems that the (undocumented) first OTP area of the newer flashes is the actual SFDP table. On a side note, Winbond devices also allow erasing the OTP regions as long as the area isn't locked down. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210321235140.8308-3-michael@walle.cc
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