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* Merge tag 'mtd/for-5.3' of ↵Linus Torvalds2019-07-136-718/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "This contains the following changes for MTD: MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: - fix BCH ECC layout for large page NAND parts - fallback to detected ecc-strength, ecc-step-size - when oops in progress use pio and interrupt polling - code refactor code to introduce helper functions - add support for v7.3 controller - FSMC: - use nand_op_trace for operation tracing - GPMI: - move all driver code into single file - various cleanups (including dmaengine changes) - use runtime PM to manage clocks - implement exec_op - MTK: - correct low level time calculation of r/w cycle - improve data sampling timing for read cycle - add validity check for CE# pin setting - fix wrongly assigned OOB buffer pointer issue - re-license MTK NAND driver as Dual MIT/GPL - STM32: - manage the get_irq error case - increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control" * tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits) mtd: concat: implement _is_locked mtd operation mtd: concat: refactor concat_lock/concat_unlock mtd: abi: do not use C++ style comments in uapi header mtd: afs: remove unneeded NULL check mtd: rawnand: stm32_fmc2: increase DMA completion timeouts mtd: rawnand: Use kzalloc() instead of kmalloc() and memset() mtd: hyperbus: Add driver for TI's HyperBus memory controller mtd: spinand: read returns badly if the last page has bitflips mtd: spinand: Add initial support for Paragon PN26G0xA mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL mtd: rawnand: gpmi: remove double assignment to block_size dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling mtd: Add flag to indicate panic_write mtd: rawnand: Add Macronix NAND read retry support mtd: onenand: Avoid fall-through warnings mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG mtd: spinand: Add support for two-byte device IDs ...
| * Merge tag 'spi-nor/for-5.3-v2' of ↵Miquel Raynal2019-07-079-747/+60
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control
| | * mtd: spi-nor: cadence-quadspi: add reset controlDinh Nguyen2019-06-271-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get the reset control properties for the QSPI controller and bring them out of reset. Most will have just one reset bit, but there is an additional OCP reset bit that is used ECC. The OCP reset bit will also need to get de-asserted as well. [1] The reason this patch is needed is in the case where a bootloader leaves the QSPI controller in a reset state, or a state where init cannot occur successfully, the patch will put the QSPI controller into a clean state. [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: declare rstc and rstc_ocp on the same line] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: fix nor->addr_width when its value configured from SFDP does ↵Liu Xiang2019-06-271-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | not match the actual width IS25LP256 gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for address width. But in actual fact the flash can support 4-byte address. Use a post bfpt fixup hook to overwrite the address width advertised by the BFPT. Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: intel-spi: Convert to use SPDX identifierMika Westerberg2019-06-224-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This gets rid of the license boilerplate duplicated in each file. No functional changes intended. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: intel-spi: Add support for Intel Elkhart Lake SPI serial flashMika Westerberg2019-06-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Intel Elkhart Lake has the same SPI serial flash controller as Ice Lake. Add Elkhart Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Spelling s/Writ/Write/Geert Uytterhoeven2019-06-221-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Add Winbond w25q16jv supportRobert Marko2019-06-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing done on Mikrotik Routerboard RB450Gx4 board under 4.14.119 and 4.19.43 kernels. The test board does not support Dual or Quad modes. Datasheet at: https://www.winbond.com/resource-files/w25q16jv%20spi%20revg%2003222018%20plus.pdf Signed-off-by: Robert Marko <robimarko@gmail.com> [tudor.ambarus@microchip.com: w25q16jv-im/jm and w25q16jv-iq/jq have different jedec ids, fix flash name.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: change "error reading JEDEC id" from dbg to errFlavio Suligoi2019-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of SPI error during the reading of the nor Id, the probe fails without any error message related to the JEDEC Id reading procedure. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Add Micron MT25QL02 supportAndrey Smirnov2019-06-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an entry for Micron MT25QL02 which is a 3V variant of already supported MT25QU02. Testing was done on a ZII VF610 Dev Board (rev. B). Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org [tudor.ambarus@microchip.com: order entry alphabetically, wrap to 80 chars limit] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: stm32: remove the driver as it was replaced by spi-stm32-qspi.cLudovic Barre2019-06-073-728/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a new driver using the SPI memory interface of the SPI framework at spi/spi-stm32-qspi.c, which can be used together with m25p80.c to replace the functionality of this SPI NOR driver. The "new" driver uses the same dt properties and not affects the legacy compatibility. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | | Merge tag 'mtd/fixes-for-5.2-rc7' of ↵Linus Torvalds2019-06-241-11/+108
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd fixes from Miquel Raynal: - Set the raw NAND number of targets to the right value - Fix a bug uncovered by a recent patch on Spansion SPI-NOR flashes * tag 'mtd/fixes-for-5.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes mtd: rawnand: initialize ntargets with maxchips
| * | | mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashesTudor Ambarus2019-06-231-11/+108
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI memory devices from different manufacturers have widely different configurations for Status, Control and Configuration registers. JEDEC 216C defines a new map for these common register bits and their functions, and describes how the individual bits may be accessed for a specific device. For the JEDEC 216B compliant flashes, we can partially deduce Status and Configuration registers functions by inspecting the 16th DWORD of BFPT. Older flashes that don't declare the SFDP tables (SPANSION FL512SAIFG1 311QQ063 A ©11 SPANSION) let the software decide how to interact with these registers. The commit dcb4b22eeaf4 ("spi-nor: s25fl512s supports region locking") uncovered a probe error for s25fl512s, when the Quad Enable bit CR[1] was set to one in the bootloader. When this bit is one, only the Write Status (01h) command with two data byts may be used, the 01h command with one data byte is not recognized and hence the error when trying to clear the block protection bits. Fix the above by using the Write Status (01h) command with two data bytes when the Quad Enable bit is one. Backward compatibility should be fine. The newly introduced spi_nor_spansion_clear_sr_bp() is tightly coupled with the spansion_quad_enable() function. Both assume that the Write Register with 16 bits, together with the Read Configuration Register (35h) instructions are supported. Fixes: dcb4b22eeaf44f91 ("spi-nor: s25fl512s supports region locking") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Jonas Bonn <jonas@norrbonn.se> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-195-21/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-14/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner2019-05-211-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details [based] [from] [clk] [highbank] [c] you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 355 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
|/ | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* spi-nor: intel-spi: Add support for Intel Comet Lake SPI serial flashMika Westerberg2019-05-061-0/+1
| | | | | | | | | Intel Comet Lake has the same SPI serial flash controller as Ice Lake. Add Comet Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* spi-nor: s25fl512s supports region lockingJonas Bonn2019-04-011-1/+3
| | | | | | | | | Both the BP[0-2] bits and the TBPROT bit are supported on this chip. Tested and verified on a Cypress s25fl512s. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: spi-nor: intel-spi: Avoid crossing 4K address boundary on read/writeAlexander Sverdlin2019-04-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was observed that reads crossing 4K address boundary are failing. This limitation is mentioned in Intel documents: Intel(R) 9 Series Chipset Family Platform Controller Hub (PCH) Datasheet: "5.26.3 Flash Access Program Register Access: * Program Register Accesses are not allowed to cross a 4 KB boundary..." Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms): "5.1.4 Address For other memory transactions, the address may start or end at any byte boundary. However, the address and payload length combination must not cross the naturally aligned address boundary of the corresponding Maximum Payload Size. It must not cross a 4 KB address boundary." Avoid this by splitting an operation crossing the boundary into two operations. Fixes: 8afda8b26d01 ("spi-nor: Add support for Intel SPI serial flash controller") Cc: stable@vger.kernel.org Reported-by: Romain Porte <romain.porte@nokia.com> Tested-by: Pascal Fabreges <pascal.fabreges@nokia.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: spi-nor: Fix comment of spi_nor_find_best_erase_type()Alexander Sverdlin2019-03-211-1/+1
| | | | | | | | | Erase types are sorted *smallest* type first, refer to spi_nor_sort_erase_mask(). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: spi-nor: Print all JEDEC ID bytes on errorGeert Uytterhoeven2019-03-211-2/+2
| | | | | | | | | | | | | | | If identification of an SPI NOR FLASH fails, the JEDEC ID is printed, which is stored in the first 3 bytes of the ID read from the FLASH. However, the extended JEDEC ID, which is stored in the remaining bytes, also matters, as it is used for identification of some FLASH types. Print all (currently 6) ID bytes read to ease failure analysis and debugging. Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* Merge tag 'spi-v5.1' of ↵Linus Torvalds2019-03-043-1234/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A fairly quiet release for SPI, the biggest thing is the conversion to use GPIO descriptors which is now 90% done but still needs some stragglers converting. Summary: - Support for inter-word delays - Conversion of the core and most drivers to use GPIO descriptors for GPIO controlled chip selects - New drivers for NXP FlexSPI and QuadSPI, SiFive and Spreadtrum" * tag 'spi-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (104 commits) spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3 spi: sifive: Remove redundant dev_err call in sifive_spi_probe() spi: sifive: Remove spi_master_put in sifive_spi_remove() spi: spi-gpio: fix SPI_CS_HIGH capability spi: pxa2xx: Setup maximum supported DMA transfer length spi: sifive: Add driver for the SiFive SPI controller spi: sifive: Add DT documentation for SiFive SPI controller spi: sprd: Add a prefix for SPI DMA channel macros spi: sprd: spi: sprd: Add DMA mode support dt-bindings: spi: Add the DMA properties for the SPI dma mode spi: sprd: Add the SPI irq function for the SPI DMA mode dt-bindings: spi: imx: Add an entry for the i.MX8QM compatible spi: use gpio[d]_set_value_cansleep for setting chipselect GPIO spi: gpio: Advertise support for SPI_CS_HIGH spi: sh-msiof: Replace spi_master by spi_controller spi: sh-hspi: Replace spi_master by spi_controller spi: rspi: Replace spi_master by spi_controller spi: atmel-quadspi: add support for sam9x60 qspi controller dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 spi: atmel-quadspi: add support for named peripheral clock ...
| * mtd: fsl-quadspi: Remove the driver as it was replaced by spi-fsl-qspi.cFrieder Schrempf2019-01-071-1224/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a new driver using the SPI memory interface of the SPI framework at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to replace the functionality of this SPI NOR driver. The new driver is already in use and this code is not compiled anymore, so let's remove it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Han Xu <han.xu@nxp.com> Tested-by: Han Xu <han.xu@nxp.com> Acked-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Add a driver for the Freescale/NXP QuadSPI controllerFrieder Schrempf2019-01-072-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each). The controller does not support generic SPI messages. This patch also disables the build of the "old" driver and reuses its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Han Xu <han.xu@nxp.com> Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Han Xu <han.xu@nxp.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | mtd: spi-nor: cadence-quadspi: fix spelling mistake: "Couldnt't" -> "Couldn't"Colin Ian King2019-02-211-1/+1
| | | | | | | | | | | | | | | | There is a spelling mistake in a dev_error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: Add support for en25qh64Roger Pueyo Centelles2019-02-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found on recent wireless routers. Its 32, 128 and 256 Mbit siblings are already supported. Tested on a COMFAST CF-E120A v3 router board. Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: Add support for MX25V8035FFrieder Schrempf2019-02-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip. It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: Add support for EN25Q80AFrieder Schrempf2019-02-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. It is used on i.MX6 boards by Kontron Electronics GmbH (N60xx, N61xx). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controllerVignesh R2019-02-131-12/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Only Octal SDR read (1-1-8)mode is supported for now. Tested with mt35xu512aba Octal flash on TI's AM654 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1Ahmet Celenk2019-02-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of the s25fl128s qspi memory, the single "s25fl128s" device entry must be split into two to match the correct JEDEC ID's for each version. Solves paging related issues of S25FL128SAGBHI210 chips. Signed-off-by: Ahmet Celenk <ahmet.celenk@procenne.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG modePurna Chandra Mandal2019-02-101-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | cadence-quadspi controller allows upto eight bytes of data to be written in software Triggered Instruction generator (STIG) mode of operation. Lower 4 bytes are written through writedatalower and upper 4 bytes by writedataupper register. This patch allows all the 8 bytes to be written. Signed-off-by: Purna Chandra Mandal <purna.chandra.mandal@intel.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: Add support for mx25u3235fAndré Valentin2019-02-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The mx25u3235f is found on the ZyXEL NBG6817 router, therefore add driver support for it so that we can upstream board support. Minimal tested with u-boot tools fw_printenv/fw_setenv on GlobalScale ESPRESSObin v5 board. Signed-off-by: André Valentin <avalentin@marcant.net> [miyatsu@qq.com: Remove unnecessary white space.] Signed-off-by: Ding Tao <miyatsu@qq.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
* | mtd: spi-nor: refine Spansion S25FL512S IDSergei Shtylyov2019-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | Spansion S25FL512S ID is erroneously using 5-byte JEDEC ID, while the chip family ID is stored in the 6th byte. Due to using only 5-byte ID, it's also covering S25FS512S and now that we have added 6-byte ID for that chip, we can convert S25FL512S to using a proper 6-byte ID as well... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* | mtd: spi-nor: add Spansion S25FS512S IDSergei Shtylyov2019-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | Spansion S25FS512S flash is currently misdetected as S25FL512S since the latter uses 5-byte JEDEC ID, while the 6th ID byte (family ID) is different on those chips. Add the 6-byte S25FS512S ID before S25FL512S ID in order not to break the existing S25FS512S users. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* | mtd: spi-nor: add octal read flag for flash mt35xu512abaYogesh Narayan Gaur2019-01-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add octal read flag for flash mt35xu512aba. This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does not seem to support newer JESD216C standard that provides auto detection of Octal mode capabilities and opcodes. Therefore, this capability is manually added using new SPI_NOR_OCTAL_READ flag. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* | mtd: spi-nor: add opcodes for octal Read/Write commandsYogesh Narayan Gaur2019-01-171-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add opcodes for octal I/O commands * Read : 1-1-8 and 1-8-8 protocol * Write : 1-1-8 and 1-8-8 protocol * opcodes for 4-byte address mode command - Entry of macros in _convert_3to4_xxx function - Add flag SPI_NOR_OCTAL_READ specifying flash support octal read commands. This flag is required for flashes which didn't provides support for auto detection of Octal mode capabilities i.e. not seems to support newer JESD216C standard. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* | mtd: spi-nor: mtk-quadspi: rename config to a common oneRyder Lee2019-01-162-9/+9
| | | | | | | | | | | | | | | | | | The quadspi is a generic communication interface which could be shared with other MediaTek SoCs. Hence rename it to a common one. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* | mtd: spi-nor: mtk-quadspi: add SNOR_HWCAPS_READ to spi_nor_hwcaps maskGuochun Mao2019-01-161-1/+2
|/ | | | | | | | | | SNOR_HWCAPS_READ should be supported by this controller, so add this flag to spi_nor_hwcaps mask. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
* Merge tag 'spi-v4.21' of ↵Linus Torvalds2018-12-253-791/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The main thing this release has been a lot of work on the integration with SPI NOR flashes, there's been some specific support for a while for controller features designed to make them perform better but it's not worked out as well as hoped so the interface has been redesigned in a way that will hopefully do better - it's already been adopted by a number of additional controllers so things are looking good. Otherwise most of the work has been driver specific: - Support for better integration with NOR flashes from Boris Brezillon and Yogesh Narayan Gaur plus usage of it in several drivers. - A big cleanup of the Rockchip driver from Emil Renner Berthing. - Lots of performance improvements for bcm2835 from Lukas Wunner. - Slave mode support for pxa2xx from Lubomir Rintel. - Support for Macronix MXIC, Mediatek MT7629 and MT8183, NPCM PSPI, and Renesas r8a77470" * tag 'spi-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (90 commits) spi: sh-msiof: Reduce the number of times write to and perform the transmission from FIFO spi: sh-msiof: Add r8a774c0 support doc: lpspi: Document DT bindings for LPSPI slave mode spi: lpspi: Let watermark change with send data length spi: lpspi: Add slave mode support spi: lpspi: Replace all "master" with "controller" spi: imx: drop useless member speed_hz from driver data struct spi: imx: rename config callback and add useful parameters spi: imx: style fixes spi: imx: mx51-ecspi: Move some initialisation to prepare_message hook. spi: imx: add a device specific prepare_message callback mtd: atmel-quadspi: disallow building on ebsa110 spi: Update NPCM PSPI controller documentation spi: npcm: Modify pspi send function spi: Use of_node_name_eq for node name comparisons spi: dw-mmio: add ACPI support spi: bcm2835: Synchronize with callback on DMA termination spi: bcm2835: Speed up FIFO access if fill level is known spi: bcm2835: Polish transfer of DMA prologue spi: spi-mem: add support for octal mode I/O data transfer ...
| *-. Merge remote-tracking branches 'spi/topic/mem' and 'spi/topic/mtd' into spi-nextMark Brown2018-12-203-791/+0
| |\ \
| | | * spi: Add QuadSPI driver for Atmel SAMA5D2Piotr Bugalski2018-11-073-559/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel contains QSPI driver strongly tied to MTD and nor-flash memory. New spi-mem interface allows usage also other memory types, especially much larger NAND with SPI interface. This driver works as SPI controller and is not related to MTD, however can work with NAND-flash or other peripherals using spi-mem interface. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * mtd: spi-nor: atmel-quadspi: Remove unused code from atmel-quadspi driverPiotr Bugalski2018-11-071-388/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code used for previous interface is no longer needed. This change just removes obsolete code. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driverPiotr Bugalski2018-11-071-73/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously added spi-mem interface is now used instead of older approach. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspiPiotr Bugalski2018-11-071-0/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new interface to existing driver. New code is not used yet, it will be enabled later. Changes are prepared in small steps to keep patches readable. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * mtd: spi-nor: atmel-quaspi: Typo fixPiotr Bugalski2018-11-071-2/+2
| | |/ | | | | | | | | | | | | | | | | | | Just minor typo fix. Fixed in preparation of new driver. Signed-off: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | mtd: spi-nor: Add support for is25lp016dFabrizio Castro2018-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The is25lp016d is found on the iwg23s from iWave, therefore add driver support for it so that we can upstream board support. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 08:00:42 +0000