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* mtd: spi-nor: hisi-sfc: Put child node np on error pathPan Bian2021-03-041-1/+3
| | | | | | | | | | | | | | commit fe6653460ee7a7dbe0cd5fd322992af862ce5ab0 upstream. Put the child node np when it fails to get or register device. Fixes: e523f11141bd ("mtd: spi-nor: add hisilicon spi-nor flash controller driver") Cc: stable@vger.kernel.org Signed-off-by: Pan Bian <bianpan2016@163.com> [ta: Add Fixes tag and Cc stable] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210121091847.85362-1-bianpan2016@163.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: core: Add erase size check for erase command initializationTakahiro Kuwano2021-03-041-0/+1
| | | | | | | | | | | | | | | | | commit 58fa22f68fcaff20ce4d08a6adffa64f65ccd37d upstream. Even if erase type is same as previous region, erase size can be different if the previous region is overlaid region. Since 'region->size' is assigned to 'cmd->size' for overlaid region, comparing 'erase->size' and 'cmd->size' can detect previous overlaid region. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/13d47e8d8991b8a7fd8cc7b9e2a5319c56df35cc.1601612872.git.Takahiro.Kuwano@infineon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: core: Fix erase type discovery for overlaid regionTakahiro Kuwano2021-03-041-4/+5
| | | | | | | | | | | | | | | | | | | | commit 969b276718de37dfe66fce3a5633f611e8cd58fd upstream. In case of overlaid regions in which their biggest erase size command overpasses in size the region's size, only the non-overlaid portion of the sector gets erased. For example, if a Sector Erase command is applied to a 256-kB range that is overlaid by 4-kB sectors, the overlaid 4-kB sectors are not affected by the erase. For overlaid regions, 'region->size' is assigned to 'cmd->size' later in spi_nor_init_erase_cmd(), so 'erase->size' can be greater than 'len'. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> [ta: Update commit description, add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/fa5d8b944a5cca488ac54ba37c95e775ac2deb34.1601612872.git.Takahiro.Kuwano@infineon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: sfdp: Fix wrong erase type bitmask for overlaid regionTakahiro Kuwano2021-03-041-1/+1
| | | | | | | | | | | | | | | | commit abdf5a5ef9652bad4d58058bc22ddf23543ba3e1 upstream. At the time spi_nor_region_check_overlay() is called, the erase types are sorted in ascending order of erase size. The 'erase_type' should be masked with 'BIT(erase[i].idx)' instead of 'BIT(i)'. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/fd90c40d5b626a1319a78fc2bcee79a8871d4d57.1601612872.git.Takahiro.Kuwano@infineon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: sfdp: Fix last erase region markingTakahiro Kuwano2021-03-041-2/+1
| | | | | | | | | | | | | | | commit 9166f4af32db74e1544a2149aef231ff24515ea3 upstream. The place of spi_nor_region_mark_end() must be moved, because 'i' is re-used for the index of erase[]. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/02ce8d84b7989ebee33382f6494df53778dd508e.1601612872.git.Takahiro.Kuwano@infineon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* spi: cadence-quadspi: Abort read if dummy cycles required are too manyPratyush Yadav2021-03-041-1/+1
| | | | | | | | | | | | | | | | [ Upstream commit ceeda328edeeeeac7579e9dbf0610785a3b83d39 ] The controller can only support up to 31 dummy cycles. If the command requires more it falls back to using 31. This command is likely to fail because the correct number of cycles are not waited upon. Rather than silently issuing an incorrect command, fail loudly so the caller can get a chance to find out the command can't be supported by the controller. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
* mtd: spi-nor: Don't copy self-pointing struct aroundAlexander Sverdlin2020-11-101-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 69a8eed58cc09aea3b01a64997031dd5d3c02c07 upstream. spi_nor_parse_sfdp() modifies the passed structure so that it points to itself (params.erase_map.regions to params.erase_map.uniform_region). This makes it impossible to copy the local struct anywhere else. Therefore only use memcpy() in backup-restore scenario. The bug may show up like below: BUG: unable to handle page fault for address: ffffc90000b377f8 Oops: 0000 [#1] PREEMPT SMP NOPTI CPU: 4 PID: 3500 Comm: flashcp Tainted: G O 5.4.53-... #1 ... RIP: 0010:spi_nor_erase+0x8e/0x5c0 Code: 64 24 18 89 db 4d 8b b5 d0 04 00 00 4c 89 64 24 18 4c 89 64 24 20 eb 12 a8 10 0f 85 59 02 00 00 49 83 c6 10 0f 84 4f 02 00 00 <49> 8b 06 48 89 c2 48 83 e2 c0 48 89 d1 49 03 4e 08 48 39 cb 73 d8 RSP: 0018:ffffc9000217fc48 EFLAGS: 00010206 RAX: 0000000000740000 RBX: 0000000000000000 RCX: 0000000000740000 RDX: ffff8884550c9980 RSI: ffff88844f9c0bc0 RDI: ffff88844ede7bb8 RBP: 0000000000740000 R08: ffffffff815bfbe0 R09: ffff88844f9c0bc0 R10: 0000000000000000 R11: 0000000000000000 R12: ffffc9000217fc60 R13: ffff88844ede7818 R14: ffffc90000b377f8 R15: 0000000000000000 FS: 00007f4699780500(0000) GS:ffff88846ff00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffffc90000b377f8 CR3: 00000004538ee000 CR4: 0000000000340fe0 Call Trace: part_erase+0x27/0x50 mtdchar_ioctl+0x831/0xba0 ? filemap_map_pages+0x186/0x3d0 ? do_filp_open+0xad/0x110 ? _copy_to_user+0x22/0x30 ? cp_new_stat+0x150/0x180 mtdchar_unlocked_ioctl+0x2a/0x40 do_vfs_ioctl+0xa0/0x630 ? __do_sys_newfstat+0x3c/0x60 ksys_ioctl+0x70/0x80 __x64_sys_ioctl+0x16/0x20 do_syscall_64+0x6a/0x200 ? prepare_exit_to_usermode+0x50/0xd0 entry_SYSCALL_64_after_hwframe+0x44/0xa9 RIP: 0033:0x7f46996b6817 Cc: stable@vger.kernel.org Fixes: c46872170a54 ("mtd: spi-nor: Move erase_map to 'struct spi_nor_flash_parameter'") Co-developed-by: Matija Glavinic Pecotic <matija.glavinic-pecotic.ext@nokia.com> Signed-off-by: Matija Glavinic Pecotic <matija.glavinic-pecotic.ext@nokia.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Baurzhan Ismagulov <ibr@radix50.net> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201005084803.23460-1-alexander.sverdlin@nokia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: Split mt25qu512a (n25q512a) entry into twoVignesh Raghavendra2020-02-111-4/+5
| | | | | | | | | | | | | | | | | commit bd8a6e31b87b39a03ab11820776363640440dbe0 upstream. mt25q family is different from n25q family of devices, even though manf ID and device IDs are same. mt25q flash has bit 6 set in 5th byte of READ ID response which can be used to distinguish it from n25q variant. mt25q flashes support stateless 4 Byte addressing opcodes where as n25q flashes don't. Therefore, have two separate entries for mt25qu512a and n25q512a. Fixes: 9607af6f857f ("mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: Fix selection of 4-byte addressing opcodes on SpansionVignesh Raghavendra2020-01-231-3/+1
| | | | | | | | | | | | | | | | | | commit 440b6d50254bdbd84c2a665c7f53ec69dd741a4f upstream. mtd->size is still unassigned when running spansion_post_sfdp_fixups() hook, therefore use nor->params.size to determine the size of flash device. This makes sure that 4-byte addressing opcodes are used on Spansion flashes that are larger than 16MiB and don't have SFDP 4BAIT table populated. Fixes: 92094ebc385e ("mtd: spi-nor: Add spansion_post_sfdp_fixups()") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: fix silent truncation in spi_nor_read_raw()Sergei Shtylyov2020-01-171-1/+1
| | | | | | | | | | | | | | | commit 3d63ee5deb466fd66ed6ffb164a87ce36425cf36 upstream. spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: fix silent truncation in spi_nor_read()Sergei Shtylyov2020-01-171-1/+1
| | | | | | | | | | | | | | | commit a719a75a7761e4139dd099330d9fe3589d844f9b upstream. spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e1233bd ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: spi-nor: Fix direction of the write_sr() transferTudor Ambarus2019-10-041-1/+1
| | | | | | | | | | | write_sr() sends data to the SPI memory, fix the direction. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Reported-by: John Garry <john.garry@huawei.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: John Garry <john.garry@huawei.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"Ashish Kumar2019-08-301-1/+4
| | | | | | | | | | | | | | | | | | | n25q512a was rebranded to mt25qu512a after its spin off from STM. mt25qu512a is different only in terms of operating frequency, the JEDEC id is the same as in n25q512a. Dual reads are supported (0x3b, 0x3c), set the SPI_NOR_DUAL_READ flag. 4-byte opcodes are supported, set the SPI_NOR_4B_OPCODES flag. Tested Single I/O and QUAD I/O mode on LS1046FRWY. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: rename entry to "mt25qu512a (n25q512a)", reword commit message, order entry by size, drop comment as it looked redundant] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: Add support for mt35xu02gAshish Kumar2019-08-301-0/+3
| | | | | | | | | | | mt35xu02g is an Octal flash supporting Single and OCTAL I/O. Tested on LS1028ARDB. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: reword commit message] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: remove superfluous pass of nor->info->sector_sizeTudor Ambarus2019-08-291-2/+3
| | | | | | | | We already pass a pointer to nor, we can obtain the sector_size by dereferencing it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: enable the debugfs for the partname and partidZhuohao Lee2019-08-291-0/+12
| | | | | | | | | | | | | | | | This patch adds spi_nor_debugfs_init() for the debugfs initialization. With this patch, we can read the partname and partid through the debugfs. The output of new debugfs nodes on my device are: cat /sys/kernel/debug/mtd/mtd0/partid spi-nor:ef6017 cat /sys/kernel/debug/mtd/mtd0/partname w25q64dw Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: hisi-sfc: Add of_node_put() before breakNishka Dasgupta2019-08-281-0/+1
| | | | | | | | | | | Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a break from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the break. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: aspeed-smc: Add of_node_put()Nishka Dasgupta2019-08-281-1/+3
| | | | | | | | | | | | | | | Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a break from the middle of the loop, there is no put, thus causing a memory leak. Upon termination of the loop (whether by break or a natural exit), either ret will have a non-zero value or child will be NULL. Hence add an of_node_put() that will execute only when ret has a non-zero value, as calling of_node_put() on a possible NULL value does not cause any further issues. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: Introduce spi_nor_get_flash_info()Tudor Ambarus2019-08-281-32/+44
| | | | | | | | | Dedicate a function for getting the pointer to the flash_info const struct. Trim a bit the spi_nor_scan() huge function. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Introduce spi_nor_set_addr_width()Tudor Ambarus2019-08-281-20/+30
| | | | | | | | | Parsing of flash parameters were interleaved with setting of the nor addr width. Dedicate a function for setting nor addr width. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Bring flash params init togetherTudor Ambarus2019-08-281-18/+11
| | | | | | | | | Bring all flash parameters default initialization in spi_nor_legacy_params_init(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add the SPI_NOR_XSR_RDY flagBoris Brezillon2019-08-281-1/+9
| | | | | | | | | | | | | | S3AN flashes use a specific opcode to read the status register. We currently use the SPI_S3AN flag to decide whether this specific SR read opcode should be used, but SPI_S3AN is about to disappear, so let's add a new flag. Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and vice versa. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add s3an_post_sfdp_fixups()Tudor Ambarus2019-08-281-7/+11
| | | | | | | | | | | | | | | | | s3an_nor_scan() was overriding the opcode selection done in spi_nor_default_setup(). Set nor->setup() method in order to avoid the unnecessary call to spi_nor_default_setup(). Now that the call to spi_nor_default_setup() is skipped, set mtd.erasesize to nor->info->sector_size, as it was when spi_nor_select_erase() was called. No dummy byte is required for the S3AN's Random Read command (0x03), so no need to set nor->read_dummy. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add a ->setup() methodTudor Ambarus2019-08-281-211/+221
| | | | | | | | | | | | | | | nor->params.setup() configures the SPI NOR memory. Useful for SPI NOR flashes that have peculiarities to the SPI NOR standard, e.g. different opcodes, specific address calculation, page size, etc. Right now the only user will be the S3AN chips, but other manufacturers can implement it if needed. Move spi_nor_setup() related code in order to avoid a forward declaration to spi_nor_default_setup(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add a ->convert_addr() methodBoris Brezillon2019-08-281-10/+14
| | | | | | | | | | | | | | | | | In order to separate manufacturer quirks from the core we need to get rid of all the manufacturer specific flags, like the SNOR_F_S3AN_ADDR_DEFAULT one. This can easily be replaced by a ->convert_addr() hook, which when implemented will provide the core with an easy way to convert an absolute address into something the flash understands. Right now the only user are the S3AN chips, but other manufacturers can implement it if needed. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add spansion_post_sfdp_fixups()Boris Brezillon2019-08-281-14/+23
| | | | | | | | | | | Add a spansion_post_sfdp_fixups() function to fix the erase opcode, erase sector size and set the SNOR_F_4B_OPCODES flag. This way, all spansion related quirks are placed in the spansion_post_sfdp_fixups() function. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add post_sfdp() hook to tweak flash configBoris Brezillon2019-08-281-1/+32
| | | | | | | | | | | | SFDP tables are sometimes wrong and we need a way to override the config chosen by the SFDP parsing logic without discarding all of it. Add a new hook called after the SFDP parsing has taken place to deal with such problems. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Rework the SPI NOR lock/unlock logicBoris Brezillon2019-08-281-13/+37
| | | | | | | | | | | | | | Add the SNOR_F_HAS_LOCK flag and set it when SPI_NOR_HAS_LOCK is set in the flash_info entry or when it's a Micron or ST flash. Move the locking hooks in a separate struct so that we have just one field to update when we change the locking implementation. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use ->default_init() hook, introduce spi_nor_late_init_params(), set ops in nor->params] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Create a ->set_4byte() methodBoris Brezillon2019-08-281-37/+39
| | | | | | | | | | | | The procedure used to enable 4 byte addressing mode depends on the NOR device, so let's provide a hook so that manufacturer specific handling can be implemented in a sane way. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use nor->params.set_4byte() instead of nor->set_4byte()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Split spi_nor_init_params()Tudor Ambarus2019-08-281-20/+63
| | | | | | | | | | | | | | | | | | | | Add functions to delimit what the chunks of code do: static void spi_nor_init_params() { spi_nor_info_init_params() spi_nor_manufacturer_init_params() spi_nor_sfdp_init_params() } Add descriptions to all methods. spi_nor_init_params() becomes of type void, as all its children return void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Move manufacturer quad_enable() in ->default_init()Tudor Ambarus2019-08-281-19/+29
| | | | | | | | | | | | | | | The goal is to move the quad_enable manufacturer specific init in the nor->manufacturer->fixups->default_init() The legacy quad_enable() implementation is spansion_quad_enable(), select this method by default. Set specific manufacturer fixups->default_init() hooks to overwrite the default quad_enable() implementation when needed. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add a default_init() fixup hook for gd25q256Boris Brezillon2019-08-281-12/+16
| | | | | | | | | | | | | | | | gd25q256 needs to tweak the ->quad_enable() implementation and the ->default_init() fixup hook is the perfect place to do that. This way, if we ever need to tweak more things for this flash, we won't have to add new fields in flash_info. We can get rid of the flash_info->quad_enable field as gd25q256 was the only user. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use ->default_init() hook instead of ->post_sfdp()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Add default_init() hook to tweak flash parametersTudor Ambarus2019-08-281-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of now, the flash parameters initialization logic is as following: a/ default flash parameters init in spi_nor_init_params() b/ manufacturer specific flash parameters updates, split across entire spi-nor core code c/ flash parameters updates based on SFDP tables d/ post BFPT flash parameter updates In the quest of removing the manufacturer specific code from the spi-nor core, we want to impose a timeline/priority on how the flash parameters are updated. The following sequence of calls is pursued: 1/ spi-nor core parameters init based on 'flash_info' struct: spi_nor_info_init_params() which can be overwritten by: 2/ MFR-based manufacturer flash parameters init: nor->manufacturer->fixups->default_init() which can be overwritten by: 3/ specific flash_info tweeks done when decisions can not be done just on MFR: nor->info->fixups->default_init() which can be overwritten by: 4/ SFDP tables flash parameters init - SFDP knows better: spi_nor_sfdp_init_params() which can be overwritten by: 5/ post SFDP tables flash parameters updates - in case manufacturers get the serial flash tables wrong or incomplete. nor->info->fixups->post_sfdp() The later can be extended to nor->manufacturer->fixups->post_sfdp() if needed. This patch opens doors for steps 2/ and 3/. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Move erase_map to 'struct spi_nor_flash_parameter'Tudor Ambarus2019-08-281-19/+21
| | | | | | | | | | | | | | | | | | | | | | All flash parameters and settings should reside inside 'struct spi_nor_flash_parameter'. Move the SMPT parsed erase map from 'struct spi_nor' to 'struct spi_nor_flash_parameter'. Please note that there is a roll-back mechanism for the flash parameter and settings, for cases when SFDP parser fails. The SFDP parser receives a Stack allocated copy of nor->params, called sfdp_params, and uses it to retrieve the serial flash discoverable parameters. JESD216 SFDP is a standard and has a higher priority than the default initialized flash parameters, so will overwrite the sfdp_params data when needed. All SFDP code uses the local copy of nor->params, that will overwrite it in the end, if the parser succeds. Saving and restoring the nor->params.erase_map is no longer needed, since the SFDP code does not touch it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Drop quad_enable() from 'struct spi-nor'Tudor Ambarus2019-08-281-17/+23
| | | | | | | | | | All flash parameters and settings should reside inside 'struct spi_nor_flash_parameter'. Drop the local copy of quad_enable() and use the one from 'struct spi_nor_flash_parameter'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Use nor->paramsTudor Ambarus2019-08-281-27/+19
| | | | | | | | | | | | | | | | | | The Flash parameters and settings are now stored in 'struct spi_nor'. Use this instead of the stack allocated params. Few functions stop passing pointer to params, as they can get it from 'struct spi_nor'. spi_nor_parse_sfdp() and children will keep passing pointer to params because of the roll-back mechanism: in case the parsing of SFDP fails, the legacy flash parameter and settings will be restored. Zeroing params is no longer needed because all SPI NOR users kzalloc 'struct spi_nor'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Regroup flash parameter and settingsTudor Ambarus2019-08-281-65/+0
| | | | | | | | | | | | | | | | | | | | The scope is to move all [FLASH-SPECIFIC] parameters and settings from 'struct spi_nor' to 'struct spi_nor_flash_parameter'. 'struct spi_nor_flash_parameter' describes the hardware capabilities and associated settings of the SPI NOR flash memory. It includes legacy flash parameters and settings that can be overwritten by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 Serial Flash Discoverable Parameters (SFDP) tables. All SFDP params and settings will fit inside 'struct spi_nor_flash_parameter'. Move spi_nor_hwcaps related code to avoid forward declarations. Add a forward declaration that we can't avoid: 'struct spi_nor' will be used in 'struct spi_nor_flash_parameter'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* Merge tag 'v5.3-rc6' into spi-nor/nextTudor Ambarus2019-08-281-2/+3
|\ | | | | | | | | | | | | | | Linux 5.3-rc6 Merge back latest release candidate, to include a fix that we depend on for new development: 834de5c1aa76 ("mtd: spi-nor: Fix the disabling of write protection at init")
| * mtd: spi-nor: Fix the disabling of write protection at initTudor Ambarus2019-08-131-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_spansion_clear_sr_bp() depends on spansion_quad_enable(). While spansion_quad_enable() is selected as default when initializing the flash parameters, the nor->quad_enable() method can be overwritten later on when parsing BFPT. Select the write protection disable mechanism at spi_nor_init() time, when the nor->quad_enable() method is already known. Fixes: 191f5c2ed4b6faba ("mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Richard Weinberger <richard@nod.at>
* | mtd: spi-nor: intel-spi: Whitelist 4B read commandsAlexander Sverdlin2019-08-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports Flash chips up to 64Mbytes. D-1500 Integrated PCH documenation however has inconsistencies regarding FADDR register width and says nothing about particular commands issued to support 64Mbytes of Flash. Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and read operations work just fine after SPINOR_OP_READ_4B and SPINOR_OP_READ_FAST_4B are white-listed (currently only SPINOR_OP_READ_FAST_4B is used and only for Macronix). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: fix a memory leak bugWenwen Wang2019-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | In spi_nor_parse_4bait(), 'dwords' is allocated through kmalloc(). However, it is not deallocated in the following execution if spi_nor_read_sfdp() fails, leading to a memory leak. To fix this issue, free 'dwords' before returning the error. Fixes: 816873eaeec6 ("mtd: spi-nor: parse SFDP 4-byte Address Instruction Table") Signed-off-by: Wenwen Wang <wenwen@cs.uga.edu> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: Fix an error code in spi_nor_read_raw()Dan Carpenter2019-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | The problem is that if "ret" is negative then when we check if "ret > len", that condition is going to be true because of type promotion. So this patch re-orders the code to check for negatives first and preserve those error codes. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: Fix Cadence QSPI RCU Schedule StallThor Thayer2019-08-211-14/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current Cadence QSPI driver sometimes caused a "rcu_sched self-detected stall" while writing large files. Stall Report: '# mtd_debug write /dev/mtd1 0 48816464 blob.img [ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU [ 1815.459789] rcu: 0-....: (2099 ticks this GP) idle=8c6/1/0x40000002 softirq=6492/6492 fqs=935 [ 1815.468442] rcu: (t=2100 jiffies g=8749 q=247) <snip> (abbreviated backtrace) [ 1815.772086] [<c05a3ea0>] (cqspi_exec_flash_cmd) (cqspi_read_reg) [ 1815.786203] [<c05a5488>] (cqspi_read_reg) from (read_sr) [ 1815.803790] [<c05a0330>] (read_sr) from (spi_nor_wait_till_ready_with_timeout) [ 1815.816610] [<c05a182c>] (spi_nor_wait_till_ready_with_timeout) from (spi_nor_write+0x104/0x1d0) [ 1815.836791] [<c05a1a44>] (spi_nor_write) from (part_write+0x50/0x58) <snip> [ 1815.997961] cadence-qspi ff809000.spi: Flash command execution timed out. [ 1816.004733] error -110 reading SR file_to_flash: write, size 0x2e8e150, n 0x2e8e150 write(): Connection timed out This was caused by a tight loop in cqspi_wait_for_bit(). Fix by using readl_relaxed_poll_timeout() which sleeps 10us while polling a register. Fit onto 80 character line by truncating the bool clear parameter Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor : Remove SPI_NOR_HAS_TB flag on s25fl512sJungseung Lee2019-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Currently, the Top/Bottom protection function (SPI_NOR_HAS_TB) is implemented to fit some flashes with TB bit on SR. s25fl512s has TBPROT bit on CR1, so the TB protection is not working on it. Fix the wrong flag on s25fl512s. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake SPI serial flashMika Westerberg2019-08-201-0/+1
| | | | | | | | | | | | | | | | Intel Tiger Lake has the same SPI serial flash controller as Ice Lake. Add Tiger Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: add support for sst26wf016b memory ICEugeniy Paltsev2019-08-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for the SST sst26wf016b flash memory IC. This IC was tested with "snps,dw-apb-ssi" SPI controller. We don't test dual/quad reads however sst26wf016b flash's datasheet advertises both dual and quad reads (and support of corresponding commands) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: Add Winbond w25q256jvmAvi Fishman2019-08-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | Similar to w25q256 (besides not supporting QPI mode) but with different ID. The "JVM" suffix is in the datasheet. The datasheet indicates DUAL and QUAD are supported. https://www.winbond.com/resource-files/w25q256jv%20spi%20revi%2010232018%20plus.pdf Signed-off-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: Rework hwcaps selection for the spi-mem caseBoris Brezillon2019-08-121-36/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The spi-mem layer provides a spi_mem_supports_op() function to check whether a specific operation is supported by the controller or not. This is much more accurate than the hwcaps selection logic based on SPI_{RX,TX}_ flags. Rework the hwcaps selection logic to use spi_mem_supports_op() when nor->spimem != NULL. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: Move m25p80 code in spi-nor.cBoris Brezillon2019-08-122-28/+602
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The m25p80 driver is actually a generic wrapper around the spi-mem layer. Not only the driver name is misleading, but we'd expect such a common logic to be directly available in the core. Another reason for moving this code is that SPI NOR controller drivers should progressively be replaced by SPI controller drivers implementing the spi_mem_ops interface, and when the conversion is done, we should have a single spi-nor driver directly interfacing with the spi-mem layer. While moving the code we also fix a longstanding issue when non-DMA-able buffers are passed by the MTD layer. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | mtd: spi-nor: always use bounce buffer for register read/writesVignesh Raghavendra2019-08-121-36/+44
|/ | | | | | | | | | | | | spi-mem layer expects all buffers passed to it to be DMA'able. But spi-nor layer mostly allocates buffers on stack for reading/writing to registers and therefore are not DMA'able. Introduce bounce buffer to be used to read/write to registers. This ensures that buffer passed to spi-mem layer during register read/writes is DMA'able. With this change nor->cmd-buf is no longer used, so drop it. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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