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path: root/drivers/net/dsa/mv88e6xxx/chip.h
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* net: dsa: mv88e6xxx: Fix PHY interrupts by parameterising PHY base addressAndrew Lunn2018-05-071-0/+1
| | | | | | | | | | | | | | Most of the mv88e6xxx switches have the PHYs at address 0, 1, 2, ... The 6341 however has the PHYs at 0x10, 0x11, 0x12. Add a parameter to the info structure for this base address. Testing of 6f88284f3bd7 ("net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs") was performed on the 6341. So it works only on the 6341. Use this base information to correctly set the interrupt. Fixes: 6f88284f3bd7 ("net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Keep ATU/VTU violation statisticsAndrew Lunn2018-03-291-4/+9
| | | | | | | | | Count the numbers of various ATU and VTU violation statistics and return them as part of the ethtool -S statistics. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Add number of internal PHYsAndrew Lunn2018-03-181-0/+1
| | | | | | | | | Add to the info structure the number of internal PHYs, if they generate interrupts. Some of the older generations of switches have internal PHYs, but no interrupt registers. In this case, set the count to zero. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Get mv88e6352 SERDES statisticsAndrew Lunn2018-03-041-1/+9
| | | | | | | | | | | | | | | | | | Add support for reading the SERDES statistics of the mv88e8352, using the standard ethtool -S option. The SERDES interface can be mapped to either port 4 or 5, so only return statistics on those ports, if the SERDES interface is in use. The counters are reset on read, so need to be accumulated. Add a per port structure to hold the stats counters. The 6352 only has a single SERDES interface and so only one port will using the newly added array. However the 6390 family has as many SERDES interfaces as ports, each with statistics counters. Also, PTP has a number of counters per port which will also need accumulating. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Allow the SERDES interfaces to have statisticsAndrew Lunn2018-03-041-3/+10
| | | | | | | | | | | When gettting the number of statistics, the strings and the actual statistics, call the SERDES ops if implemented. This means the stats code needs to return the number of strings/stats they have placed into the data, so that the SERDES strings/stats can follow on. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Poll when no interrupt definedAndrew Lunn2018-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | Not all boards have the interrupt output from the switch connected to a GPIO line. In such cases, phylib has to poll the internal PHYs, rather than receive an interrupt when there is a change in the link state. phylib polls once per second, and per PHY reads around 4 words. With a switch typically having 4 internal PHYs, this means 16 MDIO transactions per second. Rather than performing this phylib level polling, have the driver poll the interrupt status register. If the status register indicates an interrupt condition processing of interrupts in the same way as if a GPIO was used. Polling 10 times a second places less load on the MDIO bus. But rather than taking on average 0.5s to detect a link change, it takes less than 0.05s. Additionally, other interrupts, such as the watchdog, ATU and VTU violations will be reported. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add rx/tx timestamping supportBrandon Streiff2018-02-141-0/+29
| | | | | | | | | | | | | | | | | | | This patch implements RX/TX timestamping support. The Marvell PTP hardware supports RX timestamping individual message types, but for simplicity we only support the EVENT receive filter since few if any clients bother with the more specific filter types. checkpatch and reverse Christmas tree changes by Andrew Lunn. Re-factor duplicated code paths and avoid IfOk anti-pattern, use the common ptp worker thread from the class layer and time stamp UDP/IPv4 frames as well as Layer-2 frame by Richard Cochran. Signed-off-by: Brandon Streiff <brandon.streiff@ni.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add support for event captureBrandon Streiff2018-02-141-0/+4
| | | | | | | | | | | | | | | | This patch adds support for configuring mv88e6xxx GPIO lines as PTP pins, so that they may be used for time stamping external events or for periodic output. Checkpatch and reverse Christmas tree fixes by Andrew Lunn Periodic output removed by Richard Cochran, until a better abstraction of a VCO is added to Linux in general. Signed-off-by: Brandon Streiff <brandon.streiff@ni.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add support for GPIO configurationBrandon Streiff2018-02-141-0/+33
| | | | | | | | | | | | | | | | | MV88E6352 and later switches support GPIO control through the "Scratch & Misc" global2 register. (Older switches do too, though with a slightly different register interface. Only the 6352-style is implemented here.) Add a new file, global2_scratch.c, for operations in the Scratch & Misc space. Additionally, add a GPIO operations structure to present an abstract view over GPIO manipulation. Reverse Christmas tree and unsigned has been replaced with unsigned int by Andrew Lunn. Signed-off-by: Brandon Streiff <brandon.streiff@ni.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: expose switch time as a PTP hardware clockBrandon Streiff2018-02-141-0/+15
| | | | | | | | | | | | | This patch adds basic support for exposing the 32-bit timestamp counter inside the mv88e6xxx switch as a ptp_clock. Adjfine implemented by Richard Cochran. Andrew Lunn: fix return value of PTP stub function. Signed-off-by: Brandon Streiff <brandon.streiff@ni.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add accessors for PTP/TAI registersBrandon Streiff2018-02-141-0/+22
| | | | | | | | | | | | | | | | | | | | This patch implements support for accessing the Precision Time Protocol and Time Application Interface registers via the AVB register interface in the Global 2 register. The register interface differs slightly between different models; older models use a 3-bit operations field, while newer models use a 2-bit field. The operations values and the special "global port" values are different between the two. This is a similar split to the differences in the "Ingress Rate" register between models, so, like in that case, we call the two variants "6352" and "6390" and create an ops structure to abstract between the two. checkpatch fixups by Andrew Lunn Signed-off-by: Brandon Streiff <brandon.streiff@ni.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Decode VTU problem interruptAndrew Lunn2018-01-141-0/+1
| | | | | | | | | When there is a problem with the VTU, an interrupt can be generated. Trap this interrupt and decode the registers to determine what the problem was, then log the error. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: Decode ATU problem interruptAndrew Lunn2018-01-141-0/+1
| | | | | | | | | When there is a problem with the ATU, an interrupt can be generated. Trap this interrupt and decode the registers to determine what the problem was, then log the error. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: remove EEE supportVivien Didelot2017-08-011-6/+0
| | | | | | | | | | | | The PHY's EEE settings are already accessed by the DSA layer through the Marvell PHY driver and there is nothing to be done for switch's MACs. Remove all EEE support from the mv88e6xxx driver and simply return 0 from the EEE ops. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add a multi_chip info flagVivien Didelot2017-07-181-52/+6
| | | | | | | | | | | | | Instead of relying on a bitmap flag, add a new multi_chip info flag to describe the presence of the indirect SMI access though the two device registers 0x0 and 0x1. All remaining capabilities and flags are now unused. Remove the mv88e6xxx_cap enum and the info flags bitmaps. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add Energy Detect opsVivien Didelot2017-07-181-14/+10
| | | | | | | | | | | | | | The 88E6352 family supports Energy Detect and has one bit for Sense and one bit for periodically transmit NLP (Energy Detect+TM). The 88E6390 family adds another bit to distinguish Auto or SW wake-up. Chips supporting EEE all have an EEE Enabled bit in the Port Status Register. This patch adds new ops for the PHY Energy Detect accesses. This also allows us to get rid of the MV88E6XXX_FLAG_EEE flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add a global2_addr info flagVivien Didelot2017-07-181-21/+6
| | | | | | | | | | | Similarly to global1_addr, add a global2_addr member in the info structure to describe the presence of the Global 2 Registers. This allows us to get rid of the MV88E6XXX_FLAG_GLOBAL2 flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add POT operationVivien Didelot2017-07-181-9/+3
| | | | | | | | | | | Add a pot_clear operation to clear the Priority Override Table and wrap its call into a mv88e6xxx_pot_setup helper. This allows us to get rid of the MV88E6XXX_FLAG_G2_POT flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add POT flag to 88E6390Vivien Didelot2017-07-181-0/+1
| | | | | | | | | The 88E6390 family clear the Priority Override Table the same way as 88E6352, thus add MV88E6XXX_FLAG_G2_POT to MV88E6XXX_FLAGS_FAMILY_6390. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: distinguish Global 2 Rsvd2CPUVivien Didelot2017-07-181-17/+0
| | | | | | | | | | | | | | | | | The 88E6185 family only has one 16-bit register to mark the 16 802.1D reserved multicast addresses in the range of 01:80:C2:00:00:0x as MGMT. The 88E6352 family also has one 16-bit register to mark the 16 GARP reserved multicast addresses in the range of 01:80:C2:00:00:2x as MGMT. Split the existing mv88e6095 prefixed mgmt_rsvd2cpu operation into two distinct mv88e6185 and mv88e6352 prefixed operations, and wrap its call into a mv88e6xxx_rsvd2cpu_setup helper. This allows us to also get rid of the MV88E6XXX_CAP_G2_MGMT_EN_* flags. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add number of Global 2 IRQsVivien Didelot2017-07-181-8/+1
| | | | | | | | | | | | | | | Similarly to g1_irqs, add a g2_irqs member to the info structure to indicates the presence of the Global 2 Interrupt Source and Mask registers. At the same time, provide helpers and document the registers since they differ a bit between 88E6352 and 88E6390 families. This allows us to get rid of the MV88E6XXX_FLAG_G2_INT flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: remove 88E6185 G2 interruptVivien Didelot2017-07-181-1/+0
| | | | | | | | | The 88E6185 family has no Global 2 Interrupt Source or Mask registers. Remove the MV88E6XXX_FLAG_G2_INT from MV88E6XXX_FLAGS_FAMILY_6185. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: remove unused capabilitiesVivien Didelot2017-07-181-26/+3
| | | | | | | | | Remove the forgotten capabilities and related flags from previous cleanups. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add irl_init_all opVivien Didelot2017-06-201-16/+3
| | | | | | | | | | | | | | | | | Some Marvell chips have an Ingress Rate Limit unit. But the command values slightly differs between models: 88E6352 use 3-bit for operations while 88E6390 use different 2-bit operations. This commit kills the IRL flags in favor of a new operation implementing the "Init all resources to the initial state" operation. This fixes the operation of 88E6390 family where 0x1000 means Read the selected resource 0, register 0 on port 16, instead of init all. A mv88e6xxx_irl_setup helper is added to wrap the operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: prefix Global VTU macrosVivien Didelot2017-06-151-2/+2
| | | | | | | | Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rework jumbo size operationVivien Didelot2017-06-091-1/+2
| | | | | | | | | | | | | | | | Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rework pause limit operationVivien Didelot2017-06-091-1/+2
| | | | | | | | | | | | | | | | | All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in a 16-bit register. New ones have an indirect table using 8-bit data. The mv88e6xxx library functions (such as in port.c) must not contain driver logic, but only generic helpers. This patch changes the port_pause_config operation for port_pause_limit taking two u8 arguments for input and output limits. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: do not prefix ops with g1Vivien Didelot2017-06-091-2/+2
| | | | | | | | | | | The mv88e6xxx_ops describe functionalities, regardless their locations (which can be Global1, Global2, or whatever register set.) Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port and set_egress_port. No functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add egress mode enumerationVivien Didelot2017-06-091-0/+7
| | | | | | | | | As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: move the Global 2 macrosVivien Didelot2017-06-041-101/+0
| | | | | | | | Move the GLOBAL2_* macros where they belong, in the related global2.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: move the Global 1 macrosVivien Didelot2017-06-041-141/+0
| | | | | | | | Move the GLOBAL_* macros where they belong, in the related global1.h header. Include it in global2.c which uses GLOBAL_STATUS_IRQ_DEVICE. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: move the Port macrosVivien Didelot2017-06-041-160/+0
| | | | | | | Move the PORT_* macros where they belong, in the related port.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: move PHY macrosVivien Didelot2017-06-041-4/+0
| | | | | | | Move the PHY_* macros where they belong, in the related phy.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rename chip headerVivien Didelot2017-06-041-0/+928
The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. At the same time, ensure that relative header inclusions are separated by a newline and sorted alphabetically. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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