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* net: dsa: sja1105: Fix sleeping while atomic in .port_hwtstamp_setVladimir Oltean2019-10-021-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently this stack trace can be seen with CONFIG_DEBUG_ATOMIC_SLEEP=y: [ 41.568348] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:909 [ 41.576757] in_atomic(): 1, irqs_disabled(): 0, pid: 208, name: ptp4l [ 41.583212] INFO: lockdep is turned off. [ 41.587123] CPU: 1 PID: 208 Comm: ptp4l Not tainted 5.3.0-rc6-01445-ge950f2d4bc7f-dirty #1827 [ 41.599873] [<c0313d7c>] (unwind_backtrace) from [<c030e13c>] (show_stack+0x10/0x14) [ 41.607584] [<c030e13c>] (show_stack) from [<c1212d50>] (dump_stack+0xd4/0x100) [ 41.614863] [<c1212d50>] (dump_stack) from [<c037dfc8>] (___might_sleep+0x1c8/0x2b4) [ 41.622574] [<c037dfc8>] (___might_sleep) from [<c122ea90>] (__mutex_lock+0x48/0xab8) [ 41.630368] [<c122ea90>] (__mutex_lock) from [<c122f51c>] (mutex_lock_nested+0x1c/0x24) [ 41.638340] [<c122f51c>] (mutex_lock_nested) from [<c0c6fe08>] (sja1105_static_config_reload+0x30/0x27c) [ 41.647779] [<c0c6fe08>] (sja1105_static_config_reload) from [<c0c7015c>] (sja1105_hwtstamp_set+0x108/0x1cc) [ 41.657562] [<c0c7015c>] (sja1105_hwtstamp_set) from [<c0feb650>] (dev_ifsioc+0x18c/0x330) [ 41.665788] [<c0feb650>] (dev_ifsioc) from [<c0febbd8>] (dev_ioctl+0x320/0x6e8) [ 41.673064] [<c0febbd8>] (dev_ioctl) from [<c0f8b1f4>] (sock_ioctl+0x334/0x5e8) [ 41.680340] [<c0f8b1f4>] (sock_ioctl) from [<c05404a8>] (do_vfs_ioctl+0xb0/0xa10) [ 41.687789] [<c05404a8>] (do_vfs_ioctl) from [<c0540e3c>] (ksys_ioctl+0x34/0x58) [ 41.695151] [<c0540e3c>] (ksys_ioctl) from [<c0301000>] (ret_fast_syscall+0x0/0x28) [ 41.702768] Exception stack(0xe8495fa8 to 0xe8495ff0) [ 41.707796] 5fa0: beff4a8c 00000001 00000011 000089b0 beff4a8c beff4a80 [ 41.715933] 5fc0: beff4a8c 00000001 0000000c 00000036 b6fa98c8 004e19c1 00000001 00000000 [ 41.724069] 5fe0: 004dcedc beff4a6c 004c0738 b6e7af4c [ 41.729860] BUG: scheduling while atomic: ptp4l/208/0x00000002 [ 41.735682] INFO: lockdep is turned off. Enabling RX timestamping will logically disturb the fastpath (processing of meta frames). Replace bool hwts_rx_en with a bit that is checked atomically from the fastpath and temporarily unset from the sleepable context during a change of the RX timestamping process (a destructive operation anyways, requires switch reset). If found unset, the fastpath (net/dsa/tag_sja1105.c) will just drop any received meta frame and not take the meta_lock at all. Fixes: a602afd200f5 ("net: dsa: sja1105: Expose PTP timestamping ioctls to userspace") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: sja1105: Initialize the meta_lockVladimir Oltean2019-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, with CONFIG_DEBUG_SPINLOCK=y, this stack trace gets printed when enabling RX timestamping and receiving a PTP frame: [ 318.537078] INFO: trying to register non-static key. [ 318.542040] the code is fine but needs lockdep annotation. [ 318.547500] turning off the locking correctness validator. [ 318.552972] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.3.0-13257-g0825b0669811-dirty #1962 [ 318.561283] Hardware name: Freescale LS1021A [ 318.565566] [<c03144bc>] (unwind_backtrace) from [<c030e164>] (show_stack+0x10/0x14) [ 318.573289] [<c030e164>] (show_stack) from [<c11b9f50>] (dump_stack+0xd4/0x100) [ 318.580579] [<c11b9f50>] (dump_stack) from [<c03b9b40>] (register_lock_class+0x728/0x734) [ 318.588731] [<c03b9b40>] (register_lock_class) from [<c03b60c4>] (__lock_acquire+0x78/0x25cc) [ 318.597227] [<c03b60c4>] (__lock_acquire) from [<c03b8ef8>] (lock_acquire+0xd8/0x234) [ 318.605033] [<c03b8ef8>] (lock_acquire) from [<c11db934>] (_raw_spin_lock+0x44/0x54) [ 318.612755] [<c11db934>] (_raw_spin_lock) from [<c1164370>] (sja1105_rcv+0x1f8/0x4e8) [ 318.620561] [<c1164370>] (sja1105_rcv) from [<c115d7cc>] (dsa_switch_rcv+0x80/0x204) [ 318.628283] [<c115d7cc>] (dsa_switch_rcv) from [<c0f58c80>] (__netif_receive_skb_one_core+0x50/0x6c) [ 318.637386] [<c0f58c80>] (__netif_receive_skb_one_core) from [<c0f58f04>] (netif_receive_skb_internal+0xac/0x264) [ 318.647611] [<c0f58f04>] (netif_receive_skb_internal) from [<c0f59e98>] (napi_gro_receive+0x1d8/0x338) [ 318.656887] [<c0f59e98>] (napi_gro_receive) from [<c0c298a4>] (gfar_clean_rx_ring+0x328/0x724) [ 318.665472] [<c0c298a4>] (gfar_clean_rx_ring) from [<c0c29e60>] (gfar_poll_rx_sq+0x34/0x94) [ 318.673795] [<c0c29e60>] (gfar_poll_rx_sq) from [<c0f5b40c>] (net_rx_action+0x128/0x4f8) [ 318.681860] [<c0f5b40c>] (net_rx_action) from [<c03022f0>] (__do_softirq+0x148/0x5ac) [ 318.689666] [<c03022f0>] (__do_softirq) from [<c0355af4>] (irq_exit+0x160/0x170) [ 318.697040] [<c0355af4>] (irq_exit) from [<c03c6818>] (__handle_domain_irq+0x60/0xb4) [ 318.704847] [<c03c6818>] (__handle_domain_irq) from [<c07e9440>] (gic_handle_irq+0x58/0x9c) [ 318.713172] [<c07e9440>] (gic_handle_irq) from [<c0301a70>] (__irq_svc+0x70/0x98) [ 318.720622] Exception stack(0xc2001f18 to 0xc2001f60) [ 318.725656] 1f00: 00000001 00000006 [ 318.733805] 1f20: 00000000 c20165c0 ffffe000 c2010cac c2010cf4 00000001 00000000 c2010c88 [ 318.741955] 1f40: c1f7a5a8 00000000 00000000 c2001f68 c03ba140 c030a288 200e0013 ffffffff [ 318.750110] [<c0301a70>] (__irq_svc) from [<c030a288>] (arch_cpu_idle+0x24/0x3c) [ 318.757486] [<c030a288>] (arch_cpu_idle) from [<c038a480>] (do_idle+0x1b8/0x2a4) [ 318.764859] [<c038a480>] (do_idle) from [<c038a94c>] (cpu_startup_entry+0x18/0x1c) [ 318.772407] [<c038a94c>] (cpu_startup_entry) from [<c1e00f10>] (start_kernel+0x4cc/0x4fc) Fixes: 844d7edc6a34 ("net: dsa: sja1105: Add a global sja1105_tagger_data structure") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: rtl8366: Check VLAN ID and not portsLinus Walleij2019-10-021-4/+7
| | | | | | | | | | | | | | | | | | There has been some confusion between the port number and the VLAN ID in this driver. What we need to check for validity is the VLAN ID, nothing else. The current confusion came from assigning a few default VLANs for default routing and we need to rewrite that properly. Instead of checking if the port number is a valid VLAN ID, check the actual VLAN IDs passed in to the callback one by one as expected. Fixes: d8652956cf37 ("net: dsa: realtek-smi: Add Realtek SMI driver") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: rtl8366rb: add missing of_node_put after calling of_get_child_by_nameWen Yang2019-10-011-6/+10
| | | | | | | | | | | | | | | | | | | of_node_put needs to be called when the device node which is got from of_get_child_by_name finished using. irq_domain_add_linear() also calls of_node_get() to increase refcount, so irq_domain will not be affected when it is released. Fixes: d8652956cf37 ("net: dsa: realtek-smi: Add Realtek SMI driver") Signed-off-by: Wen Yang <wenyang@linux.alibaba.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Vivien Didelot <vivien.didelot@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: sja1105: Prevent leaking memoryNavid Emamdoost2019-09-301-2/+4
| | | | | | | | | | | | In sja1105_static_config_upload, in two cases memory is leaked: when static_config_buf_prepare_for_upload fails and when sja1105_inhibit_tx fails. In both cases config_buf should be released. Fixes: 8aa9ebccae87 ("net: dsa: Introduce driver for NXP SJA1105 5-port L2 switch") Fixes: 1a4c69406cc1 ("net: dsa: sja1105: Prevent PHY jabbering during switch reset") Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: sja1105: Ensure PTP time for rxtstamp reconstruction is not in the ↵Vladimir Oltean2019-09-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | past Sometimes the PTP synchronization on the switch 'jumps': ptp4l[11241.155]: rms 8 max 16 freq -21732 +/- 11 delay 742 +/- 0 ptp4l[11243.157]: rms 7 max 17 freq -21731 +/- 10 delay 744 +/- 0 ptp4l[11245.160]: rms 33592410 max 134217731 freq +192422 +/- 8530253 delay 743 +/- 0 ptp4l[11247.163]: rms 811631 max 964131 freq +10326 +/- 557785 delay 743 +/- 0 ptp4l[11249.166]: rms 261936 max 533876 freq -304323 +/- 126371 delay 744 +/- 0 ptp4l[11251.169]: rms 48700 max 57740 freq -20218 +/- 30532 delay 744 +/- 0 ptp4l[11253.171]: rms 14570 max 30163 freq -5568 +/- 7563 delay 742 +/- 0 ptp4l[11255.174]: rms 2914 max 3440 freq -22001 +/- 1667 delay 744 +/- 1 ptp4l[11257.177]: rms 811 max 1710 freq -22653 +/- 451 delay 744 +/- 1 ptp4l[11259.180]: rms 177 max 218 freq -21695 +/- 89 delay 741 +/- 0 ptp4l[11261.182]: rms 45 max 92 freq -21677 +/- 32 delay 742 +/- 0 ptp4l[11263.186]: rms 14 max 32 freq -21733 +/- 11 delay 742 +/- 0 ptp4l[11265.188]: rms 9 max 14 freq -21725 +/- 12 delay 742 +/- 0 ptp4l[11267.191]: rms 9 max 16 freq -21727 +/- 13 delay 742 +/- 0 ptp4l[11269.194]: rms 6 max 15 freq -21726 +/- 9 delay 743 +/- 0 ptp4l[11271.197]: rms 8 max 15 freq -21728 +/- 11 delay 743 +/- 0 ptp4l[11273.200]: rms 6 max 12 freq -21727 +/- 8 delay 743 +/- 0 ptp4l[11275.202]: rms 9 max 17 freq -21720 +/- 11 delay 742 +/- 0 ptp4l[11277.205]: rms 9 max 18 freq -21725 +/- 12 delay 742 +/- 0 Background: the switch only offers partial RX timestamps (24 bits) and it is up to the driver to read the PTP clock to fill those timestamps up to 64 bits. But the PTP clock readout needs to happen quickly enough (in 0.135 seconds, in fact), otherwise the PTP clock will wrap around 24 bits, condition which cannot be detected. Looking at the 'max 134217731' value on output line 3, one can see that in hex it is 0x8000003. Because the PTP clock resolution is 8 ns, that means 0x1000000 in ticks, which is exactly 2^24. So indeed this is a PTP clock wraparound, but the reason might be surprising. What is going on is that sja1105_tstamp_reconstruct(priv, now, ts) expects a "now" time that is later than the "ts" was snapshotted at. This, of course, is obvious: we read the PTP time _after_ the partial RX timestamp was received. However, the workqueue is processing frames from a skb queue and reuses the same PTP time, read once at the beginning. Normally the skb queue only contains one frame and all goes well. But when the skb queue contains two frames, the second frame that gets dequeued might have been partially timestamped by the RX MAC _after_ we had read our PTP time initially. The code was originally like that due to concerns that SPI access for PTP time readout is a slow process, and we are time-constrained anyway (aka: premature optimization). But some timing analysis reveals that the time spent until the RX timestamp is completely reconstructed is 1 order of magnitude lower than the 0.135 s deadline even under worst-case conditions. So we can afford to read the PTP time for each frame in the RX timestamping queue, which of course ensures that the full PTP time is in the partial timestamp's future. Fixes: f3097be21bf1 ("net: dsa: sja1105: Add a state machine for RX timestamping") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: qca8k: Use up to 7 ports for all operationsMichal Vokáč2019-09-301-2/+2
| | | | | | | | | | | | | | | | | | The QCA8K family supports up to 7 ports. So use the existing QCA8K_NUM_PORTS define to allocate the switch structure and limit all operations with the switch ports. This was not an issue until commit 0394a63acfe2 ("net: dsa: enable and disable all ports") disabled all unused ports. Since the unused ports 7-11 are outside of the correct register range on this switch some registers were rewritten with invalid content. Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family") Fixes: a0c02161ecfc ("net: dsa: variable number of ports") Fixes: 0394a63acfe2 ("net: dsa: enable and disable all ports") Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: microchip: Always set regmap stride to 1Marek Vasut2019-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The regmap stride is set to 1 for regmap describing 8bit registers already. However, for 16/32/64bit registers, the stride is 2/4/8 respectively. This is not correct, as the switch protocol supports unaligned register reads and writes and the KSZ87xx even uses such unaligned register accesses to read e.g. MIB counter. This patch fixes MIB counter access on KSZ87xx. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: David S. Miller <davem@davemloft.net> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: George McCollister <george.mccollister@gmail.com> Cc: Tristram Ha <Tristram.Ha@microchip.com> Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Cc: Woojung Huh <woojung.huh@microchip.com> Fixes: 46558d601cb6 ("net: dsa: microchip: Initial SPI regmap support") Fixes: 255b59ad0db2 ("net: dsa: microchip: Factor out regmap config generation into common header") Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: qca8k: Fix port enable for CPU portAndrew Lunn2019-09-271-0/+3
| | | | | | | | | | | | The CPU port does not have a PHY connected to it. So calling phy_support_asym_pause() results in an Opps. As with other DSA drivers, add a guard that the port is a user port. Reported-by: Michal Vokáč <michal.vokac@ysoft.com> Fixes: 0394a63acfe2 ("net: dsa: enable and disable all ports") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: Use the correct style for SPDX License IdentifierNishad Kamdar2019-09-221-1/+1
| | | | | | | | | | | | | | | | | This patch corrects the SPDX License Identifier style in header file for Distributed Switch Architecture drivers. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
* net: dsa: b53: Use the correct style for SPDX License IdentifierNishad Kamdar2019-09-221-2/+2
| | | | | | | | | | | | | | | | | This patch corrects the SPDX License Identifier style in header file for Broadcom BCM53xx managed switch driver. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
* net: dsa: sja1105: Add dependency for NET_DSA_SJA1105_TASMao Wenan2019-09-211-0/+1
| | | | | | | | | | | | | | | | | | If CONFIG_NET_DSA_SJA1105_TAS=y and CONFIG_NET_SCH_TAPRIO=n, below error can be found: drivers/net/dsa/sja1105/sja1105_tas.o: In function `sja1105_setup_tc_taprio': sja1105_tas.c:(.text+0x318): undefined reference to `taprio_offload_free' sja1105_tas.c:(.text+0x590): undefined reference to `taprio_offload_get' drivers/net/dsa/sja1105/sja1105_tas.o: In function `sja1105_tas_teardown': sja1105_tas.c:(.text+0x610): undefined reference to `taprio_offload_free' make: *** [vmlinux] Error 1 sja1105_tas needs tc-taprio, so this patch add the dependency for it. Fixes: 317ab5b86c8e ("net: dsa: sja1105: Configure the Time-Aware Scheduler via tc-taprio offload") Signed-off-by: Mao Wenan <maowenan@huawei.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
* net: dsa: sja1105: Configure the Time-Aware Scheduler via tc-taprio offloadVladimir Oltean2019-09-166-1/+500
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This qdisc offload is the closest thing to what the SJA1105 supports in hardware for time-based egress shaping. The switch core really is built around SAE AS6802/TTEthernet (a TTTech standard) but can be made to operate similarly to IEEE 802.1Qbv with some constraints: - The gate control list is a global list for all ports. There are 8 execution threads that iterate through this global list in parallel. I don't know why 8, there are only 4 front-panel ports. - Care must be taken by the user to make sure that two execution threads never get to execute a GCL entry simultaneously. I created a O(n^4) checker for this hardware limitation, prior to accepting a taprio offload configuration as valid. - The spec says that if a GCL entry's interval is shorter than the frame length, you shouldn't send it (and end up in head-of-line blocking). Well, this switch does anyway. - The switch has no concept of ADMIN and OPER configurations. Because it's so simple, the TAS settings are loaded through the static config tables interface, so there isn't even place for any discussion about 'graceful switchover between ADMIN and OPER'. You just reset the switch and upload a new OPER config. - The switch accepts multiple time sources for the gate events. Right now I am using the standalone clock source as opposed to PTP. So the base time parameter doesn't really do much. Support for the PTP clock source will be added in a future series. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: sja1105: Advertise the 8 TX queuesVladimir Oltean2019-09-161-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for the tc-taprio offload (and potentially for other future offloads such as tc-mqprio). Instead of looking directly at skb->priority during xmit, let's get the netdev queue and the queue-to-traffic-class mapping, and put the resulting traffic class into the dsa_8021q PCP field. The switch is configured with a 1-to-1 PCP-to-ingress-queue-to-egress-queue mapping (see vlan_pmap in sja1105_main.c), so the effect is that we can inject into a front-panel's egress traffic class through VLAN tagging from Linux, completely transparently. Unfortunately the switch doesn't look at the VLAN PCP in the case of management traffic to/from the CPU (link-local frames at 01-80-C2-xx-xx-xx or 01-1B-19-xx-xx-xx) so we can't alter the transmission queue of this type of traffic on a frame-by-frame basis. It is only selected through the "hostprio" setting which ATM is harcoded in the driver to 7. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: sja1105: Add static config tables for schedulingVladimir Oltean2019-09-163-1/+222
| | | | | | | | In order to support tc-taprio offload, the TTEthernet egress scheduling core registers must be made visible through the static interface. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: b53: Add support for port_egress_floods callbackFlorian Fainelli2019-09-162-0/+35
| | | | | | | | | Add support for configuring the per-port egress flooding control for both Unicast and Multicast traffic. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: microchip: add ksz9567 to ksz9477 driverGeorge McCollister2019-09-123-0/+11
| | | | | | | | | | | | Add support for the KSZ9567 7-Port Gigabit Ethernet Switch to the ksz9477 driver. The KSZ9567 supports both SPI and I2C. Oddly the ksz9567 is already in the device tree binding documentation. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: microchip: add KSZ9477 I2C driverTristram Ha2019-09-124-0/+110
| | | | | | | | | | Add KSZ9477 I2C driver support. The code ksz9477.c and ksz_common.c are used together to generate the I2C driver. Signed-off-by: Tristram Ha <Tristram.Ha@microchip.com> [george.mccollister@gmail.com: bring up to date, use ksz_common regmap macros] Signed-off-by: George McCollister <george.mccollister@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add RXNFC supportVivien Didelot2019-09-102-0/+226
| | | | | | | | | | | | | Implement the .get_rxnfc and .set_rxnfc DSA operations to configure a port's Layer 2 Policy Control List (PCL) via ethtool. Currently only dropping frames based on MAC Destination or Source Address (including the option VLAN parameter) is supported. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: introduce .port_set_policyVivien Didelot2019-09-104-1/+121
| | | | | | | | | | | Introduce a new .port_set_policy operation to configure a port's Policy Control List, based on mapping such as DA, SA, Etype and so on. Models similar to 88E6352 and 88E6390 are supported at the moment. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: complete ATU state definitionsVivien Didelot2019-09-103-27/+41
| | | | | | | | | | | | | Marvell has different values for the state of a MAC address, depending on its multicast bit. This patch completes the definitions for these states. At the same time, use 0 which is intuitive enough and simplifies the code a bit, instead of the UC or MC unused value. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mt7530: Add support for port 5René van Dorst2019-09-052-6/+168
| | | | | | | | | | | | | | | Adding support for port 5. Port 5 can muxed/interface to: - internal 5th GMAC of the switch; can be used as 2nd CPU port or as extra port with an external phy for a 6th ethernet port. - internal PHY of port 0 or 4; Used in most applications so that port 0 or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC. Signed-off-by: René van Dorst <opensource@vdorst.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mt7530: Convert to PHYLINK APIRené van Dorst2019-09-052-87/+211
| | | | | | | | | Convert mt7530 to PHYLINK API Signed-off-by: René van Dorst <opensource@vdorst.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller2019-09-022-0/+2
|\ | | | | | | | | | | | | r8152 conflicts are the NAPI fixes in 'net' overlapping with some tasklet stuff in net-next Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: microchip: add KSZ8563 compatibility stringRazvan Stefanescu2019-08-311-0/+1
| | | | | | | | | | | | | | It is a 3-Port 10/100 Ethernet Switch with 1588v2 PTP. Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: microchip: fill regmap_config nameGeorge McCollister2019-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | Use the register value width as the regmap_config name to prevent the following error when the second and third regmap_configs are initialized. "debugfs: Directory '${bus-id}' with parent 'regmap' already present!" Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: centralize SERDES IRQ handlingVivien Didelot2019-09-014-175/+69
| | | | | | | | | | | | | | | | | | | | | | | | The .serdes_irq_setup are all following the same steps: get the SERDES lane, get the IRQ mapping, request the IRQ, then enable it. So do the .serdes_irq_free implementations: get the SERDES lane, disable the IRQ, then free it. This patch removes these operations in favor of generic functions. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: introduce .serdes_irq_statusVivien Didelot2019-09-014-21/+64
| | | | | | | | | | | | | | | | Introduce a new .serdes_irq_status operation to prepare the abstraction of IRQ thread from the SERDES IRQ setup code. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: introduce .serdes_irq_enableVivien Didelot2019-09-015-50/+66
| | | | | | | | | | | | | | | | Introduce a new .serdes_irq_enable operation to prepare the abstraction of IRQ enabling from the SERDES IRQ setup code. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: pass lane to .serdes_powerVivien Didelot2019-09-015-27/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the first step of all .serdes_power implementations is getting the lane mapping. Since we have an operation for that, call it in the wrapper and pass the lane down to the .serdes_power operation. This also allows to avoid querying the SERDES lane twice in mv88e6xxx_port_set_cmode. At the same time provide mv88e6xxx_serdes_power_{up,down} helpers and prefer up/down instead of on/off as in the documentation. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: merge mv88e6352_serdes_power_setVivien Didelot2019-09-011-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | The mv88e6352_serdes_power_set helper is only used at one place, in mv88e6352_serdes_power. Keep it simple and merge the two functions together. Use mv88e6xxx_serdes_get_lane instead of mv88e6352_port_has_serdes to avoid moving code. No functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: implement mv88e6352_serdes_get_laneVivien Didelot2019-09-013-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Even though 88E6352 has no dedicated lane for SERDES interfaces, it uses a similar code as the other .serdes_get_lane implementations to check the port's CMODE and ensure that SERDES operations are doable. For consistency, implement mv88e6352_serdes_get_lane for the 88E6352 and similar switches which simply returns an unused 0xff lane address. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: simplify .serdes_get_laneVivien Didelot2019-09-014-122/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the mapping between a SERDES interface and its lane is static, we don't need to stick with negative error codes actually and we can simply return 0 if there is no lane, just like the IRQ mapping. This way we can keep a simple and intuitive API using unsigned lane numbers while simplifying the implementations with single return statements. Last but not least, fix the reverse chrismas tree in mv88e6390x_serdes_get_lane. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: introduce .serdes_irq_mappingVivien Didelot2019-09-014-6/+45
| | | | | | | | | | | | | | | | Introduce a new .serdes_irq_mapping operation to prepare the abstraction of IRQ mapping from the SERDES IRQ setup code. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: fix SERDES IRQ mappingVivien Didelot2019-09-012-11/+5
| | | | | | | | | | | | | | | | | | The current mv88e6xxx SERDES code checks for negative error code from irq_find_mapping, while this function returns an unsigned integer. This patch removes this dead code and simply returns 0 is no IRQ is found. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: check errors in mv88e6352_serdes_irq_linkVivien Didelot2019-09-011-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | The mv88e6352_serdes_irq_link helper is not checking for any error that may occur during hardware accesses. Worst, the "up" boolean is set from the potentially unused "status" variable, if read operations failed. As done in mv88e6390_serdes_irq_link_sgmii, return right away and do not call dsa_port_phylink_mac_change if an error occurred. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: fix freeing unused SERDES IRQVivien Didelot2019-08-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now mv88e6xxx does not enable its ports at setup itself and let the DSA core handle this, unused ports are disabled without being powered on first. While that is expected, the SERDES powering code was assuming that a port was already set up before powering it down, resulting in freeing an unused IRQ. The patch fixes this assumption. Fixes: b759f528ca3d ("net: dsa: mv88e6xxx: enable SERDES after setup") Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Marek Behún <marek.behun@nic.cz> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: keep CMODE writable code privateVivien Didelot2019-08-294-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up patch for commit 7a3007d22e8d ("net: dsa: mv88e6xxx: fully support SERDES on Topaz family"). Since .port_set_cmode is only called from mv88e6xxx_port_setup_mac and mv88e6xxx_phylink_mac_config, it is fine to keep this "make writable" code private to the mv88e6341_port_set_cmode implementation, instead of adding yet another operation to the switch info structure. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: get serdes lane after lockVivien Didelot2019-08-291-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up patch for commit 17deaf5cb37a ("net: dsa: mv88e6xxx: create serdes_get_lane chip operation"). The .serdes_get_lane implementations access the CMODE of a port, even though it is cached at the moment, it is safer to call them after the mutex is locked, not before. At the same time, check for an eventual error and return IRQ_DONE, instead of blindly ignoring it. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: fully support SERDES on Topaz familyMarek Behún2019-08-274-6/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we support SERDES on the Topaz family in a limited way: no IRQs and the cmode is not writable, thus the mode is determined by strapping pins. Marvell's examples though show how to make cmode writable on port 5 and support SGMII autonegotiation. It is done by writing hidden registers, for which we already have code. This patch adds support for making the cmode for the SERDES port writable on the Topaz family, via a new chip operation, .port_set_cmode_writable, which is called from mv88e6xxx_port_setup_mac just before .port_set_cmode. SERDES IRQs are also enabled for Topaz. Tested on Turris Mox. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: rename port cmode macroMarek Behún2019-08-273-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | This is a cosmetic update. We are removing the last underscore from macros MV88E6XXX_PORT_STS_CMODE_100BASE_X and MV88E6XXX_PORT_STS_CMODE_1000BASE_X. The 2500base-x version does not have that underscore. Also PHY_INTERFACE_MODE_ macros do not have it there. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: simplify SERDES code for Topaz and PeridotMarek Behún2019-08-274-92/+42
| | | | | | | | | | | | | | | | | | | | | | | | By adding an additional serdes_get_lane implementation (for Topaz), we can merge the implementations of other SERDES functions (powering and IRQs). We can skip checking port numbers, since the serdes_get_lane() methods inform if there is no lane on a port or if the lane cannot be used for given cmode. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: create serdes_get_lane chip operationMarek Behún2019-08-275-96/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a serdes_get_lane() method in the mv88e6xxx operations structure. Use it instead of calling the different implementations. Also change the methods so that their return value is used only for error. The lane number is put into a place referred to by a pointer given as argument. If the port does not have a lane, return -ENODEV. Lanes are phy addresses, so use u8 as their type. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: update code operating on hidden registersMarek Behún2019-08-274-64/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the functions operating on the hidden debug registers into it's own file, port_hidden.c. The functions prefix is renamed from mv88e6390_hidden_ to mv88e6xxx_port_hidden_, to be consistent with the rest of this driver. The macros are prefixed with MV88E6XXX_ prefix, and are changed not to use the BIT() macro nor bit shifts, since the rest of the port.h file does not use it. We also add the support for setting the Block Address field when operating hidden registers. Marvell's mdio examples for SERDES settings on Topaz use Block Address 0x7 when reading/writing hidden registers, and although the specification says that block must be set to 0xf, those settings are reachable only with Block Address 0x7. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: support 2500base-x in SGMII IRQ handlerMarek Behún2019-08-271-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv88e6390_serdes_irq_link_sgmii IRQ handler reads the SERDES PHY status register to determine speed, among other things. If cmode of the port is set to 2500base-x, though, the PHY still reports 1000 Mbps (the PHY register itself does not differentiate between 1000 Mbps and 2500 Mbps - it thinks it is running at 1000 Mbps, although clock is 2.5x faster). Look at the cmode and set SPEED_2500 if cmode is set to 2500base-x. Also tell mv88e6xxx_port_setup_mac the PHY interface mode corresponding to current cmode in terms of phy_interface_t. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: sja1105: Clear VLAN filtering offload netdev featureVladimir Oltean2019-08-271-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The switch barely supports traffic I/O, and it does that by repurposing VLANs when there is no bridge that is taking control of them. Letting DSA declare this netdev feature as supported (see dsa_slave_create) would mean that VLAN sub-interfaces created on sja1105 switch ports will be hardware offloaded. That means that net/8021q/vlan_core.c would install the VLAN into the filter tables of the switch, potentially interfering with the tag_8021q VLANs. We need to prevent that from happening and not let the 8021q core offload VLANs to the switch hardware tables. In vlan_filtering=0 modes of operation, the switch ports can pass through VLAN-tagged frames with no problem. Suggested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller2019-08-271-2/+8
|\| | | | | | | | | | | | | Minor conflict in r8169, bug fix had two versions in net and net-next, take the net-next hunks. Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: dsa: bcm_sf2: Do not configure PHYLINK on CPU portFlorian Fainelli2019-08-211-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SF2 binding does not specify that the CPU port should have properties mandatory for successfully instantiating a PHYLINK object. As such, there will be missing properties (including fixed-link) and when attempting to validate and later configure link modes, we will have an incorrect set of parameters (interface, speed, duplex). Simply prevent the CPU port from being configured through PHYLINK since bcm_sf2_imp_setup() takes care of that already. Fixes: 0e27921816ad ("net: dsa: Use PHYLINK for the CPU/DSA ports") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: wrap SERDES IRQ in power functionVivien Didelot2019-08-201-13/+19
| | | | | | | | | | | | | | | | Now that mv88e6xxx_serdes_power is only called after driver setup, we can wrap the SERDES IRQ code directly within it for clarity. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: enable SERDES after setupVivien Didelot2019-08-201-31/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | SERDES is powered on for CPU and DSA ports and powered down for unused ports at setup time. But now that DSA calls mv88e6xxx_port_enable and mv88e6xxx_port_disable for all ports, the SERDES power can now be handled after setup inconditionally for all ports. Using the port enable and disable callbacks also have the benefit to handle the SERDES IRQ for non user ports as well. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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