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* Merge branch 'pci/spdx' into nextBjorn Helgaas2018-02-0120-91/+21
|\ | | | | | | | | | | | | | | | | * pci/spdx: PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate PCI: Add SPDX GPL-2.0 when no license was specified
| * PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateBjorn Helgaas2018-01-2819-91/+19
| | | | | | | | | | | | | | | | | | | | | | Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * PCI: Add SPDX GPL-2.0 when no license was specifiedBjorn Helgaas2018-01-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") added SPDX GPL-2.0 to several PCI files that previously contained no license information. Add SPDX GPL-2.0 to all other PCI files that did not contain any license information and hence were under the default GPL version 2 license of the kernel. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | Merge remote-tracking branch 'lorenzo/pci/keystone' into nextBjorn Helgaas2018-02-011-1/+4
|\ \ | | | | | | | | | | | | * lorenzo/pci/keystone: PCI: keystone: Fix interrupt-controller-node lookup
| * | PCI: keystone: Fix interrupt-controller-node lookupJohan Hovold2017-12-191-1/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix child-node lookup during initialisation which was using the wrong OF-helper and ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent pci node could end up being prematurely freed as of_find_node_by_name() drops a reference to its first argument. Any matching child interrupt-controller node was also leaked. Fixes: 0c4ffcfe1fbc ("PCI: keystone: Add TI Keystone PCIe driver") Cc: stable <stable@vger.kernel.org> # 3.18 Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Johan Hovold <johan@kernel.org> [lorenzo.pieralisi@arm.com: updated commit subject] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge remote-tracking branch 'lorenzo/pci/endpoint' into nextBjorn Helgaas2018-02-012-19/+36
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * lorenzo/pci/endpoint: PCI: endpoint: Use EPC's device in dma_alloc_coherent()/dma_free_coherent() PCI: designware-ep: Fix ->get_msi() to check MSI_EN bit PCI: endpoint: Fix find_first_zero_bit() usage PCI: endpoint: Populate func_no before calling pci_epc_add_epf() PCI: designware-ep: Fix find_first_zero_bit() usage
| * | PCI: designware-ep: Fix ->get_msi() to check MSI_EN bitKishon Vijay Abraham I2017-12-192-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ->get_msi() now checks MSI_EN bit in the MSI CAPABILITY register to find whether the host supports MSI instead of using the MSI ADDRESS in the MSI CAPABILITY register. This fixes the issue with the following sequence 'modprobe pci_endpoint_test' enables MSI 'rmmod pci_endpoint_test' disables MSI but MSI address (in EP's capability register) has a valid value 'modprobe pci_endpoint_test no_msi=1' - Since MSI address (in EP's capability register) has a valid value (set during the previous insertion of the module), EP thinks host supports MSI. Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: designware-ep: Fix find_first_zero_bit() usageNiklas Cassel2017-12-192-10/+32
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_first_zero_bit()'s parameter 'size' is defined in bits, not in bytes. find_first_zero_bit() is called with size in bytes rather than bits, which thus defines a too low upper limit, causing dw_pcie_ep_inbound_atu() to assign iatu index #4 to both bar 4 and bar 5, which makes bar 5 overwrite the settings set by bar 4. Since the sizes of the bitmaps are known, dynamically allocate the bitmaps, and use the correct size when calling find_first_zero_bit(). Additionally, make sure that ep->num_ob_windows and ep->num_ib_windows, which are obtained from device tree, are smaller than the maximum number of iATUs (MAX_IATU_IN/MAX_IATU_OUT). Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | Merge remote-tracking branch 'lorenzo/pci/dwc' into nextBjorn Helgaas2018-02-0110-336/+579
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * lorenzo/pci/dwc: PCI: exynos: Fix a potential init_clk_resources NULL pointer dereference PCI: iproc: Fix NULL pointer dereference for BCMA PCI: dra7xx: Iterate over INTx status bits PCI: dra7xx: Fix legacy INTD IRQ handling PCI: qcom: Account for const type of of_device_id.data PCI: dwc: artpec6: Fix return value check in artpec6_add_pcie_ep() PCI: exynos: Remove deprecated PHY initialization code PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC bindings: PCI: artpec: Add support for the ARTPEC-7 SoC PCI: dwc: artpec6: Deassert the core before waiting for PHY PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument PCI: dwc: artpec6: Add support for endpoint mode bindings: PCI: artpec: Add support for endpoint mode PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions PCI: dwc: artpec6: Use BIT and GENMASK macros PCI: dwc: artpec6: Remove unused defines PCI: dwc: dra7xx: Help compiler to remove unused code PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode PCI: designware-ep: Add generic function for raising MSI irq PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits PCI: dwc: Use the DMA-API to get the MSI address pci: dwc: pci-dra7xx: Make shutdown handler static Includes resolution to conflict between: 4494738de0d9 ("PCI: endpoint: Add the function number as argument to EPC ops") 6f6d7873711c ("PCI: designware-ep: Add generic function for raising MSI irq") The resolution is due to Niklas Cassel <niklas.cassel@axis.com>: https://lkml.kernel.org/r/20180201085608.GA22568@axis.com
| * | PCI: exynos: Fix a potential init_clk_resources NULL pointer dereferenceJaehoon Chung2018-01-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid triggering a NULL pointer dereference in exynos_pcie_probe() a check must be put in place to detect if the init_clk_resources hook is initialized before calling it. Add the respective function pointer check in exynos_pcie_probe(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dra7xx: Iterate over INTx status bitsVignesh R2018-01-101-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible that more than one legacy IRQ may be set at the same time, therefore iterate and handle all the pending INTx interrupts before clearing the status and exiting the IRQ handler. Otherwise, some interrupts would be lost. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: dra7xx: Fix legacy INTD IRQ handlingVignesh R2018-01-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Legacy INTD IRQ handling is broken on dra7xx due to fact that driver uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size 4 which is numbered 0-3. Therefore when INTD IRQ line is used with pci-dra7xx driver following warning is seen: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:342 irq_domain_associate+0x12c/0x1c4 error: hwirq 0x4 is too large for dummy Fix this by using pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 as done in other PCIe drivers. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Reported-by: Chris Welch <Chris.Welch@viavisolutions.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: qcom: Account for const type of of_device_id.dataJulia Lawall2018-01-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver creates various const structures that it stores in the data field of an of_device_id array. Adding const to the declaration of the location that receives the const value from the data field ensures that the compiler will continue to check that the value is not modified. Furthermore, the const-discarding cast on the extraction from the data field is no longer needed. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: dwc: artpec6: Fix return value check in artpec6_add_pcie_ep()Wei Yongjun2018-01-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: exynos: Remove deprecated PHY initialization codeJaehoon Chung2018-01-021-208/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos platforms have a PCI PHY driver in the PHY framework that can be used by the PCI host bridge drivers to initialize and manage the PHY. Remove the deprecated PHY initialization code in the Exynos PCI host bridge driver by updating the driver to use the PHY framework API; modify the DT binding documentation accordingly. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | PCI: dwc: artpec6: Add support for the ARTPEC-7 SoCNiklas Cassel2017-12-211-4/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the ARTPEC-7 SoC in the artpec6 driver. The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar. Unfortunately, some fields in the PCIECFG and PCIESTAT register have changed. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: artpec6: Deassert the core before waiting for PHYNiklas Cassel2017-12-211-16/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Waiting for the PHY while the core was held in reset worked for artpec6, but for artpec7, in order to read the required registers, the core has to be out of reset. Refactor the code so we always wait for the PHY after the core has been deasserted, since this works for both artpec6 and artpec7. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argumentNiklas Cassel2017-12-214-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current cpu addr fixup mask for ARTPEC-6, GENMASK(27, 0), is wrong. The correct cpu addr fixup mask for ARTPEC-6 is GENMASK(28, 0). However, having a hardcoded cpu addr fixup mask in each driver is arguably wrong. A device tree property called something like "cpu-addr-fixup-mask" would have been a better solution. Introducing such a property is not needed though, since we already have pp->cfg0_base and ep->phys_base, which is derived from already existing device tree properties. It is also worth noting that for ARTPEC-7, hardcoding the cpu addr fixup mask is not possible, since it uses a High Address Bits Look Up Table, which means that it can, at runtime, map the PCIe window to an arbitrary address in the 32-bit address space. By using pp->cfg0_base and ep->phys_base, we avoid hardcoding a mask in each driver. This should work for ARTPEC-6, DRA7xx, and ARTPEC-7. I have not changed the code in DRA7xx though, since their existing code works, but if they want, they could use the same logic as artpec6_pcie_cpu_addr_fixup, and thus remove their hardcoded mask. The reason why the fixup mask is needed is explained in commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated address"). Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: dwc: artpec6: Add support for endpoint modeNiklas Cassel2017-12-212-11/+164
| | | | | | | | | | | | | | | | | | | | | | | | The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in endpoint mode. Add endpoint mode support to the artpec6 driver. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functionsNiklas Cassel2017-12-211-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Split artpec6_pcie_establish_link() into smaller functions to better match other drivers such as dra7xx and imx6. This is also done to prepare for endpoint mode support. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: artpec6: Use BIT and GENMASK macrosNiklas Cassel2017-12-211-17/+17
| | | | | | | | | | | | | | | | | | | | | Use BIT and GENMASK macros to improve readability. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: artpec6: Remove unused definesNiklas Cassel2017-12-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to DBI read-only registers") removed the only write using these defines, but it did not remove the defines. Remove the defines since they are now unused. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: dra7xx: Help compiler to remove unused codeNiklas Cassel2017-12-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dra7xx driver supports both host and ep mode. When enabling support for only one of the modes, help the compiler to remove code for the mode that we have not enabled in the driver. By adding if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) return -ENODEV; anything after that statement will get silently dropped by the compiler, including static functions and structures that are referenced indirectly from there. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probeNiklas Cassel2017-12-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assign pp->ops in *_add_pcie_port() to match how it is done in other drivers like exynos, imx7, keystone, armada8k, artpec6, designware-plat, hisi, kirin and spear13xx. This is probably a remainder since when dev and ops were assigned as members to pp. Since we now assign them as members to struct dw_pcie, the pp->ops assignment should definitely be in dra7xx_add_pcie_port(). This is done so that the compiler (in a later commit) can remove more code when enabling only one of the two supported modes (host/ep) in the dra7xx driver. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep modeNiklas Cassel2017-12-212-26/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the Kconfig and Makefile handling for host/ep mode, since the previous handling was a bit unorthodox and would have been a bit bloated once more DWC based controllers added support for ep mode. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: designware-ep: Add generic function for raising MSI irqNiklas Cassel2017-12-212-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic function for raising MSI irqs that can be used by all DWC based controllers. Note that certain controllers, like DRA7xx, have a special convenience register for raising MSI irqs that doesn't require you to explicitly map the MSI address. Therefore, it is likely that certain drivers will not use this generic function, even if they can. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()Niklas Cassel2017-12-213-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the static keyword from dw_pcie_ep_reset_bar() so that pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar(). Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_initNiklas Cassel2017-12-212-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain SoCs need to map the MSI address in raise_irq. To map an address, you first need to call pci_epc_mem_alloc_addr(), however, pci_epc_mem_alloc_addr() calls ioremap() (which can sleep). Since raise_irq is only called from atomic context, we can't call pci_epc_mem_alloc_addr() from raise_irq. Pre-allocate a page in dw_pcie_ep_init(), so that this page can later be used to map/unmap the MSI address in raise_irq. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writableNiklas Cassel2017-12-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain registers that pcie-designware-ep tries to write to are read-only registers. However, these registers can become read/write if we first enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after writing these registers. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bitsNiklas Cassel2017-12-212-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI on systems where the RC has set a 64 bit MSI address. Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | PCI: dwc: Use the DMA-API to get the MSI addressNiklas Cassel2017-12-212-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the DMA-API to get the MSI address. This address will be written to our PCI config space and to the register which determines which AXI address the DWC IP will spoof for incoming MSI irqs. Since it is a PCIe endpoint device, rather than the CPU, that is supposed to write to the MSI address, the proper way to get the MSI address is by using the DMA API, not by using virt_to_phys(). Using virt_to_phys() might work on some systems, but using the DMA API should work on all systems. This is essentially the same thing as allocating a buffer in a driver to which the endpoint will write to. To do this, we use the DMA API. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | pci: dwc: pci-dra7xx: Make shutdown handler staticVignesh R2017-12-201-1/+1
| |/ | | | | | | | | | | | | | | | | | | Define dra7xx_pcie_shutdown() as a static function as it is not used in other compilation units. Signed-off-by: Vignesh R <vigneshr@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Keerthy <j-keerthy@ti.com>
* | PCI: endpoint: Add the function number as argument to EPC opsCyrille Pitchen2018-01-311-8/+12
| | | | | | | | | | | | | | | | This patch updates the prototype of most handlers from 'struct pci_epc_ops' so the EPC library can now support multi-function devices. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | PCI: Regroup all PCI related entries into drivers/pci/MakefileCyrille Pitchen2018-01-311-0/+2
|/ | | | | | | | | | | | | | | | | | | | | Clean up drivers/Makefile by moving the pci/endpoint and pci/dwc entries from drivers/Makefile into drivers/pci/Makefile. Since we don't want to introduce any dependency between CONFIG_PCI and CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile. Hence all Makefiles in drivers/pci/ were updated accordingly so no file is compiled when CONFIG_PCI is not defined. Also, we add a comment to reinforce that EPC and EPF libraries must be initialized before their users. Hence built-in EPC drivers, such as those of Designware, are linked after the endpoint core libraries. Finally, we add another comment to explain why obj-y has been chosen instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* Merge tag 'pci-v4.15-changes' of ↵Linus Torvalds2017-11-155-0/+510
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - detach driver before tearing down procfs/sysfs (Alex Williamson) - disable PCIe services during shutdown (Sinan Kaya) - fix ASPM oops on systems with no Root Ports (Ard Biesheuvel) - fix ASPM LTR_L1.2_THRESHOLD programming (Bjorn Helgaas) - fix ASPM Common_Mode_Restore_Time computation (Bjorn Helgaas) - fix portdrv MSI/MSI-X vector allocation (Dongdong Liu, Bjorn Helgaas) - report non-fatal AER errors only to the affected endpoint (Gabriele Paoloni) - distribute bus numbers, MMIO, and I/O space among hotplug bridges to allow more devices to be hot-added (Mika Westerberg) - fix pciehp races during initialization and surprise link down (Mika Westerberg) - handle surprise-removed devices in PME handling (Qiang) - support resizable BARs for large graphics devices (Christian König) - expose SR-IOV offset, stride, and VF device ID via sysfs (Filippo Sironi) - create SR-IOV virtfn/physfn sysfs links before attaching driver (Stuart Hayes) - fix SR-IOV "ARI Capable Hierarchy" restore issue (Tony Nguyen) - enforce Kconfig IOV/REALLOC dependency (Sascha El-Sharkawy) - avoid slot reset if bridge itself is broken (Jan Glauber) - clean up pci_reset_function() path (Jan H. Schönherr) - make pci_map_rom() fail if the option ROM is invalid (Changbin Du) - convert timers to timer_setup() (Kees Cook) - move PCI_QUIRKS to PCI bus Kconfig menu (Randy Dunlap) - constify pci_dev_type and intel_mid_pci_ops (Bhumika Goyal) - remove unnecessary pci_dev, pci_bus, resource, pcibios_set_master() declarations (Bjorn Helgaas) - fix endpoint framework overflows and BUG()s (Dan Carpenter) - fix endpoint framework issues (Kishon Vijay Abraham I) - avoid broken Cavium CN8xxx bus reset behavior (David Daney) - extend Cavium ACS capability quirks (Vadim Lomovtsev) - support Synopsys DesignWare RC in ECAM mode (Ard Biesheuvel) - turn off dra7xx clocks cleanly on shutdown (Keerthy) - fix Faraday probe error path (Wei Yongjun) - support HiSilicon STB SoC PCIe host controller (Jianguo Sun) - fix Hyper-V interrupt affinity issue (Dexuan Cui) - remove useless ACPI warning for Hyper-V pass-through devices (Vitaly Kuznetsov) - support multiple MSI on iProc (Sandor Bodo-Merle) - support Layerscape LS1012a and LS1046a PCIe host controllers (Hou Zhiqiang) - fix Layerscape default error response (Minghuan Lian) - support MSI on Tango host controller (Marc Gonzalez) - support Tegra186 PCIe host controller (Manikanta Maddireddy) - use generic accessors on Tegra when possible (Thierry Reding) - support V3 Semiconductor PCI host controller (Linus Walleij) * tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (85 commits) PCI/ASPM: Add L1 Substates definitions PCI/ASPM: Reformat ASPM register definitions PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe() PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up() PCI: Fix kernel-doc build warning PCI: Fail pci_map_rom() if the option ROM is invalid PCI: Move pci_map_rom() error path PCI: Move PCI_QUIRKS to the PCI bus menu alpha/PCI: Make pdev_save_srm_config() static PCI: Remove unused declarations PCI: Remove redundant pci_dev, pci_bus, resource declarations PCI: Remove redundant pcibios_set_master() declarations PCI/PME: Handle invalid data when reading Root Status PCI: hv: Use effective affinity mask PCI: pciehp: Do not clear Presence Detect Changed during initialization PCI: pciehp: Fix race condition handling surprise link down PCI: Distribute available resources to hotplug-capable bridges ...
| * Merge branch 'pci/host-layerscape' into nextBjorn Helgaas2017-11-141-0/+12
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-layerscape: PCI: layerscape: Change default error response behavior PCI: Disable MSI for Freescale Layerscape PCIe RC mode arm64: dts: ls1046a: Add PCIe controller DT nodes arm64: dts: ls1012a: Add PCIe controller DT node PCI: layerscape: Add support for ls1012a arm64: dts: ls1012a: Add MSI controller DT node irqchip/ls-scfg-msi: Add LS1012a MSI support
| | * PCI: layerscape: Change default error response behaviorMinghuan Lian2017-10-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it sends an OKAY response to the device's internal AXI slave system interface. However, this default system error response behavior cannot be used for other types of outbound non-posted requests. For example, the outbound memory read transaction requires an actual ERROR response, like UR completion or completion timeout. Fix this by forwarding the error response of the non-posted request. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * PCI: layerscape: Add support for ls1012aHou Zhiqiang2017-10-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ls1012a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * | Merge branch 'pci/host-hisi' into nextBjorn Helgaas2017-11-143-0/+481
| |\ \ | | | | | | | | | | | | | | | | * pci/host-hisi: PCI: hisi: Add HiSilicon STB SoC PCIe controller driver
| | * | PCI: hisi: Add HiSilicon STB SoC PCIe controller driverJianguo Sun2017-10-243-0/+481
| | |/ | | | | | | | | | | | | | | | | | | | | | Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * / PCI: dra7xx: Add shutdown handler to cleanly turn off clocksKeerthy2017-10-111-0/+17
| |/ | | | | | | | | | | | | | | Add shutdown handler to cleanly turn off clocks. This will help in cases of kexec where in a new kernel can boot abruptly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | Merge tag 'usb-4.15-rc1' of ↵Linus Torvalds2017-11-131-0/+16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big set of USB and PHY driver updates for 4.15-rc1. There is the usual amount of gadget and xhci driver updates, along with phy and chipidea enhancements. There's also a lot of SPDX tags and license boilerplate cleanups as well, which provide some churn in the diffstat. Other major thing is the typec code that moved out of staging and into the "real" part of the drivers/usb/ tree, which was nice to see happen. All of these have been in linux-next with no reported issues for a while" * tag 'usb-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (263 commits) usb: gadget: f_fs: Fix use-after-free in ffs_free_inst USB: usbfs: compute urb->actual_length for isochronous usb: core: message: remember to reset 'ret' to 0 when necessary USB: typec: Remove remaining redundant license text USB: typec: add SPDX identifiers to some files USB: renesas_usbhs: rcar?.h: add SPDX tags USB: chipidea: ci_hdrc_tegra.c: add SPDX line USB: host: xhci-debugfs: add SPDX lines USB: add SPDX identifiers to all remaining Makefiles usb: host: isp1362-hcd: remove a couple of redundant assignments USB: adutux: remove redundant variable minor usb: core: add a new usb_get_ptm_status() helper usb: core: add a 'type' parameter to usb_get_status() usb: core: introduce a new usb_get_std_status() helper usb: core: rename usb_get_status() 'type' argument to 'recip' usb: core: add Status Type definitions USB: gadget: Remove redundant license text USB: gadget: function: Remove redundant license text USB: gadget: udc: Remove redundant license text USB: gadget: legacy: Remove redundant license text ...
| * | PCI: dra7xx: Create functional dependency between PCIe and PHYKishon Vijay Abraham I2017-10-231-0/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI core access configuration space registers in resume_noirq callbacks. In the case of dra7xx, PIPE3 PHY connected to PCIe controller has to be enabled before accessing configuration space registers. Since PIPE3 PHY is enabled by only configuring control module registers, no aborts has been observed so far (though during noirq stage, interface clock of PIPE3 PHY is not enabled). With new TRM updates, PIPE3 PHY has to be initialized (PIPE3 PHY registers has to be accessed) as well which requires the interface clock of PIPE3 PHY to be enabled. The interface clock of PIPE3 PHY is derived from OCP2SCP and hence PCIe PHY is modeled as a child of OCP2SCP. Since pm_runtime is not enabled during noirq stage, pm_runtime_get_sync done in phy_init doesn't enable OCP2SCP clocks resulting in abort when PIPE3 PHY registers are accessed. Create a function dependency between PCIe and PHY here to make sure PCIe is suspended before PCIe PHY/OCP2SCP and resumed after PCIe PHY/OCP2SCP. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
* / License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge branch 'pci/trivial' into nextBjorn Helgaas2017-09-077-12/+11
|\ | | | | | | | | | | | | * pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2017-09-017-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/endpoint' into nextBjorn Helgaas2017-09-073-5/+16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/endpoint: tools: PCI: Add a missing option help line misc: pci_endpoint_test: Enable/Disable MSI using module param misc: pci_endpoint_test: Avoid using hard-coded BAR sizes misc: pci_endpoint_test: Add support to not enable MSI interrupts misc: pci_endpoint_test: Add support to provide aligned buffer addresses misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR PCI: designware-ep: Do not disable BARs during initialization PCI: dra7xx: Reset all BARs during initialization PCI: dwc: designware: Provide page_size to pci_epc_mem PCI: endpoint: Remove the ->remove() callback PCI: endpoint: Add support to poll early for host commands PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs PCI: endpoint: Do not reset *command* inadvertently PCI: endpoint: Add "volatile" to pci_epf_test_reg PCI: endpoint: Add support for configurable page size PCI: endpoint: Make ->remove() callback optional PCI: endpoint: Add an API to get matching "pci_epf_device_id" PCI: endpoint: Use of_dma_configure() to set initial DMA mask
| * | PCI: designware-ep: Do not disable BARs during initializationKishon Vijay Abraham I2017-08-291-4/+0
| | | | | | | | | | | | | | | | | | | | | Some platforms like K2G has reserved use of BAR_0 which shouldn't be disabled by software. Avoid disabling all BARs during initialization. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: dra7xx: Reset all BARs during initializationKishon Vijay Abraham I2017-08-291-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | dra7xx has all base address registers (BAR) enabled by default. Reset all BARs during initialization and so that BARs are enabled only if they are actually used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: dwc: designware: Provide page_size to pci_epc_memKishon Vijay Abraham I2017-08-292-1/+3
| |/ | | | | | | | | | | | | | | | | | | | | Use the newly introduced __pci_epc_mem_init() instead of pci_epc_mem_init() to provide page_size to pci_epc_mem. This is in preparation for adding EP support to K2G which has a restriction that the address region should be either divided into 1MB/2MB/4MB or 8MB sizes (Ref: 11.14.4.9.1 Outbound Address Translation in K2G TRM SPRUHY8F January 2016 – Revised May 2017). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 13:33:09 +0000