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* Merge tag 'pci-v4.13-changes' of ↵Linus Torvalds2017-07-0852-652/+3297
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add sysfs max_link_speed/width, current_link_speed/width (Wong Vee Khee) - make host bridge IRQ mapping much more generic (Matthew Minter, Lorenzo Pieralisi) - convert most drivers to pci_scan_root_bus_bridge() (Lorenzo Pieralisi) - mutex sriov_configure() (Jakub Kicinski) - mutex pci_error_handlers callbacks (Christoph Hellwig) - split ->reset_notify() into ->reset_prepare()/reset_done() (Christoph Hellwig) - support multiple PCIe portdrv interrupts for MSI as well as MSI-X (Gabriele Paoloni) - allocate MSI/MSI-X vector for Downstream Port Containment (Gabriele Paoloni) - fix MSI IRQ affinity pre/post/min_vecs issue (Michael Hernandez) - test INTx masking during enumeration, not at run-time (Piotr Gregor) - avoid using device_may_wakeup() for runtime PM (Rafael J. Wysocki) - restore the status of PCI devices across hibernation (Chen Yu) - keep parent resources that start at 0x0 (Ard Biesheuvel) - enable ECRC only if device supports it (Bjorn Helgaas) - restore PRI and PASID state after Function-Level Reset (CQ Tang) - skip DPC event if device is not present (Keith Busch) - check domain when matching SMBIOS info (Sujith Pandel) - mark Intel XXV710 NIC INTx masking as broken (Alex Williamson) - avoid AMD SB7xx EHCI USB wakeup defect (Kai-Heng Feng) - work around long-standing Macbook Pro poweroff issue (Bjorn Helgaas) - add Switchtec "running" status flag (Logan Gunthorpe) - fix dra7xx incorrect RW1C IRQ register usage (Arvind Yadav) - modify xilinx-nwl IRQ chip for legacy interrupts (Bharat Kumar Gogada) - move VMD SRCU cleanup after bus, child device removal (Jon Derrick) - add Faraday clock handling (Linus Walleij) - configure Rockchip MPS and reorganize (Shawn Lin) - limit Qualcomm TLP size to 2K (hardware issue) (Srinivas Kandagatla) - support Tegra MSI 64-bit addressing (Thierry Reding) - use Rockchip normal (not privileged) register bank (Shawn Lin) - add HiSilicon Kirin SoC PCIe controller driver (Xiaowei Song) - add Sigma Designs Tango SMP8759 PCIe controller driver (Marc Gonzalez) - add MediaTek PCIe host controller support (Ryder Lee) - add Qualcomm IPQ4019 support (John Crispin) - add HyperV vPCI protocol v1.2 support (Jork Loeser) - add i.MX6 regulator support (Quentin Schulz) * tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (113 commits) PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support PCI: Add DT binding for Sigma Designs Tango PCIe controller PCI: rockchip: Use normal register bank for config accessors dt-bindings: PCI: Add documentation for MediaTek PCIe PCI: Remove __pci_dev_reset() and pci_dev_reset() PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done() PCI: xilinx: Make of_device_ids const PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts PCI: vmd: Move SRCU cleanup after bus, child device removal PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000 PCI: versatile: Add local struct device pointers PCI: tegra: Do not allocate MSI target memory PCI: tegra: Support MSI 64-bit addressing PCI: rockchip: Use local struct device pointer consistently PCI: rockchip: Check for clk_prepare_enable() errors during resume MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer PCI: rockchip: Configure RC's MPS setting PCI: rockchip: Reconfigure configuration space header type PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses() PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() ...
| * Merge branch 'pci/host-tango' into nextBjorn Helgaas2017-07-073-0/+156
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-tango: PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support PCI: Add DT binding for Sigma Designs Tango PCIe controller Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile
| | * PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge supportMarc Gonzalez2017-07-073-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is required to work around several hardware bugs in the PCIe controller. The SMP8759 does not support legacy interrupts or IO space. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [bhelgaas: add CONFIG_BROKEN dependency, various cleanups] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-xilinx' into nextBjorn Helgaas2017-07-042-2/+45
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-xilinx: PCI: xilinx: Make of_device_ids const PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts
| | * | PCI: xilinx: Make of_device_ids constArvind Yadav2017-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. File size before: text data bss dec hex filename 195 600 0 795 31b drivers/pci/host/pcie-xilinx.o File size after constify xilinx_pcie_of_match: text data bss dec hex filename 595 184 0 779 30b drivers/pci/host/pcie-xilinx.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: xilinx-nwl: Modify IRQ chip for legacy interruptsBharat Kumar Gogada2017-07-021-1/+44
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add spinlock for protecting legacy mask register - Few wifi end points which only support legacy interrupts, performs hardware reset functionalities after disabling interrupts by invoking disable_irq() and then re-enable using enable_irq(), they enable hardware interrupts first and then virtual IRQ line later. - The legacy IRQ line goes low only after DEASSERT_INTx is received. As the legacy IRQ line is high immediately after hardware interrupts are enabled but virq of EP is still in disabled state and EP handler is never executed resulting no DEASSERT_INTx. If dummy IRQ chip is used, interrupts are not masked and system hangs with CPU stall. - Add IRQ chip functions instead of dummy IRQ chip for legacy interrupts. - Legacy interrupts are level sensitive, so using handle_level_irq() is more appropriate as it is masks interrupts until Endpoint handles interrupts and unmasks interrupts after Endpoint handler is executed. - Legacy interrupts are level triggered, virtual IRQ line of EndPoint shows as edge in /proc/interrupts. - Set IRQ flags of virtual IRQ line of EP to level triggered at the time of mapping. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-vmd' into nextBjorn Helgaas2017-07-041-2/+5
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-vmd: PCI: vmd: Move SRCU cleanup after bus, child device removal PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000
| | * | PCI: vmd: Move SRCU cleanup after bus, child device removalJon Derrick2017-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent __call_srcu() changes have exposed that we need to cleanup SRCU structures after pci_stop_root_bus() calls into vmd_msi_free(). Fixes: 3906b91844d6 ("PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU") Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com> Cc: <stable@vger.kernel.org> # 4.11
| | * | PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000Bjorn Helgaas2017-07-021-1/+4
| | |/ | | | | | | | | | | | | | | | | | | VMD domains are allocated starting at 0x10000, not 0x1000 as the comment said. Correct the comment and add a reference to the ACPI spec for _SEG. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
| * | Merge branch 'pci/host-versatile' into nextBjorn Helgaas2017-07-041-9/+9
| |\ \ | | | | | | | | | | | | | | | | * pci/host-versatile: PCI: versatile: Add local struct device pointers
| | * | PCI: versatile: Add local struct device pointersBjorn Helgaas2017-07-021-9/+9
| | |/ | | | | | | | | | | | | | | | | | | Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-tegra' into nextBjorn Helgaas2017-07-041-12/+21
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-tegra: PCI: tegra: Do not allocate MSI target memory PCI: tegra: Support MSI 64-bit addressing
| | * | PCI: tegra: Do not allocate MSI target memoryThierry Reding2017-07-021-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI host bridge found on Tegra SoCs doesn't require the MSI target address to be backed by physical system memory. Writes are intercepted within the controller and never make it to the memory pointed to. Since no actual system memory is required, remove the allocation of a single page and hardcode the MSI target address with a special address that maps to the last 4 KiB page within the range that is reserved for system memory and memory-mapped I/O in the FPCI address map. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| | * | PCI: tegra: Support MSI 64-bit addressingThierry Reding2017-07-021-7/+6
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSI target address can reside beyond the 32-bit boundary on devices with more than 2 GiB of system memory. The PCI host bridge on Tegra can easily support 64-bit addresses, so make sure to pass the upper 32 bits of the target address to endpoints when allocating MSI entries. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | Merge branch 'pci/host-rockchip' into nextBjorn Helgaas2017-07-041-25/+100
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-rockchip: PCI: rockchip: Use normal register bank for config accessors PCI: rockchip: Use local struct device pointer consistently PCI: rockchip: Check for clk_prepare_enable() errors during resume MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer PCI: rockchip: Configure RC's MPS setting PCI: rockchip: Reconfigure configuration space header type PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses() PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu() PCI: rockchip: Control vpcie0v9 for system PM
| | * | PCI: rockchip: Use normal register bank for config accessorsShawn Lin2017-07-031-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip's RC has two banks of registers for the root port: a normal bank that is strictly compatible with the PCIe spec, and a privileged bank that can be used to change RO bits of root port registers. When probing the RC driver, we use the privileged bank to do some basic setup work as some RO bits are hw-inited to wrong value. But we didn't change to the normal bank after probing the driver. This leads to a serious problem when the PME code tries to clear the PME status by writing PCI_EXP_RTSTA_PME to the register of PCI_EXP_RTSTA. Per PCIe 3.0 spec, section 7.8.14, the PME status bit is RW1C. So the PME code is doing the right thing to clear the PME status but we find the RC doesn't clear it but actually setting it to one. So finally the system trap in pcie_pme_work_fn() as PCI_EXP_RTSTA_PME is true now forever. This issue can be reproduced by booting kernel with pci=nomsi. Use the normal register bank for the PCI config accessors. The privileged bank is used only internally by this driver. Fixes: e77f847d ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Brian Norris <briannorris@chromium.org>
| | * | PCI: rockchip: Use local struct device pointer consistentlyShawn Lin2017-07-021-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a local "struct device *dev" in rockchip_pcie_probe(). Use it consistently throughout the function. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Check for clk_prepare_enable() errors during resumeArvind Yadav2017-07-021-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
| | * | PCI: rockchip: Configure RC's MPS settingShawn Lin2017-07-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Reconfigure configuration space header typeShawn Lin2017-07-021-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1 configuration space header should be used when accessing PCIe switch. So we need to reconfigure the header according to the bus number we are accessing. Otherwise we could not visit the buses behind the switch. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()Shawn Lin2017-07-021-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | We need to reconfigure the header type later, so split out a new function. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()Shawn Lin2017-07-021-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuration accesses is also part of ATU settings, so let's keep all of them inside rockchip_pcie_cfg_atu(). Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu()Shawn Lin2017-07-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename rockchip_cfg_atu() to keep the name consistent with other functions in pcie-rockchip.c. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Control vpcie0v9 for system PMShawn Lin2017-07-021-0/+11
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to work then in S3 if folks assign it DT. But we should note that there is a side effect that we could not support beacon wakeup if we disable vpcie0v9 for aggressive power-saving. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Brian Norris <briannorris@chromium.org> Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
| * | Merge branch 'pci/host-rcar' into nextBjorn Helgaas2017-07-041-1/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-rcar: PCI: rcar-gen2: Make of_device_ids const PCI: rcar: Use proper name for the R-Car SoC
| | * | PCI: rcar-gen2: Make of_device_ids constArvind Yadav2017-07-021-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | Merge branch 'pci/host-qcom' into nextBjorn Helgaas2017-07-041-58/+377
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-qcom: PCI: qcom: Limit TLP size to 2K to work around hardware issue PCI: qcom: Fix spelling mistake: "asser" -> "assert" PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc PCI: qcom: Add support for IPQ4019 PCIe controller
| | * | PCI: qcom: Limit TLP size to 2K to work around hardware issueSrinivas Kandagatla2017-07-021-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit TLP size to 2K to work around a hardware bug in the v0 version of PCIe IP. When using default TLP size of 4K, the internal buffer gets corrupted due to this hardware bug. This bug was originally noticed during ssh session between APQ8064-based board and PC. Network packets got corrupted randomly and terminated the ssh session due to this bug. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: qcom: Fix spelling mistake: "asser" -> "assert"Colin Ian King2017-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trivial fix to spelling mistake in dev_err message. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: qcom: Reorder to put v0 functions together, v1 functions together, etcBjorn Helgaas2017-07-021-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | Previously the v0, v1, and v2 functions were not grouped together in a consistent order. Reorder them to make them consistent. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: qcom: Add support for IPQ4019 PCIe controllerJohn Crispin2017-07-021-0/+306
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the IPQ4019 PCIe controller. IPQ4019 supports Gen 1/2, one lane, one PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the same as for the MSM8996, however the clocks and reset lines differ. [bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile issues] Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Rob Herring <robh@kernel.org> # binding
| * | Merge branch 'pci/host-mediatek' into nextBjorn Helgaas2017-07-043-0/+566
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-mediatek: dt-bindings: PCI: Add documentation for MediaTek PCIe PCI: mediatek: Add MediaTek PCIe host controller support
| | * | PCI: mediatek: Add MediaTek PCIe host controller supportRyder Lee2017-07-023-0/+566
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the MediaTek PCIe Gen2 controller which can be found on MT7623 series SoCs. [bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from http://lkml.kernel.org/r/1496644078-27122-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/1497588789-28607-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from http://lkml.kernel.org/r/1498555451-55073-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in powerup fixes from http://lkml.kernel.org/r/1497866400-41844-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in poweroff when link down fixes from http://lkml.kernel.org/r/1497866400-41844-3-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in optional property fixes from http://lkml.kernel.org/r/1497866400-41844-4-git-send-email-ryder.lee@mediatek.com] [bhelgaas: set host->map_irq and host->swizzle_irq and drop pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up() to mtk_pcie_link_up() for consistency, add local struct device pointer] [bhelgaas: fold in pci_add_flags() removal from http://lkml.kernel.org/r/1499061300-55951-1-git-send-email-ryder.lee@mediatek.com] Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-kirin' into nextBjorn Helgaas2017-07-043-0/+528
| |\ \ | | | | | | | | | | | | | | | | * pci/host-kirin: PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver
| | * | PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driverXiaowei Song2017-07-023-0/+528
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hisilicon PCIe driver shares the common functions for PCIe dw-host. The poweron functions are developed on hi3660 SoC, while other functions are common for Kirin series SoCs. Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature are not supported currently. Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/20170704021516.96575-1-songxiaowei@hisilicon.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Cc: Guodong Xu <guodong.xu@linaro.org>
| * | Merge branch 'pci/host-imx6' into nextBjorn Helgaas2017-07-031-1/+36
| |\ \ | | | | | | | | | | | | | | | | * pci/host-imx6: PCI: imx6: Add regulator support
| | * | PCI: imx6: Add regulator supportQuentin Schulz2017-07-021-1/+36
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards might require to control a regulator to power the PCIe port. Add support for an optional regulator defined in Device Tree linked in the PCIe controller under `vpcie-supply`. If present, the regulator will be disabled and then enabled as part of the PCIe host initialization process and will be disabled when shutting down. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> [bhelgaas: use dev_err() instead of pr_err() in imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
| * | Merge branch 'pci/host-hv' into nextBjorn Helgaas2017-07-031-81/+364
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-hv: PCI: hv: Use vPCI protocol version 1.2 PCI: hv: Add vPCI version protocol negotiation PCI: hv: Temporary own CPU-number-to-vCPU-number infra PCI: hv: Use page allocation for hbus structure PCI: hv: Fix comment formatting and use proper integer fields
| | * | PCI: hv: Use vPCI protocol version 1.2Jork Loeser2017-07-021-54/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the Hyper-V vPCI driver to use the Server-2016 version of the vPCI protocol, fixing MSI creation and retargeting issues. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
| | * | PCI: hv: Add vPCI version protocol negotiationJork Loeser2017-07-021-19/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hyper-V vPCI offers different protocol versions. Add the infra for negotiating the one to use. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
| | * | PCI: hv: Temporary own CPU-number-to-vCPU-number infraJork Loeser2017-07-021-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To ease parallel effort to centralize CPU-number-to-vCPU-number conversion, temporarily stand up own version, file-local hv_tmp_cpu_nr_to_vp_nr(). Once the changes have merged, this work-around can be removed, and the calls replaced with hv_cpu_number_to_vp_number(). Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
| | * | PCI: hv: Use page allocation for hbus structureJork Loeser2017-07-021-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hv_pcibus_device structure contains an in-memory hypercall argument that must not cross a page boundary. Allocate the structure as a page to ensure that. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
| | * | PCI: hv: Fix comment formatting and use proper integer fieldsJork Loeser2017-07-021-5/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | Fix comment formatting and use proper integer fields. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
| * | Merge branch 'pci/host-faraday' into nextBjorn Helgaas2017-07-031-0/+56
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-faraday: PCI: faraday: Add clock handling PCI: faraday: Add clock bindings
| | * | PCI: faraday: Add clock handlingLinus Walleij2017-07-021-0/+56
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some optional clock handling to the Faraday FTPCI100. We just get and prepare+enable the clocks right now, if they exist. We can add more elaborate clock handling later. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [bhelgaas: folded in "Make clocks compulsory" fix from http://lkml.kernel.org/r/20170621085730.28804-1-linus.walleij@linaro.org Also folded in the clock max/cur speed fixes from http://lkml.kernel.org/r/20170621162651.25315-1-linus.walleij@linaro.org] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2017-07-032-2/+3
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-dra7xx: PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
| | * | PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAINArvind Yadav2017-07-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we tried to clear interrupt requests by clearing bits in the PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN registers. But per the TRM, these fields are RW1C, so we must *set* bits to clear the interrupt bits. Fixes: 47ff3de911a7 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: dwc: dra7xx: Depend on appropriate SoC or compile testPeter Robinson2017-07-021-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | The PCI controller attached to a SoC isn't much use if the core SoC isn't enabled, unless of course it's compile testing, so add appropriate dependency. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | Merge branch 'pci/host-designware' into nextBjorn Helgaas2017-07-0312-16/+19
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/host-designware: PCI: dwc: Constify dw_pcie_host_ops structures PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
| | * | PCI: dwc: Constify dw_pcie_host_ops structuresJisheng Zhang2017-07-0211-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
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