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| * | phy: cadence-torrent: Add function to get PLL to be configured for DPSwapnil Jakhade2023-05-081-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or multilink protocol configuration for which PHY is configured. In multilink configurations with other protocols, either PLL0 or PLL1 will be used for DP. For single link DP, both PLLs need to be configured at POR. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom-qmp: Add SA8775P USB3 UNI phyShazad Hussain2023-05-081-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SA8775P platform has 5nm USB3 UNI phy attached to the USB0 and USB1 controllers. Add QMP PHY config, pcs entries and support for the new compatible for SA8775P platform. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230428130824.23803-5-quic_shazhuss@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exitDmitry Rokosov2023-05-081-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, all Amlogic boards used the XTAL clock as the default board clock for the USB PHY input, so there was no need to enable it. However, with the introduction of new Amlogic SoCs like the A1 family, the USB PHY now uses a gated clock. Hence, it is necessary to enable this gated clock during the PHY initialization sequence, or disable it during the PHY exit, as appropriate. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230426102922.19705-2-ddrokosov@sberdevices.ru Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | | Merge tag 'media/v6.5-1' of ↵Linus Torvalds2023-07-051-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - Lots of improvement at atomisp driver, which is starting to look in good shape - Mediatek vcodec driver has gained support for av1 and hevc stateless codecs - New sensor driver: ov01a10 - verisilicon driver has gained AV1 entropy helpers - tegra-video has gained support for Tegra20 parallel input - dvb core has gained an extra property to better support DVB-S2X - as usual, lots of cleanups, fixes and improvements on media drivers * tag 'media/v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (253 commits) media: wl128x: fix a clang warning media: dvb: mb86a20s: get rid of a clang-15 warning media: cec: i2c: ch7322: also select REGMAP media: add HAS_IOPORT dependencies media: tc358746: select CONFIG_GENERIC_PHY media: mediatek: vcodec: Add dbgfs help function media: mediatek: vcodec: Add encode to support dbgfs media: mediatek: vcodec: Change dbgfs interface to support encode media: mediatek: vcodec: Get each instance format type media: mediatek: vcodec: Get each context resolution information media: mediatek: vcodec: Add a debugfs file to get different useful information media: mediatek: vcodec: Add debug params to control different log level media: mediatek: vcodec: Add debugfs interface to get debug information media: mediatek: vcodec: support stateless AV1 decoder media: verisilicon: Conditionally ignore native formats media: verisilicon: Enable AV1 decoder on rk3588 media: verisilicon: Add film grain feature to AV1 driver media: verisilicon: Add Rockchip AV1 decoder media: verisilicon: Add AV1 entropy helpers media: verisilicon: Compute motion vectors size for AV1 frames ...
| * | | media: tc358746: select CONFIG_GENERIC_PHYArnd Bergmann2023-06-281-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tc358746 driver selects CONFIG_GENERIC_PHY_MIPI_DPHY and links to that, but this fails when CONFIG_GENERIC_PHY is disabled, because Kbuild then never enters the drivers/phy directory for building object files: ERROR: modpost: "phy_mipi_dphy_get_default_config_for_hsclk" [drivers/media/i2c/tc358746.ko] undefined! Add an explicit 'select GENERIC_PHY' here to ensure that the directory is entered, and add another dependency on that symbol so make it more obvious what is going on if another driver has the same problem, as this will produce a Kconfig warning. Link: https://lore.kernel.org/linux-media/20230623152318.2276816-1-arnd@kernel.org Fixes: 80a21da360516 ("media: tc358746: add Toshiba TC358746 Parallel to CSI-2 bridge driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
* | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-06-294-0/+4
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This batch of clk driver updates contains almost no new SoC support. Instead there's a treewide patch series from Maxime that makes clk_ops::determine_rate mandatory for muxes. Beyond that core framework change we have the usual pile of clk driver updates such as migrating i2c drivers to use .probe() again or YAMLfication of clk DT bindings so we can validate DTBs. Overall the SoCs that got the most updates this time around in terms of diffstat are the Amlogic and Mediatek drivers because they added new SoC support or fixed up various drivers to have proper data. In general things look kinda quiet. I suspect the core framework change may still shake out some problems after the merge window, mostly because not everyone tests linux-next where that series has been for some number of weeks. I saw that there's at least one pending fix for Tegra that needs to be wrapped up into a proper patch. I'll try to catch those bits before the window closes so that -rc1 is bootable. More details below. Core: - Make clk_ops::determine_rate mandatory for muxes New Drivers: - Add amlogic a1 SoC family PLL and peripheral clock controller support Updates: - Handle allocation failures from kasprintf() and friends - Migrate platform clk drivers to .remove_new() - Migrate i2c clk drivers to .probe() instead of .probe_new() - Remove CLK_SET_PARENT from all Mediatek MSDC core clocks - Add infra_ao reset support for Mediatek MT8188 SoCs - Align driver_data to i2c_device_id tables in some i2c clk drivers - Use device_get_match_data() in vc5 clk driver - New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA clock drivers - Use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean DT property in clk-pic32mzda - Convert AT91 clock dt-bindings to YAML - Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX - Keep i.MX UART clocks enabled during kernel boot if earlycon is set - Drop imx_unregister_clocks() as there are no users anymore - Switch to _safe iterator on imx_clk_scu_unregister() to avoid use after free - Add determine_rate op to the imx8m composite clock - Use device managed API for iomap and kzalloc for i.MXRT1050, i.MX8MN, i.MX8MP and i.MX93 clock controller drivers - Add missing interrupt DT property for the i.MX8M clock controller - Re-add support for Exynos4212 clock controller because we are re-introducing the SoC in the mainline - Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve some objtool warnings - Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC - Convert the Renesas clock drivers to readl_poll_timeout_atomic() - Add PWM clock on Renesas R-Car V3U - Fix PLL5 on Renesas RZ/G2L and RZ/V2L" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (149 commits) clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf() clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon ...
| * | phy: ti: j721e-wiz: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI J721e Wiz clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-44-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | phy: ti: am654-serdes: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI AM654 SerDes clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-43-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | phy: cadence: torrent: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence Torrent refclk clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-42-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | phy: cadence: sierra: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence Sierra PLL clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-41-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | phy: qcom-snps: correct struct qcom_snps_hsphy kerneldocKrzysztof Kozlowski2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | Update kerneldoc of struct qcom_snps_hsphy to fix: drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c:135: warning: Function parameter or member 'update_seq_cfg' not described in 'qcom_snps_hsphy' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230507144818.193039-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: amlogic: phy-meson-g12a-mipi-dphy-analog: fix CNTL2_DIF_TX_CTL0 valueNeil Armstrong2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported fixing timings issues. Fixes: 2a56dc650e54 ("phy: amlogic: Add G12A Analog MIPI D-PHY driver") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v4-10-2592c29ea263@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: mediatek: rework the floating point comparisons to fixed pointTom Rix2023-05-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc on aarch64 reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’ is incompatible with the use of floating-point types 240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) Floating point should not be used, so rework the floating point comparisons to fixed point. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230502145005.2927101-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-pcie-msm8996: fix init-count imbalanceJohan Hovold2023-05-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The init counter is not decremented on initialisation errors, which prevents retrying initialisation. Add the missing decrement on initialisation errors so that the counter reflects the state of the device. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: stable@vger.kernel.org # 4.12 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230502103810.12061-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp-combo: fix init-count imbalanceJohan Hovold2023-05-081-2/+3
|/ | | | | | | | | | | | | | | | The init counter is not decremented on initialisation errors, which prevents retrying initialisation and can lead to the runtime suspend callback attempting to disable resources that have never been enabled. Add the missing decrement on initialisation errors so that the counter reflects the state of the device. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: stable@vger.kernel.org # 4.12 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230502103810.12061-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-fixes-6.4-1' of ↵Linus Torvalds2023-05-051-8/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy fixes from Vinod Koul: - Fix for mediatek driver warning for variable used uninitialized and for wrong pll math * tag 'phy-fixes-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: mediatek: hdmi: mt8195: fix wrong pll calculus phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc
| * phy: mediatek: hdmi: mt8195: fix wrong pll calculusGuillaume Ranquet2023-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'. Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calcGuillaume Ranquet2023-05-041-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported by the kernel test robot. Fix the issue by removing the variable altogether and testing out the return value of mtk_hdmi_pll_set_hw() Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64321@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | Merge tag 'phy-for-6.4' of ↵Linus Torvalds2023-05-0360-821/+1514
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New support: - UFS PHY for Qualcomm SA8775p, SM7150 - PCIe 2 lane phy support for sc8180x and PCIe PHY for SDX65 - Mediatke hdmi phy support for mt8195 - rockchip naneng combo phy support for RK358 Updates: - Drop Thunder Bay eMMC PHY driver - RC support for PCIe phy for Qualcomm SDX55 - SGMII support in WIZ driver for J721E - PCIe and multilink SGMII PHY support in cadence driver - Big pile of platform remove callback returning void conversions" * tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits) phy: cadence: cdns-dphy-rx: Add common module reset support phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select() phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration phy: mediatek: add support for phy-mtk-hdmi-mt8195 phy: phy-mtk-hdmi: Add generic phy configure callback dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port dt-bindings: phy: ti,phy-j721e-wiz: document clock-output-names dt-bindings: phy: ti,phy-j721e-wiz: drop assigned-clocks dt-bindings: phy: ti,phy-am654-serdes: drop assigned-clocks type dt-bindings: phy: cadence-torrent: drop assigned-clocks dt-bindings: phy: cadence-sierra: drop assigned-clocks phy: rockchip: remove unused hw_to_inno function phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes phy: qcom-qmp-ufs: Add SM7150 support ...
| * phy: cadence: cdns-dphy-rx: Add common module reset supportSinthu Raja2023-04-121-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPHY RX module has a common module reset (RSTB_CMN) which is expected to be released during configuration. In J721E SR1.0 the RSTB_CMN is internally tied to CSI_RX_RST and is hardware controlled, for all other newer platforms the common module reset is software controlled. Add support to control common module reset during configuration and also skip common module reset based on soc_device_match() for J721E SR1.0. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230314073137.2153-1-vaishnav.a@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721ESiddharth Vadapalli2023-04-121-0/+2
| | | | | | | | | | | | | | | | | | Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309092434.443550-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()Siddharth Vadapalli2023-04-121-6/+5
| | | | | | | | | | | | | | | | | | | | | | In the wiz_mode_select() function, the configuration performed for PHY_TYPE_USXGMII is unreachable. Fix it. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationSwapnil Jakhade2023-04-121-2/+139
| | | | | | | | | | | | | | | | | | | | Add register sequences for PCIe + SGMII PHY multilink configuration. This has been validated on TI J7 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: mediatek: add support for phy-mtk-hdmi-mt8195Guillaume Ranquet2023-04-125-0/+614
| | | | | | | | | | | | | | | | | | Add support for the mediatek hdmi phy on MT8195 SoC Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Link: https://lore.kernel.org/r/20220919-v8-3-a84c80468fe9@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: phy-mtk-hdmi: Add generic phy configure callbackGuillaume Ranquet2023-04-122-0/+13
| | | | | | | | | | | | | | | | | | | | Some phys, such as mt8195, needs to have a configure callback defined. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Link: https://lore.kernel.org/r/20220919-v8-2-a84c80468fe9@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ↵Gaosheng Cui2023-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ulpi_port The tegra_xusb_port_unregister should be called when usb2_port and ulpi_port map fails in tegra_xusb_add_usb2_port() or in tegra_xusb_add_ulpi_port(), fix it. Fixes: 53d2a715c240 ("phy: Add Tegra XUSB pad controller support") Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221129111634.1547747-1-cuigaosheng1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: remove unused hw_to_inno functionTom Rix2023-04-121-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | clang with W=1 reports drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c:284:36: error: unused function 'hw_to_inno' [-Werror,-Wunused-function] static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) ^ This function is not used so remove it. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lore.kernel.org/r/20230324132649.2649166-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775pBartosz Golaszewski2023-04-121-0/+37
| | | | | | | | | | | | | | | | Add QMP PHY config for sa8775p and add support for the new compatible. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230411130446.401440-4-brgl@bgdev.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tblDmitry Baryshkov2023-04-101-5/+0
| | | | | | | | | | | | | | | | | | | | The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX table is empty, so we can drop it completely. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230331151250.4049-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanesDmitry Baryshkov2023-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of lanes to 2. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Cc: stable@vger.kernel.org # 5.15 Sgned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230331151250.4049-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-ufs: Add SM7150 supportDavid Wronek2023-03-311-0/+61
| | | | | | | | | | | | | | | | | | | | | | Add the tables and constants for init sequences for UFS QMP phy found in SM7150 SoC. Signed-off-by: David Wronek <davidwronek@gmail.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: Add naneng combo phy support for RK3588Lucas Tanure2023-03-311-0/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RK3588 combo phy This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net> Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com> Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp: Add support for SDX65 QMP PCIe PHYRohit Agarwal2023-03-314-0/+193
| | | | | | | | | | | | | | | | | | | | The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip-pcie: remove unused phy_rd_cfg functionTom Rix2023-03-311-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | clang with W=1 reports drivers/phy/rockchip/phy-rockchip-pcie.c:122:19: error: unused function 'phy_rd_cfg' [-Werror,-Wunused-function] static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy, ^ This function is not used, so remove it. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230321122503.1783311-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: omap-usb2-phy: Use dev_err_probe()Ye Xingchen2023-03-311-5/+3
| | | | | | | | | | | | | | | | | | Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/202303231545522162256@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: dphy: Use devm_platform_ioremap_resource()Yang Li2023-03-311-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | According to commit 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to use devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230323073534.75037-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: use qmp_combo_offsets_v3 instead of _v6Dmitry Baryshkov2023-03-311-17/+1
| | | | | | | | | | | | | | | | | | | | The qmp_combo_offsets_v3 table is already used for v3 and v4 PHYs. Reuse it for v6 too, dropping the separate qmp_combo_offsets_v6. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230323144726.1614344-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: fix v3 offsets tableDmitry Baryshkov2023-03-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | SM8350 and SM8450 use qmp_combo_offsets_v3 table, which doesn't have PCS_USB offset. Add the usb3_pcs_usb entry to program correct registers while setting up sm8350 and sm8450 USB+DP combo PHYs. Fixes: 05bd18348b88 ("phy: qcom-qmp-combo: Add config for SM6350") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230323144726.1614344-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence: Sierra: Use clk_parent_data to provide parent informationLars-Peter Clausen2023-03-311-42/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than requesting the parent reference clocks for the sierra PHY PLLs and then assigning the parents as a struct clk. Use the clk_parent_data feature for the clock framework and only specify the firmware names of the parent clocks. The clock framework internally will then translate this to the actual clocks. This allows to remove a bit of boilerplate code. It also allows to only specify a single reference clock for both PLLs, which is a valid use case. The clock framework can handle the case where not all inputs for a clock mux are connected, while the custom implementation in the driver could not. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Lars-Peter Clausen2023-03-311-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | The `devm_clk_register()` API is deprecated. Switch to `devm_clk_hw_register()`. Since the driver enables its own internal PLLs using the clock API we still need to get a reference to the PLL clocks using the `devm_clk_hw_get_clk()` API. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230326011416.363318-1-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: xilinx: phy-zynqmp: mention SGMII as supported protocolRadhey Shyam Pandey2023-03-311-3/+2
| | | | | | | | | | | | | | | | | | | | SGMII is validated on kria KR260 robotics starter kit. So modify the comment description to include it in supported controllers list. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1679940407-13131-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machinesMichael Grzeschik2023-03-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | An minimum udelay of 200 us seems to be necessary on some machines. After the setup of the pll, which needs about 100 us to be locked there seem to be additional 100 us to get the phy really functional. Without this delay the usb runs not functional. With this additional short udelay this issue was not reported again. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20230227151318.1894938-1-m.grzeschik@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: xgene: Depend on ARCH_XGENE rather than plain arm64Mark Brown2023-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The X-Gene PHY driver is unlikely to be useful on a kernel without general X-Gene support enabled but currently only depends on arm64 rather than the specific platform support. Narrow the dependency to ARCH_XGENE like we do for other X-Gene specific drivers to ensure that users who have configured down the set of platforms enabled don't see the option. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-phy-build-deps-v1-1-7091bcbd16b0@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: st: miphy28lp: use _poll_timeout functions for waitsAlain Volmat2023-03-201-32/+10
| | | | | | | | | | | | | | | | | | | | This commit introduces _poll_timeout functions usage instead of wait loops waiting for a status bit. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20230210224309.98452-1-avolmat@me.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: tegra: xusb: Support sleepwalk for Tegra234Henry Lin2023-03-202-0/+21
| | | | | | | | | | | | | | | | | | | | Add new registers programming in sleepwalk sequence for Tegra234: MASTER_ENABLE_A/B/C/D in XUSB_AO_UTMIP_SLEEPWALK. Signed-off-by: Henry Lin <henryl@nvidia.com> Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Link: https://lore.kernel.org/r/20230309061708.4156383-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: st: spear: drop of_match_ptr for ID tableKrzysztof Kozlowski2023-03-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might not be relevant here). This also fixes !CONFIG_OF error: drivers/phy/st/phy-spear1310-miphy.c:172:34: error: ‘spear1310_miphy_of_match’ defined but not used [-Werror=unused-const-variable=] drivers/phy/st/phy-spear1340-miphy.c:182:34: error: ‘spear1340_miphy_of_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230312132611.352654-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: marvell: drop of_match_ptr for ID tableKrzysztof Kozlowski2023-03-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might not be relevant here). This also fixes !CONFIG_OF error: drivers/phy/marvell/phy-pxa-28nm-hsic.c:192:34: error: ‘mv_hsic_phy_dt_match’ defined but not used [-Werror=unused-const-variable=] drivers/phy/marvell/phy-pxa-28nm-usb2.c:324:34: error: ‘mv_usbphy_dt_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230312132611.352654-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: Use of_property_present() for testing DT property presenceRob Herring2023-03-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230310144720.1544600-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: phy-twl4030-usb: Convert to platform remove callback returning voidUwe Kleine-König2023-03-201-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-32-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: phy-ti-pipe3: Convert to platform remove callback returning voidUwe Kleine-König2023-03-201-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-31-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
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