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* phy: hisilicon: Fix an out of bounds check in hisi_inno_phy_probe()Harshit Mogalapalli2023-07-241-1/+1
| | | | | | | | | | | | | | | | | The size of array 'priv->ports[]' is INNO_PHY_PORT_NUM. In the for loop, 'i' is used as the index for array 'priv->ports[]' with a check (i > INNO_PHY_PORT_NUM) which indicates that INNO_PHY_PORT_NUM is allowed value for 'i' in the same loop. This > comparison needs to be changed to >=, otherwise it potentially leads to an out of bounds write on the next iteration through the loop Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Link: https://lore.kernel.org/r/20230721090558.3588613-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-snps-femto-v2: use qcom_snps_hsphy_suspend/resume error codeAdrien Thierry2023-07-121-4/+2
| | | | | | | | | The return value from qcom_snps_hsphy_suspend/resume is not used. Make sure qcom_snps_hsphy_runtime_suspend/resume return this value as well. Signed-off-by: Adrien Thierry <athierry@redhat.com> Link: https://lore.kernel.org/r/20230629144542.14906-4-athierry@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-snps-femto-v2: properly enable ref clockAdrien Thierry2023-07-121-15/+48
| | | | | | | | | | | | | | | | | | | The driver is not enabling the ref clock, which thus gets disabled by the clk_disable_unused() initcall. This leads to the dwc3 controller failing to initialize if probed after clk_disable_unused() is called, for instance when the driver is built as a module. To fix this, switch to the clk_bulk API to handle both cfg_ahb and ref clocks at the proper places. Note that the cfg_ahb clock is currently not used by any device tree instantiation of the PHY. Work needs to be done separately to fix this. Link: https://lore.kernel.org/linux-arm-msm/ZEqvy+khHeTkC2hf@fedora/ Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Adrien Thierry <athierry@redhat.com> Link: https://lore.kernel.org/r/20230629144542.14906-3-athierry@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-snps-femto-v2: keep cfg_ahb_clk enabled during runtime suspendAdrien Thierry2023-07-121-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the dwc3 core, both system and runtime suspend end up calling dwc3_suspend_common(). From there, what happens for the PHYs depends on the USB mode and whether the controller is entering system or runtime suspend. HOST mode: (1) system suspend on a non-wakeup-capable controller The [1] if branch is taken. dwc3_core_exit() is called, which ends up calling phy_power_off() and phy_exit(). Those two functions decrease the PM runtime count at some point, so they will trigger the PHY runtime sleep (assuming the count is right). (2) runtime suspend / system suspend on a wakeup-capable controller The [1] branch is not taken. dwc3_suspend_common() calls phy_pm_runtime_put_sync(). Assuming the ref count is right, the PHY runtime suspend op is called. DEVICE mode: dwc3_core_exit() is called on both runtime and system sleep unless the controller is already runtime suspended. OTG mode: (1) system suspend : dwc3_core_exit() is called (2) runtime suspend : do nothing In host mode, the code seems to make a distinction between 1) runtime sleep / system sleep for wakeup-capable controller, and 2) system sleep for non-wakeup-capable controller, where phy_power_off() and phy_exit() are only called for the latter. This suggests the PHY is not supposed to be in a fully powered-off state for runtime sleep and system sleep for wakeup-capable controller. Moreover, downstream, cfg_ahb_clk only gets disabled for system suspend. The clocks are disabled by phy->set_suspend() [2] which is only called in the system sleep path through dwc3_core_exit() [3]. With that in mind, don't disable the clocks during the femto PHY runtime suspend callback. The clocks will only be disabled during system suspend for non-wakeup-capable controllers, through dwc3_core_exit(). [1] https://elixir.bootlin.com/linux/v6.4/source/drivers/usb/dwc3/core.c#L1988 [2] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/LV.AU.1.2.1.r2-05300-gen3meta.0/drivers/usb/phy/phy-msm-snps-hs.c#L524 [3] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/LV.AU.1.2.1.r2-05300-gen3meta.0/drivers/usb/dwc3/core.c#L1915 Signed-off-by: Adrien Thierry <athierry@redhat.com> Link: https://lore.kernel.org/r/20230629144542.14906-2-athierry@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: mediatek: hdmi: mt8195: fix prediv bad upper limit testGuillaume Ranquet2023-07-121-1/+1
| | | | | | | | | | | | | The pll prediv calculus searchs for the smallest prediv that gets the ns_hdmipll_ck in the range of 5 GHz to 12 GHz. A typo in the upper bound test was testing for 5Ghz to 1Ghz Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230529-hdmi_phy_fix-v1-1-bf65f53af533@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-mtk-dp: Fix an error code in probe()Dan Carpenter2023-07-121-1/+1
| | | | | | | | | | Negative -EINVAL was intended instead of positive EINVAL. Fixes: 6a23afad443a ("phy: phy-mtk-dp: Add driver for DP phy") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/3c699e00-2883-40d9-92c3-0da1dc38fdd4@moroto.mountain Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.5_v2' of ↵Linus Torvalds2023-07-0524-446/+2584
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Debugfs support for phy core and mediatek driver - Hisilicon inno-usb2-phy driver supporting Hi3798MV100 - Qualcomm SGMII SerDes PHY driver, SM6115 & QCM2290 QMP-USB support, SA8775P USB PHY & USB3 UNI support, QUSB2 support for IPQ9574, IPQ9574 USB3 PHY UpdatesL - Sparx5 serdes phy power optimzation - cadence salvo usb properties and updates and torrent DP with PCIe & USB support - Yaml conversion for Broadcom kona USB bindings and MXS USB binding" * tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (67 commits) dt-bindings: phy: brcm,brcmstb-usb-phy: Fix error in "compatible" conditional schema dt-bindings: phy: mixel,mipi-dsi-phy: Remove assigned-clock* properties dt-bindings: phy: intel,combo-phy: restrict node name suffixes dt-bindings: phy: qcom,usb-hs-phy: Add compatible phy: tegra: xusb: check return value of devm_kzalloc() phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550 phy: qcom: add the SGMII SerDes PHY driver dt-bindings: phy: describe the Qualcomm SGMII PHY phy: qualcomm: fix indentation in Makefile phy: usb: suppress OC condition for 7439b2 phy: usb: Turn off phy when port is in suspend phy: tegra: xusb: Clear the driver reference in usb-phy dev dt-bindings: phy: mxs-usb-phy: add imx8ulp and imx8qm compatible dt-bindings: phy: mxs-usb-phy: convert to DT schema format dt-bindings: phy: qcom,qmp-usb: fix bindings error dt-bindings: phy: qcom,qmp-ufs: fix the sc8180x regs dt-bindings: phy: qcom,qmp-pcie: fix the sc8180x regs phy: mediatek: tphy: add debugfs files phy: core: add debugfs files phy: fsl-imx8mp-usb: add support for phy tuning ...
| * phy: tegra: xusb: check return value of devm_kzalloc()Claudiu Beznea2023-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | devm_kzalloc() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: f67213cee2b3 ("phy: tegra: xusb: Add usb-role-switch support") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230531073950.145339-1-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550Neil Armstrong2023-06-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | The SM8550 PHY also uses a different offset for the CMN_STATUS reg, use the right one for the v6 Display Port configuration. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-phy-init-fix-v1-1-4e9da9f97991@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: add the SGMII SerDes PHY driverBartosz Golaszewski2023-06-213-0/+461
| | | | | | | | | | | | | | | | | | Implement support for the SGMII/SerDes PHY present on various Qualcomm platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230619091336.194914-4-brgl@bgdev.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qualcomm: fix indentation in MakefileBartosz Golaszewski2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | Align all entries in Makefile. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230619091336.194914-2-brgl@bgdev.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: usb: suppress OC condition for 7439b2Justin Chen2023-06-211-0/+34
| | | | | | | | | | | | | | | | | | | | | | We hit a false positive OC for 7439b2 in DRD/device mode for the second port. So disable the OC check for this use case. Add capability to suppress OC condition for specific ports. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/1686859578-45242-3-git-send-email-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: usb: Turn off phy when port is in suspendJustin Chen2023-06-212-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The COMMONONN bit turns off the PHY when the host controller puts it into suspend state. This can happen during the following... - Nothing is connected to the port - The host controller goes into low power mode whatever due to auto suspend or system suspend. With COMMONONN we also must unset U2_FREECLK_EXISTS since the UTMI clock is fed by the PHY. With these changes we see a power savings of ~12mW when port is in suspend. Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Justin Chen <justin.chen@broadcom.com> Link: https://lore.kernel.org/r/1686859578-45242-2-git-send-email-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: tegra: xusb: Clear the driver reference in usb-phy devEJ Hsu2023-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the dual-role port, it will assign the phy dev to usb-phy dev and use the port dev driver as the dev driver of usb-phy. When we try to destroy the port dev, it will destroy its dev driver as well. But we did not remove the reference from usb-phy dev. This might cause the use-after-free issue in KASAN. Fixes: e8f7d2f409a1 ("phy: tegra: xusb: Add usb-phy support") Cc: stable@vger.kernel.org Signed-off-by: EJ Hsu <ejh@nvidia.com> Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230609062932.3276509-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: mediatek: tphy: add debugfs filesChunfeng Yun2023-05-191-0/+356
| | | | | | | | | | | | | | | | | | These debugfs files are mainly used to make eye diagram test easier, especially helpful to do HQA test for a new IC without efuse enabled. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: core: add debugfs filesChunfeng Yun2023-05-191-0/+14
| | | | | | | | | | | | | | | | | | Add a debugfs root for phy class, and create a debugfs directory under the root when create phy, then phy drivers can add debugfs files. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: fsl-imx8mp-usb: add support for phy tuningLi Jun2023-05-191-0/+218
| | | | | | | | | | | | | | | | | | | | | | Add USB PHY parameter tuning for USB certifications. Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> [j.zink: ported to v6.3-rc1 from NXP downstream repo + cleanups] Signed-off-by: Johannes Zink <j.zink@pengutronix.de> Link: https://lore.kernel.org/r/20230516-lustige-usb-phy-dinge-v2-2-3383a0de34ac@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: Introduce drm_bridgeBjorn Andersson2023-05-192-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: Introduce orientation switchingBjorn Andersson2023-05-192-9/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/ Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-6-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: Introduce orientation variableBjorn Andersson2023-05-191-24/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In multiple places throughout the driver code has been written in prepration for handling of orientation switching. Introduce a typec_orientation in qmp_combo and fill out the various "placeholders" with the associated logic. By initializing the orientation to "normal" this change has no functional impact, but reduces the size of the upcoming introduction of dynamic orientation switching. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-5-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: Extend phy_mutex to all phy_opsBjorn Andersson2023-05-191-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy core ensures mutual exclusion across the ops for a given phy, but the upcoming introduction of USB Type-C orientation switching might race with the DisplayPort phy operations. So extend the mutual exclusion to cover the remaining ops as well, to avoid concurrent reconfiguration of the hardware. Reported-by: Johan Hovold <johan@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-4-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-combo: Move phy_mutex out of com_init/exitBjorn Andersson2023-05-191-19/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming introduction of USB Type-C orientation switching the region of mutual exclusion needs to be extended to cover both the common init/exit as well as the individual functions. So move the phy_mutex one step up the stack. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-3-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * Merge branch 'fixes' into nextVinod Koul2023-05-195-11/+13
| |\ | | | | | | | | | This brings in the Qcom qmp patch fixes into next as well
| * | phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt propertyFrank Li2023-05-191-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-6-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence: salvo: add .set_mode APIPeter Chen2023-05-191-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For NXP platform design, the PHY can't know VBUS well, it causes the FSM in controller seeing the disconnection at L1 use case. With .set_mode API introduced, the controller driver could force PHY seeing B Session VALID when it is at the device mode (VBUS is there), and keep FSM working well. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-5-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence: salvo: add bist fixPeter Chen2023-05-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very limited parts may fail to work on full speed mode (both host and device modes) for USB3 port due to higher threshold in full speed receiver of USB2.0 PHY. One example failure symptom is, the enumeration is failed when connecting full speed USB mouse to USB3 port, especially under high temperature. The workaround is to configure threshold voltage value of single ended receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-4-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence: salvo: decrease delay value to zero for txvalidPeter Chen2023-05-191-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For USB2 L1 use cases, some hosts may start transferring less than 20us after End of Resume, it causes the host seeing corrupt packet from the device side. The reason is the delay time between PHY powers up and txvalid is 20us. To fix it, we change the delay value as 0us. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-3-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence: salvo: add access for USB2PHYPeter Chen2023-05-191-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an offset for USB2PHY in SALVO phy, add offset parameter for read and write API to cover both USB2 and USB3 PHY control. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-2-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom-qmp-usb: add support for updated qcm2290 / sm6115 bindingBhupesh Sharma2023-05-171-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new qcm2290 / sm6115 binding. The USB QMP phy on these devices supports 2 lanes. Note that the binding now does not describe every register subregion and instead the driver holds the corresponding offsets. While at it also include support for PCS_MISC region which was left out earlier. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230516150511.2346357-3-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: ti: gmii-sel: Enable USXGMII mode for J784S4Siddharth Vadapalli2023-05-161-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4Siddharth Vadapalli2023-05-161-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: ti: gmii-sel: Enable SGMII mode for J721ESiddharth Vadapalli2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: ti: gmii-sel: Enable SGMII mode for J7200Siddharth Vadapalli2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: ti: gmii-sel: Add support for SGMII modeSiddharth Vadapalli2023-05-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC supports it. The extra_modes member of the phy_gmii_sel_soc_data struct corresponding to the SoC is used to determine whether or not the SoC supports SGMII mode. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: freescale: imx8m-pcie: Use devm_platform_ioremap_resource()Yang Li2023-05-161-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230428052758.38636-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: hisilicon: Allow building phy-hisi-inno-usb2 on ARM32David Yang2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support for inno-usb2-phy on Hi3798MV100 was added into existing driver, while Hi3798MV100 is a A9 ARM32-only SoC. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://lore.kernel.org/r/20230509060449.1151113-3-mmyangfl@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: hisilicon: Add inno-usb2-phy driver for Hi3798MV100David Yang2023-05-161-16/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adopt existing phy-hisi-inno-usb2 driver to Hi3798MV100, with a slightly different TEST register convention. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://lore.kernel.org/r/20230509060449.1151113-2-mmyangfl@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: Revert "phy: Remove SOC_EXYNOS4212 dep. from PHY_EXYNOS4X12_USB"Artur Weber2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit fee7e1d50c6e6da1d99035181ba5a5c88f5bb526. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230501195525.6268-9-aweber.kernel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom: qmp: Update IPQ9574 USB Phy initialization SequenceVaradarajan Narayanan2023-05-161-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/4f15c21f28e2a1332fbdb04d60641cbbf05c6f15.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom-qusb2: add QUSB2 support for IPQ9574Varadarajan Narayanan2023-05-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the phy init sequence for the Super Speed ports found on IPQ9574. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/7c67e9e92227add6544009092adbd400c3cb47db.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanesDaniel Machon2023-05-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resetting the serdes involves reconfiguring it with preset values. The serdesmode is required to determine the clock-providing CMU, therefore make sure the serdes is not reconfigured if the serdesmode is not set. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: remove power up of all CMUsDaniel Machon2023-05-082-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | CMUs should not be powered up by default anymore, so remove responsible code. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: power on CMUs individuallyDaniel Machon2023-05-081-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a preset map of serdes mode and index to CMU index. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-6-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: power down all CMUs by defaultDaniel Machon2023-05-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU. Individual CMUs are later powered up, when the serdes lanes are configured. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-5-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: reorder CMU functionsDaniel Machon2023-05-081-153/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: configure optimal quiet mode for serdes lanesDaniel Machon2023-05-081-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the serdes lanes of the sparx5 will transition between normal mode and quiet mode, depending on activity. Make sure that the quiet mode is configured optimally for all lanes initially. Although not much, this will save a small amount of power. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-3-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: sparx5-serdes: add registers required for SD/CMU power downDaniel Machon2023-05-081-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add registers required to configure serdeses and CMUs for initial power down. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-2-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence-torrent: Add USB + DP multilink configurationSwapnil Jakhade2023-05-081-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | Add USB + DP no SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclkSwapnil Jakhade2023-05-081-57/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add multilink DP configuration support for 100MHz reference clock rate. This is the only clock rate supported currently for multilink PHY configurations. Also, add PCIe + DP multiprotocol multilink register configuration sequences for 100MHz refclk with no SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: cadence-torrent: Prepare driver for multilink DP supportSwapnil Jakhade2023-05-081-137/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prepares driver for multilink DP support as well as for multiprotocol PHY configurations involving DP as one of the required protocols. This needs changes in functions configuring default single link DP with master lane 0 to support non-zero master lane values and associated PLL configurations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-3-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 17:56:15 +0000