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path: root/drivers/pinctrl/intel/pinctrl-intel.c
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* pinctrl: intel: Set default bias in case no particular value givenAndy Shevchenko2020-11-181-0/+8
| | | | | | | | | | | | | | | | | | | | | [ Upstream commit f3c75e7a9349d1d33eb53ddc1b31640994969f73 ] When GPIO library asks pin control to set the bias, it doesn't pass any value of it and argument is considered boolean (and this is true for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual drivers must behave well, when they got the resistance value of 1 Ohm, i.e. transforming it to sane default. In case of Intel pin control hardware the 5 kOhm sounds plausible because on one hand it's a minimum of resistors present in all hardware generations and at the same time it's high enough to minimize leakage current (will be only 200 uA with the above choice). Fixes: e57725eabf87 ("pinctrl: intel: Add support for hardware debouncer") Reported-by: Jamie McClymont <jamie@kwiius.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* pinctrl: intel: Avoid potential glitches if pin is in GPIO modeAndy Shevchenko2019-10-211-1/+20
| | | | | | | | | | | | | | | | | | | | | When consumer requests a pin, in order to be on the safest side, we switch it first to GPIO mode followed by immediate transition to the input state. Due to posted writes it's luckily to be a single I/O transaction. However, if firmware or boot loader already configures the pin to the GPIO mode, user expects no glitches for the requested pin. We may check if the pin is pre-configured and leave it as is till the actual consumer toggles its state to avoid glitches. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip") Cc: stable@vger.kernel.org Cc: fei.yang@intel.com Reported-by: Oliver Barta <oliver.barta@aptiv.com> Reported-by: Malin Jonsson <malin.jonsson@ericsson.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Allocate IRQ chip dynamicAndy Shevchenko2019-10-011-13/+14
| | | | | | | | | | | | | | | | | | Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: ee1a6ca43dba ("pinctrl: intel: Add Intel Broxton pin controller support") Depends-on: 5ff56b015e85 ("pinctrl: intel: Disable GPIO pin interrupts in suspend") Reported-by: Federico Ricchiuto <fed.ricchiuto@gmail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: mark intel_pin_to_gpio __maybe_unusedArnd Bergmann2019-09-091-1/+1
| | | | | | | | | | | | | | | The intel_pin_to_gpio() function is only called by the PM support functions and causes a warning when those are disabled: drivers/pinctrl/intel/pinctrl-intel.c:841:12: error: unused function 'intel_pin_to_gpio' [-Werror,-Wunused-function] Mark it __maybe_unused to suppress the warning. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Chris Chiu <chiu@endlessm.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: remap the pin number to gpio offset for irq enabled pinChris Chiu2019-08-191-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Asus X571GT, GPIO 297 is configured as an interrupt and serves for the touchpad. The touchpad will report input events much less than expected after S3 suspend/resume, which results in extremely slow cursor movement. However, the number of interrupts observed from /proc/interrupts increases much more than expected even no touching touchpad. This is due to the value of PADCFG0 of PIN 225 for the interrupt has been changed from 0x80800102 to 0x80100102. The GPIROUTIOXAPIC is toggled on which results in the spurious interrupts. The PADCFG0 of PIN 225 is expected to be saved during suspend, but the 297 is saved instead because the gpiochip_line_is_irq() expect the GPIO offset but what's really passed to it is PIN number. In this case, the /sys/kernel/debug/pinctrl/INT3450:00/gpio-ranges shows 288: INT3450:00 GPIOS [436 - 459] PINS [216 - 239] So gpiochip_line_is_irq() returns true for GPIO offset 297, the suspend routine spuriously saves the content for PIN 297 which we expect to save for PIN 225. This commit maps the PIN number to GPIO offset first in the intel_pinctrl_should_save() to make sure the values for the specific PINs can be correctly saved and then restored. Fixes: c538b9436751 ("pinctrl: intel: Only restore pins that are used by the driver") Signed-off-by: Chris Chiu <chiu@endlessm.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Allow to request locked padsAndy Shevchenko2019-08-181-17/+52
| | | | | | | | | | Some firmwares would like to protect pads from being modified by OS and at the same time provide them to OS as a resource. So, the driver in such circumstances may request pad and may not change its state. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Remove dev_err() usage after platform_get_irq()Stephen Boyd2019-08-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Use NSEC_PER_USEC for debounce calculusAndy Shevchenko2019-08-071-4/+5
| | | | | | | | | | Replace hard coded constants with self-explanatory names, i.e. use NSEC_PER_USEC for debounce calculus. While here, add a unit suffix to debounce period constant. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Remove default Interrupt Status offsetAndy Shevchenko2019-08-071-4/+0
| | | | | | | | Since some of the GPIO controllers use different Interrupt Status offset, it make sense to provide it explicitly in the drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Simplify offset validation in intel_get_padcfg()Andy Shevchenko2019-08-071-1/+1
| | | | | | | | There is more generic and simpler validation just against the nregs. Using it allows to drop customization from the intel_get_padcfg(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Drop double check for data in intel_pinctrl_probe_by_uid()Andy Shevchenko2019-07-231-2/+0
| | | | | | | | There is no need to duplicate the check which is done in the common intel_pinctrl_probe(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Use devm_platform_ioremap_resource()Andy Shevchenko2019-07-231-4/+1
| | | | | | | | Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Clear interrupt status in mask/unmask callbackKai-Heng Feng2019-05-201-31/+6
| | | | | | | | | | | | Commit a939bb57cd47 ("pinctrl: intel: implement gpio_irq_enable") was added because clearing interrupt status bit is required to avoid unexpected behavior. Turns out the unmask callback also needs the fix, which can solve weird IRQ triggering issues on I2C touchpad ELAN1200. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Use GENMASK() consistentlyAndy Shevchenko2019-05-201-4/+4
| | | | | | | Use GENMASK() macro for all definitions. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()Andy Shevchenko2019-04-281-2/+4
| | | | | | | | | We better to use usual pattern for read-modify-update, than doing some operations in definition block. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Retain HOSTSW_OWN for requested gpio pinChris Chiu2019-04-281-1/+55
| | | | | | | | | | | | | | | | | | The touchpad of the ASUS laptops E403NA, X540NA, X541NA are not responsive after suspend/resume. The following error message shows after resume. i2c_hid i2c-ELAN1200:00: failed to reset device. On these laptops, the touchpad interrupt is connected via a GPIO pin which is controlled by Intel pinctrl. After system resumes, the GPIO is in ACPI mode and no longer works as an IRQ. This commit saves the HOSTSW_OWN value during suspend, make sure the HOSTSW_OWN mode remains the same after resume. Signed-off-by: Chris Chiu <chiu@endlessm.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: pinctrl-intel: move gpio suspend/resume to noirq phaseBinbin Wu2019-04-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | In current driver, SET_LATE_SYSTEM_SLEEP_PM_OPS is used to install the callbacks for suspend/resume. GPIO pin may be used as the interrupt pin by some device. However, using SET_LATE_SYSTEM_SLEEP_PM_OPS() to install the callbacks, the resume callback is called after resume_device_irqs(). Unintended interrupts may arrive due to resuming device irqs first, but the GPIO controller is not properly restored. Normally, for a SMP system, there are multiple cores, so even when there are unintended interrupts, BSP gets the chance to initialize the GPIO chip soon. But when there is only 1 core is active (other cores are offlined or single core) during resume, it is more easily to observe the unintended interrupts. This patch renames the suspend/resume function by adding suffix "_noirq", and installs the callbacks using SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(). Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Unexport intel_pinctrl_probe()Andy Shevchenko2018-11-081-3/+2
| | | | | | | Since there are no more users, unexport it and make static. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: simplify getting .driver_dataWolfram Sang2018-11-081-4/+2
| | | | | | | | | | We should get 'driver_data' from 'struct device' directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Fix a spelling typo in kernel documentationAndy Shevchenko2018-10-031-1/+1
| | | | | | | | | | | | | | | The parameter 'community' had been spelled incorrectly. Fix it here. As a side effect it satisfies static checkers that issue the following warnings: drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Function parameter or member 'community' not described in 'intel_gpio_to_pin' drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Excess function parameter 'commmunity' description in 'intel_gpio_to_pin' Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Convert unsigned to unsigned intAndy Shevchenko2018-10-031-50/+51
| | | | | | | | Simple type conversion with no functional change implied. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v4.19-rc6' into develLinus Walleij2018-10-011-80/+63
|\ | | | | | | | | | | | | | | | | | | This is the 4.19-rc6 release I needed to merge this in because of extensive conflicts in the MSM and Intel pin control drivers. I know how to resolve them, so let's do it like this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Revert "pinctrl: intel: Do pin translation when lock IRQ"Mika Westerberg2018-09-251-32/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 55aedef50d4d810670916d9fce4a40d5da2079e7. Commit 55aedef50d4d ("pinctrl: intel: Do pin translation when lock IRQ") added special translation from GPIO number to hardware pin number to irq_reqres/relres hooks to avoid failure when IRQs are requested. The actual failure happened inside gpiochip_lock_as_irq() because it calls gpiod_get_direction() and pinctrl-intel.c::intel_gpio_get_direction() implementation originally missed the translation so the two hooks made it work by skipping the ->get_direction() call entirely (it overwrote the default GPIOLIB provided functions). The proper fix that adds translation to GPIO callbacks was merged with commit 96147db1e1df ("pinctrl: intel: Do pin translation in other GPIO operations as well"). This allows us to use the default GPIOLIB provided functions again. In addition as find out by Benjamin Tissoires the two functions (intel_gpio_irq_reqres()/intel_gpio_irq_relres()) now cause problems of their own because they operate on pin numbers and pass that pin number to gpiochip_lock_as_irq() which actually expects a GPIO number. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911 Fixes: 55aedef50d4d ("pinctrl: intel: Do pin translation when lock IRQ") Reported-and-tested-by: Benjamin Tissoires <benjamin.tissoires@gmail.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: intel: Do pin translation in other GPIO operations as wellMika Westerberg2018-09-201-48/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason I thought GPIOLIB handles translation from GPIO ranges to pinctrl pins but it turns out not to be the case. This means that when GPIOs operations are performed for a pin controller having a custom GPIO base such as Cannon Lake and Ice Lake incorrect pin number gets used internally. Fix this in the same way we did for lock/unlock IRQ operations and translate the GPIO number to pin before using it. Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Reported-by: Rajat Jain <rajatja@google.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Rajat Jain <rajatja@google.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Introduce intel_pinctrl_probe_by_hid() internal APIAndy Shevchenko2018-08-311-0/+9
| | | | | | | | | | | | | | | | | | | | Introduce intel_pinctrl_probe_by_hid() internal API to simplify drivers, which are using ACPI _HID to distinguish which SoC data needs to be used when being probed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Introduce intel_pinctrl_probe_by_uid() internal APIAndy Shevchenko2018-08-311-0/+38
| | | | | | | | | | | | | | | | | | | | Introduce intel_pinctrl_probe_by_uid() internal API to simplify drivers, which are using ACPI _UID to distinguish which SoC data needs to be used when being probed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Fix a spelling typo in kernel documentationAndy Shevchenko2018-08-291-1/+1
|/ | | | | | | | | | | | | | | The parameter 'community' had been spelled incorrectly. Fix it here. As a side effect it satisfies static checkers that issue the following warnings: drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Function parameter or member 'community' not described in 'intel_gpio_to_pin' drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Excess function parameter 'commmunity' description in 'intel_gpio_to_pin' Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq()Andy Shevchenko2018-08-031-2/+4
| | | | | | | | | | | | gpiochip_lock_as_irq() may return a few error codes, do not shadow them by -EINVAL and let caller to decide. No functional change intended. Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Do pin translation when lock IRQAndy Shevchenko2018-07-291-0/+30
| | | | | | | | | | | | | Default GPIOLIB callbacks for request and release IRQ do not do a GPIO to pin translation which is necessary for Intel hardware, such as Intel Cannonlake. Absence of the translation prevents some pins to be locked as IRQ due to direction check. Introduce own callbacks to make translation possible to avoid above issue. Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Convert to use SPDX identifierAndy Shevchenko2018-07-021-4/+1
| | | | | | | | | | Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Implement intel_gpio_get_direction callbackJavier Arteaga2018-03-231-0/+19
| | | | | | | | | | Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Signed-off-by: Javier Arteaga <javier@emutex.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: ensure error return ret is initializedColin Ian King2017-12-071-1/+1
| | | | | | | | | | | | | | | In the (unlikely) event that community->ngpps is zero, or if every gpp->gpio_base is less than zero, then an ininitialized value in ret is returned by function intel_gpio_add_pin_ranges. Fix this by ensuring ret is initialized to zero. It's a moot point, but I think it is worthwhile ensuring this corner case is fixed. Detected by CoverityScan, CID#1462415 ("Uninitialized scalar variable") Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Initialize GPIO properly when used through irqchipMika Westerberg2017-12-021-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | When a GPIO is requested using gpiod_get_* APIs the intel pinctrl driver switches the pin to GPIO mode and makes sure interrupts are routed to the GPIO hardware instead of IOAPIC. However, if the GPIO is used directly through irqchip, as is the case with many I2C-HID devices where I2C core automatically configures interrupt for the device, the pin is not initialized as GPIO. Instead we rely that the BIOS configures the pin accordingly which seems not to be the case at least in Asus X540NA SKU3 with Focaltech touchpad. When the pin is not properly configured it might result weird behaviour like interrupts suddenly stop firing completely and the touchpad stops responding to user input. Fix this by properly initializing the pin to GPIO mode also when it is used directly through irqchip. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Reported-by: Daniel Drake <drake@endlessm.com> Reported-and-tested-by: Chris Chiu <chiu@endlessm.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Allow custom GPIO base for pad groupsMika Westerberg2017-11-291-39/+117
| | | | | | | | | | | | | | | | | Currently we always have direct mapping between GPIO numbers and the hardware pin numbers. However, there are cases where that's not the case anymore (more about this in the next patch). Instead we need to be able to specify custom GPIO base for certain pad groups. To support this, add a new field (gpio_base) to the pad group structure and update the core Intel pinctrl driver to handle this accordingly. Passing 0 as gpio_base will use direct mapping so the existing drivers do not need to be modified. Passing -1 excludes the whole pad group from having GPIO mapping. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'gpio-irqchip-rework' of /home/linus/linux-gpio into develLinus Walleij2017-11-091-1/+1
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| * gpio: Move irqdomain into struct gpio_irq_chipThierry Reding2017-11-081-1/+1
| | | | | | | | | | | | | | | | | | In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Make offset to interrupt status register configurableMika Westerberg2017-10-311-8/+12
|/ | | | | | | | | | | Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Read back TX buffer stateAndy Shevchenko2017-08-311-1/+6
| | | | | | | | | | | | In the same way as it's done in pinctrl-cherryview.c we would provide a readback TX buffer state. Fixes: 17fab473693 ("pinctrl: intel: Set pin direction properly") Reported-by: "Bourque, Francis" <francis.bourque@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: "Bourque, Francis" <francis.bourque@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Decrease indentation in intel_gpio_set()Andy Shevchenko2017-08-311-12/+12
| | | | | | | | | Decrease indentation in intel_gpio_set() to make it looking slightly better and be in align with intel_gpio_get(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Disable GPIO pin interrupts in suspendRushikesh S Kadam2017-08-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fix prevents unintended wakes from second level GPIO pin interrupts. On some Intel Kabylake platforms, it is observed that GPIO pin interrupts can wake the platform from suspend-to-idle, even though the IRQ is not configured as IRQF_NO_SUSPEND or enable_irq_wake(). This can cause undesired wakes on Mobile devices such as Laptops and Chromebook devices. For example a headset jack insertion is not a desired wake source on Chromebook devices. The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model. All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or IRQ15). The driver registers an irq_chip struct and maps an irq_domain for the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second level IRQ for the respective pin. In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs that are not marked for wake. The pinctrl-intel driver does not implement a irq_disable() callback (to take advantage of lazy disabling). The pinctrl-intel GPIO interrupts are not disabled in hardware during suspend entry, and thus are able to wake the SoC out of suspend-to-idle. This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to disable the second level interrupts at suspend_noirq stage via the irq_mask callbacks. The irq_mask callback disables the IRQs in hardware by programming the corresponding GPIO pad registers. Only IRQs that are not marked for wake are disabled. Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Make it possible to specify mode per pin in a groupMika Westerberg2017-06-091-1/+5
| | | | | | | | | | On some SoCs not all pins in a group use the same mode when a certain function is muxed out of them. This makes it possible to specify mode per pin as an array instead in addition to single integer. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add support for variable size pad groupsMika Westerberg2017-06-091-52/+142
| | | | | | | | | | | | | | | | | | | | | | | | | The Intel GPIO hardware has a concept of pad groups, which means 1 to 32 pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The existing hardware has the same amount of pads in each pad group (except the last one) so it is possible to use community->gpp_size to calculate start offset of each register. With the next generation SoCs the pad group size is not always the same anymore which means we cannot use community->gpp_size for register offset calculations directly. To support variable size pad groups we introduce struct intel_padgroup that can be filled in by the client drivers according the hardware pad group layout. The core driver will always use these when it performs calculations for pad register offsets. The core driver will automatically populate pad groups based on community->gpp_size if the driver does not provide any. This makes sure the existing drivers still work as expected. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: unlock on error in intel_config_set_pull()Dan Carpenter2017-02-131-2/+4
| | | | | | | | We need to unlock before returning -EINVAL on this error path. Fixes: 04cc058f0c52 ("pinctrl: intel: Add support for 1k additional pull-down") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add support for 1k additional pull-downMika Westerberg2017-01-301-1/+17
| | | | | | | | | The next generation Intel GPIO hardware supports additional 1k pull-down per-pad. Add support for this to the Intel core pinctrl driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add support for hardware debouncerMika Westerberg2017-01-301-2/+128
| | | | | | | | | | | | | | The next generation Intel GPIO hardware has two additional registers PADCFG2 and PADCFG3. The latter is marked as reserved but the former includes configuration for per-pad hardware debouncer. This patch adds support for that in the Intel pinctrl core driver. Since these are additional features on top of the current generation hardware, we use revision number and feature flags to enable this if detected. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v4.10-rc6' into develLinus Walleij2017-01-301-11/+19
|\ | | | | | | | | | | | | | | Linux 4.10-rc6 Resolved conflicts in: drivers/pinctrl/pinctrl-amd.c drivers/pinctrl/samsung/pinctrl-exynos.c
| * pinctrl: intel: Set pin direction properlyAndy Shevchenko2017-01-111-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two bits in the PADCFG0 register to configure direction, one per TX/RX buffers. For now we wrongly assume that the GPIO is always requested before it is being used, which is not true when the GPIO is used through irqchip. In this case the GPIO is never requested and we never enable RX buffer for it. Fix this by setting both bits accordingly. Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Convert to use devm_gpiochip_add_data()Mika Westerberg2017-01-111-19/+4
|/ | | | | | | | | This simplifies error handling and allows us to drop intel_pinctrl_remove() completely. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: set default handler to be handle_bad_irq()Andy Shevchenko2016-12-071-1/+1
| | | | | | | | | We switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Only restore pins that are used by the driverMika Westerberg2016-10-181-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend to explicitly disable USB touchscreen interrupt. This is done to prevent situation where the lid is closed the touchscreen is left functional. The pinctrl driver (wrongly) assumes it owns all pins which are owned by host and not locked down. It is perfectly fine for BIOS to use those pins as it is also considered as host in this context. What happens is that when the lid of Dell XPS 13 is closed, the BIOS configures CPU_GP_1 low disabling the touchscreen interrupt. During resume we restore all host owned pins to the known state which includes CPU_GP_1 and this overwrites what the BIOS has programmed there causing the touchscreen to fail as no interrupts are reaching the CPU anymore. Fix this by restoring only those pins we know are explicitly requested by the kernel one way or other. Cc: stable@vger.kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361 Reported-by: AceLan Kao <acelan.kao@canonical.com> Tested-by: AceLan Kao <acelan.kao@canonical.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 20:58:57 +0000