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path: root/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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* pinctrl: qcom/msm: Convert to platform remove callback returning voidUwe Kleine-König2023-10-101-1/+1
| | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Refactor generic qcom pinctrl driverRohit Agarwal2023-05-161-3/+3
| | | | | | | | | | | | Reuse the generic pingroup struct from pinctrl.h in msm_pingroup along with the macro defined. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Remove the msm_function structRohit Agarwal2023-05-161-53/+45
| | | | | | | | | | | | | Remove the msm_function struct to reuse the generic pinfunction struct. Also, define a generic PINFUNCTION macro that can be used across qcom target specific pinctrl files to avoid code repetition. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: add open drain supportJaiganesh Narayanan2020-07-161-0/+1
| | | | | | | | | | [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based WiFi APs. ] Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lore.kernel.org/r/20200703080646.23233-1-computersforpeace@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner2019-06-051-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* pinctrl: msm: add support to configure ipq40xx GPIO_PULL bitsRam Chandra Jangir2017-08-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO_PULL bits configurations in TLMM_GPIO_CFG register differs for IPQ40xx from rest of the other qcom SoCs. As it does not support the keeper state and therefore can't support bias-bus-hold property. This patch adds a pull_no_keeper setting which configures the msm_gpio_pull bits for ipq40xx. This is required to fix the proper configurations of gpio-pull bits for nand pins mux. IPQ40xx SoC: 2'b10: Internal pull up enable. 2'b11: Unsupport For other SoC's: 2'b10: Keeper 2'b11: Pull-Up Note: Due to pull_no_keeper length, all kerneldoc entries in the msm_pinctrl_soc_data struct had to be realigned. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: add most remaining pin definitionsRam Chandra Jangir2017-08-141-85/+346
| | | | | | | | | | | | | | | | | | | This patch adds multiple pinctrl functions and mappings for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have been missing from the current minimal version. This patch has been updated from the original version that was posted by Ram Chandra Jangir on the LEDE-DEV ML: <https://patchwork.ozlabs.org/patch/752962/>. A short summary of the changes are documented in the device-tree patch of this series: "dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups" Cc: John Crispin <john@phrozen.org> Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: add missing pingroups for pins > 70Christian Lamparter2017-03-231-0/+30
| | | | | | | | | | | This patch adds the missing PINGROUP for GPIO70-99. This fixes a crash that happens in pinctrl-msm, if any of the GPIO70-99 are accessed. Fixes: 5303f7827fcd41d ("pinctrl: qcom: ipq4019: set ngpios to correct value") Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: fix register offsetsMatthew McClintock2016-03-311-5/+5
| | | | | | | | | For this SoC the register offsets changed from previous versions to be separated by a larger amount. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: fix the function enum for gpio modeMatthew McClintock2016-03-311-1/+1
| | | | | | | | | Without this, we would fail to set the mode to gpio if trying to configure for that mode Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: set ngpios to correct valueMatthew McClintock2016-03-311-1/+1
| | | | | | | | | This should have been bumped to 100 when the extra pins were added in the original pinctrl patch Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl supportVaradarajan Narayanan2016-02-161-0/+453
Add pinctrl driver support for IPQ4019 platform Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [Dropped .owner assignment] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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