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* | | pinctrl: Add pinctrl-aspeed-g4 driverAndrew Jeffery2016-09-073-0/+1240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add core support for Aspeed SoCsAndrew Jeffery2016-09-076-0/+1081
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controllerMartin Blumenstingl2016-09-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: zynq: fix typo in sdio1_3_grp pin listDaniel Glöckner2016-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It contains pin 50 instead of pin 40. Signed-off-by: Daniel Glöckner <dg@emlix.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v4.9-tag2' of ↵Linus Walleij2016-09-065-0/+2660
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Add support for R-Car M3-W Add initial support for the Pin Function Controller on the Renesas R-Car M3-W SoC: - Basic definitions, - SCIF (serial) pins, groups and functions, - SDHI pins, groups and functions.
| * | pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functionsTakeshi Kihara2016-08-191-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functionsTakeshi Kihara2016-08-191-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Initial R8A7796 PFC supportTakeshi Kihara2016-08-195-0/+2085
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | | pinctrl: imx: output one pin/config pair per line in pinconf-groupsVladimir Zapolskiy2016-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cat /sys/kernel/debug/pinctrl/${pinctrl}/pinconf-groups output is hardly readable, if a pin group contains more than one pin the output is glued and looks like this: MX6Q_PAD_SD1_DAT0: 0x17071MX6Q_PAD_SD1_CMD: 0x17071MX6Q_PAD_SD1_CLK: 0x17071 Add two space indentation and a new line separator to improve readability of the output. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sirf: make core support explicitly non-modularPaul Gortmaker2016-08-271-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-sirf.o --> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-sirf.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sirf: make atlas7 explicitly non-modularPaul Gortmaker2016-08-271-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-atlas7.o ---> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-atlas7.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: make it explicitly non-modularPaul Gortmaker2016-08-271-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ROCKCHIP drivers/pinctrl/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-gpio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nomadik: make core support explicitly non-modularPaul Gortmaker2016-08-271-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/pinctrl/nomadik/Kconfig:config PINCTRL_NOMADIK drivers/pinctrl/nomadik/Kconfig: bool "Nomadik pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nomadik: make abx500 explicitly non-modularPaul Gortmaker2016-08-271-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: config PINCTRL_ABX500 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_ALIAS is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: mediatek: make mtk-common explicitly non-modularPaul Gortmaker2016-08-271-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/mediatek/pinctrl-mtk-common.o ---> drivers/pinctrl/mediatek/Makefile:obj-y += pinctrl-mtk-common.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. We don't replace module.h with init.h since the file doesn't need that. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson-gxbb: add pins for PWMNeil Armstrong2016-08-241-0/+79
| | | | | | | | | | | | | | | | | | | | | Add support for PWM pins, for EE and AO domains. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v4.9-tag1' of ↵Linus Walleij2016-08-226-53/+3047
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 - Bias and DU support for R-Car H3, - Basic R-Car V2H support, - Cleanups and fixes.
| * | pinctrl: sh-pfc: r8a7795: Add DU supportLaurent Pinchart2016-08-161-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add DU pin groupsSergei Shtylyov2016-08-081-0/+144
| | | | | | | | | | | | | | | | | | | | | Add DU pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add VIN pin groupsSergei Shtylyov2016-08-081-0/+577
| | | | | | | | | | | | | | | | | | | | | | | | Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Fix VI1_D14_G6_Y6 and VI1_D15_G7_Y7 pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795Geert Uytterhoeven2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sh-pfc: r8a7792: Add CAN pin groupsSergei Shtylyov2016-08-081-0/+37
| | | | | | | | | | | | | | | | | | | | | Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add SDHI pin groupsSergei Shtylyov2016-08-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groupsSergei Shtylyov2016-08-081-0/+99
| | | | | | | | | | | | | | | | | | | | | Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Add R8A7792 PFC supportSergei Shtylyov2016-08-085-6/+1747
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PFC support for the R8A7792 SoC including pin groups for some on-chip devices such as SCIF, INTC, and LBSC... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: s/LSBC/LBSC/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Fix overly long linesSergei Shtylyov2016-08-081-40/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PORT_GP_CFG_<n>() macros take up more than 80 columns -- and not for a good reason. Make the header file checkpatch.pl-proof at least in this respect... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Add bias pinconf supportUlrich Hecht2016-08-081-12/+242
| |/ | | | | | | | | | | | | | | Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | pinctrl: amlogic: gxbb: add the IR remote input pinMartin Blumenstingl2016-08-221-0/+8
| | | | | | | | | | | | | | | | This adds the IR remote receiver to the AO domain devices. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: palmas: fix a possible NULL dereferenceLABBE Corentin2016-08-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | of_match_device could return NULL, and so cause a NULL pointer dereference later at line 1009: pinctrl_data = match->data; For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Reported-by: coverity (CID 1324136) Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: exynos: remove duplicate calls in irq handlerperr perr2016-08-221-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Because chained_irq_enter() has already called chip->irq_mask() and chip->irq_ack(), also chained_irq_exit() will call chip->irq_unmask(), so it's not necessary to call chip->irq_*() here. Signed-off-by: Perr Zhang <strongbox8@zoho.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [Hand-edited from whitespace damaged patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: get rid of unneeded domain structuresBeniamino Galvani2016-08-225-228/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver originally supported more domains (register ranges) per pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make driver independent from two-domain configuration") each device gets assigned a single domain and we instantiate multiple pinctrl devices in the DT. Therefore, now the 'meson_domain' and 'meson_domain_data' structures don't have any reason to exist and can be removed to make the model simpler to understand. This commit doesn't change behavior. Tested on a Odroid-C2. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: st: Use second parameter to gpio specifierPatrice Chotard2016-08-111-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to use the second parameter of gpio specifier, which is used to specify whether the gpio is active high or low. Simply remove specific of_xlate callback() and of_gpio_n_cells and use default one set by of_gpiochip_add() which allows to use second parameter gpio specifier. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: use of_property_read_boolJulia Lawall2016-08-111-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e1,e2,x; @@ - if (of_get_property(e1,e2,NULL)) - x = true; - else - x = false; + x = of_property_read_bool(e1,e2); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindingsStephen Boyd2016-08-112-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The drivers don't really need to know which PMIC they're for, so make a generic binding for them. This alleviates us from updating the drivers every time a new PMIC comes out. It's still recommended that we update the binding with new PMIC models and always specify the specific model for the MPPs and gpios before the generic compatible string in devicetree, but this at least cuts down on adding more and more compatible strings to the drivers until we actually need them. Cc: <devicetree@vger.kernel.org> Acked-by: "Ivan T. Ivanov" <iivanov.xz@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sun6i: add SPDIF to pin description.Marcus Cooper2016-08-111-2/+10
|/ | | | | | | | | Add the SPDIF mux functionality to the pinctrl for the Allwinner A31 SoC. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.8-1' of ↵Linus Torvalds2016-07-28105-2681/+10726
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.8 kernel cycle. Nothing stands out as especially exiting: new drivers, new subdrivers, lots of cleanups and incremental features. Business as usual. New drivers: - New driver for Oxnas pin control and GPIO. This ARM-based chipset is used in a few storage (NAS) type devices. - New driver for the MAX77620/MAX20024 pin controller portions. - New driver for the Intel Merrifield pin controller. New subdrivers: - New subdriver for the Qualcomm MDM9615 - New subdriver for the STM32F746 MCU - New subdriver for the Broadcom NSP SoC. Cleanups: - Demodularization of bool compiled-in drivers. Apart from this there is just regular incremental improvements to a lot of drivers, especially Uniphier and PFC" * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits) pinctrl: fix pincontrol definition for marvell pinctrl: xway: fix typo Revert "pinctrl: amd: make it explicitly non-modular" pinctrl: iproc: Add NSP and Stingray GPIO support pinctrl: Update iProc GPIO DT bindings pinctrl: bcm: add OF dependencies pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe() pinctrl: Add STM32F746 MCU support pinctrl: intel: Protect set wake flow by spin lock pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe() pinctrl: uniphier: add Ethernet pin-mux settings sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code pinctrl: ns2: fix return value check in ns2_pinmux_probe() pinctrl: qcom: update DT bindings with ebi2 groups pinctrl: qcom: establish proper EBI2 pin groups pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro Documentation: dt: Add new compatible to STM32 pinctrl driver bindings includes: dt-bindings: Add STM32F746 pinctrl DT bindings pinctrl: sunxi: fix nand0 function name for sun8i pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 ...
| * pinctrl: fix pincontrol definition for marvellAndreas Klinger2016-07-241-42/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Marvell mv88f6180 with pin control driver one can not use multi purpose pins 35 through 44. I'm using this controller on an embedded board and i found that the pin multiplexing is not the same as in the hardware spezification. This patch alters the pin description so that mpp pins 0 to 19 as well as 35 to 44 are usable. Pin settings i used can be found here: http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf Signed-off-by: Andreas Klinger <ak@it-klinger.de> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: xway: fix typoLinus Walleij2016-07-221-1/+1
| | | | | | | | | | | | | | | | | | A typo in the previous commit to this file needs fixing. Cc: Amitoj Kaur Chawla <amitoj1606@gmail.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Fixes: 6b4316aecec0 ("pinctrl: xway: Change structure initialisation to c99 style") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Revert "pinctrl: amd: make it explicitly non-modular"Paul Gortmaker2016-07-221-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b8c2b10a9bc0272a20e096852f8fbbf361749dda. This patch was in my queue at the same time that a conversion of the same driver from bool --> tristate was pending and merged. That is commit 337ea0fb1535 ("pinctrl: Turn AMD support to tristate") Normally the conflict would show up in the build coverage I do, however in this case an avoidable instance of linux/module.h in linux/gpio/driver.h (!) causes the build failure to be masked and instead the tristate gets built-in even for selected "=m". In working on removing module.h from driver.h this issue was then revealed (along with other implicit module.h assumptions in gpio, and mfd -- which will be fixed separately.) Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: iproc: Add NSP and Stingray GPIO supportRay Jui2016-07-221-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iProc GPIO controller is shared among multiple iProc based SoCs. In the NSP integration, the drive strength pinctrl function is disabled. In the integration of Stingray, pinctrl is handled by another block and this GPIO controller is solely used as a GPIO controller, and therefore should not be registered to the pinconf framework This patch introduces new SoC specific compatible strings "brcm,iproc-nsp-gpio" for NSP with drive strength feature disabled and "brcm,iproc-stingray-gpio" for Stingray with all PINCONF features disabled This patch is developed based on the initial work from Yendapally Reddy Dhananjaya <yendapally.reddy@broadcom.com> who attempted to disable drive strength configuration for the iProc based NSP chip. In addition, Pramod Kumar <pramod.kumar@broadcom.com> also contributed to make the support more generic across all currently supported PINCONF functions in the iProc GPIO/PINCONF driver Signed-off-by: Pramod Kumar <pramodku@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm: add OF dependenciesArnd Bergmann2016-07-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building without CONFIG_OF gives us these warnings for the broadcom pinctrl drivers: drivers/pinctrl/bcm/pinctrl-nsp-mux.c:356:20: error: 'pinconf_generic_dt_node_to_map_group' undeclared here (not in a function) drivers/pinctrl/bcm/pinctrl-cygnus-mux.c:739:20: error: 'pinconf_generic_dt_node_to_map_group' undeclared here (not in a function) The function is only available when CONFIG_OF is set, so we should add a Kconfig dependency for both drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: cc4fa83f66e9 ("pinctrl: nsp: add pinmux driver support for Broadcom NSP SoC") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()Wei Yongjun2016-07-221-6/+2
| | | | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Add STM32F746 MCU supportAlexandre TORGUE2016-07-113-0/+1688
| | | | | | | | | | | | | | | | | | This patch which adds STM32F746 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: intel: Protect set wake flow by spin lockAndy Shevchenko2016-07-111-0/+5
| | | | | | | | | | | | | | | | | | It seems intel_gpio_irq_wake() misses lock protection against I/O flow. Use spin lock here as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()Wei Yongjun2016-07-111-6/+2
| | | | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-117-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the following Ethernet interfaces: PH1-LD4: MII, RMII PH1-Pro4: MII, RMII, RGMII PH1-sLD8: MII, RMII (Built-in PHY is also supported) ProXstream2: MII, RMII, RGMII PH1-LD6b: RMII, RGMII PH1-LD11: RMII (Built-in PHY is also supported) PH1-LD20: RMII, RGMII Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the codeWei Yongjun2016-07-111-4/+1
| | | | | | | | | | | | | | | | Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ns2: fix return value check in ns2_pinmux_probe()Wei Yongjun2016-07-111-2/+2
| | | | | | | | | | | | | | | | | | In case of error, the function pinctrl_register() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: establish proper EBI2 pin groupsLinus Walleij2016-07-081-22/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After some digging around I found documentation (!) of the APQ8060 EBI2 pin groups. It turns out I first need to split the group in two: ebi2cs and ebi2 proper. The chip select pins are kind of orthogonal to the other EBI2 pins since CS1B and CS2B can be muxed over address bits 7 and 6 (don't know why, but they can). This is good to fix up before we add users. Also found what the "holes" in the assignment all the way up to gpio158 was actually for. All mux documentation comes from "Snapdragon(TM) S3 APQ8060-based DragonBoard(TM) GPIO User Guide Rev. E August 10, 2012", published by Bsquare Corporation. As the documentation seems a bit hard to come by I put some comments in the group definitions so that it is clear to all readers what is going on here and what the lines are used for. Cc: Björn Andersson <bjorn.andersson@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macroFabio Estevam2016-07-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e2756baa4217 ("pinctrl: imx21: make it explicitly non-modular") missed the removal of the MODULE_DEVICE_TABLE() macro causing the following build error: drivers/pinctrl/freescale/pinctrl-imx21.c:328:1: error: data definition has no type or storage class [-Werror] MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match); ,so remove the macro to fix this problem. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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