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* pinctrl: rockchip: add pinmux_ops.gpio_set_direction callbackQuentin Schulz2022-10-211-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | commit 4635c0e2a7f7f3568cbfccae70121f9835efa62c upstream. Before the split of gpio and pinctrl sections in their own driver, rockchip_set_mux was called in pinmux_ops.gpio_set_direction for configuring a pin in its GPIO function. This is essential for cases where pinctrl is "bypassed" by gpio consumers otherwise the GPIO function is not configured for the pin and it does not work. Such was the case for the sysfs/libgpiod userspace GPIO handling. Let's re-implement the pinmux_ops.gpio_set_direction callback so that the gpio subsystem can request from the pinctrl driver to put the pin in its GPIO function. Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20220930132033.4003377-2-foss+kernel@0leil.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* pinctrl: ocelot: Fix interrupt controllerHoratiu Vultur2022-09-141-14/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an external device generated a level based interrupt then the interrupt controller could miss the interrupt. The reason is that the interrupt controller can detect only link changes. In the following example, if there is a PHY that generates an interrupt then the following would happen. The GPIO detected that the interrupt line changed, and then the 'ocelot_irq_handler' was called. Here it detects which GPIO line saw the change and for that will call the following: 1. irq_mask 2. phy interrupt routine 3. irq_eoi 4. irq_unmask And this works fine for simple cases, but if the PHY generates many interrupts, for example when doing PTP timestamping, then the following could happen. Again the function 'ocelot_irq_handler' will be called and then from here the following could happen: 1. irq_mask 2. phy interrupt routine 3. irq_eoi 4. irq_unmask Right before step 3(irq_eoi), the PHY will generate another interrupt. Now the interrupt controller will acknowledge the change in the interrupt line. So we miss the interrupt. A solution will be to use 'handle_level_irq' instead of 'handle_fasteoi_irq', because for this will change routine order of handling the interrupt. 1. irq_mask 2. irq_ack 3. phy interrupt routine 4. irq_unmask And now if the PHY will generate a new interrupt before irq_unmask, the interrupt controller will detect this because it already acknowledge the change in interrupt line at step 2(irq_ack). But this is not the full solution because there is another issue. In case there are 2 PHYs that share the interrupt line. For example phy1 generates an interrupt, then the following can happen: 1.irq_mask 2.irq_ack 3.phy0 interrupt routine 4.phy1 interrupt routine 5.irq_unmask In case phy0 will generate an interrupt while clearing the interrupt source in phy1, then the interrupt line will be kept down by phy0. So the interrupt controller will not see any changes in the interrupt line. The solution here is to update 'irq_unmask' such that it can detect if the interrupt line is still active or not. And if it is active then call again the procedure to clear the interrupts. But we don't want to do it every time, only if we know that the interrupt controller has not seen already that the interrupt line has changed. While at this, add support also for IRQ_TYPE_LEVEL_LOW. Fixes: be36abb71d878f ("pinctrl: ocelot: add support for interrupt controller") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220909145942.844102-1-horatiu.vultur@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Fix name for A100 R_PIOMichael Wu2022-08-261-1/+1
| | | | | | | | | | | The name of A100 R_PIO driver should be sun50i-a100-r-pinctrl, not sun50iw10p1-r-pinctrl. Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller") Signed-off-by: Michael Wu <michael@allwinnertech.com> Acked-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220819024541.74191-1-michael@allwinnertech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: sc8180x: Fix wrong pin numbersMolly Sophia2022-08-221-4/+4
| | | | | | | | | | | | The pin numbers for UFS_RESET and SDC2_* are not consistent in the pinctrl driver for sc8180x. So fix it. Signed-off-by: Molly Sophia <mollysophia379@gmail.com> Fixes: 97423113ec4b ("pinctrl: qcom: Add sc8180x TLMM driver") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220807122645.13830-3-mollysophia379@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: sc8180x: Fix gpio_wakeirq_mapMolly Sophia2022-08-221-1/+1
| | | | | | | | | | | | | Currently in the wakeirq_map, gpio36 and gpio37 have the same wakeirq number, resulting in gpio37 being unable to trigger interrupts. It looks like that this is a typo in the wakeirq map. So fix it. Signed-off-by: Molly Sophia <mollysophia379@gmail.com> Fixes: 97423113ec4b ("pinctrl: qcom: Add sc8180x TLMM driver") Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220807122645.13830-2-mollysophia379@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v6.0-1' of ↵Linus Torvalds2022-08-1063-558/+11183
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ...
| * pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSMJohn Garry2022-08-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | All the many other configs depend on config PINCTRL_MSM, yet for config PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450 depend on PINCTRL_MSM to be consistent with the rest. Signed-off-by: John Garry <john.garry@huawei.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sm8250: Fix PDC mapJianhua Lu2022-08-031-1/+1
| | | | | | | | | | | | | | | | | | | | Fix the PDC mapping for SM8250, gpio39 is mapped to irq73(not irq37). Fixes: b41efeed507a("pinctrl: qcom: sm8250: Specify PDC map.") Signed-off-by: Jianhua Lu <lujianhua000@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220803015645.22388-1-lujianhua000@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: amd: Fix an unused variableMario Limonciello2022-08-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | `char *output_enable` is no longer used once switching to unicode output. Fixes: e8129a076a50 ("pinctrl: amd: Use unicode for debugfs output") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220801144952.141-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: amd: Use unicode for debugfs outputMario Limonciello2022-07-261-58/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The output is currently split across two lines making it more difficult to parse unless the newlines are removed between pins or it's read in by a parser like Libreoffice Calc or Google docs. To make it easier to follow to the naked eye in a terminal window: * drop the newline in the middle of pin definitions * shorten all output using unicode characters * align all pipe delimitters * output the same phrase even for disabled functions (but with a ∅ character) Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220722220810.28894-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: amd: Fix newline declaration in debugfs outputMario Limonciello2022-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently the debugfs output for pinctrl-amd puts the first line combined with "GPIO bank". This makes it a little harder to process as the file needs to be manually corrected for the mistake. Change this to be a new line character instead. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220722220810.28894-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: Fix typo 'the the' in commentSlark Xiao2022-07-261-1/+1
| | | | | | | | | | | | | | | | Replace 'the the' with 'the' in the comment. Signed-off-by: Slark Xiao <slark_xiao@163.com> Link: https://lore.kernel.org/r/20220722092419.77052-1-slark_xiao@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mvebu: Missing a blank line after declarations.Xin Gao2022-07-261-0/+10
| | | | | | | | | | | | | | | | Missing a blank line after declarations. Signed-off-by: Xin Gao <gaoxin@cdjrlc.com> Link: https://lore.kernel.org/r/20220719182647.9038-1-gaoxin@cdjrlc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add SM6375 TLMM driverKonrad Dybcio2022-07-263-0/+1554
| | | | | | | | | | | | | | | | | | Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"Linus Walleij2022-07-181-12/+10
| | | | | | | | | | | | | | | | This reverts commit 7542766e78fc374d81d8c2db214c4b4308645277. It was noted during follow-up that the approach is incorrect. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx93: Add MODULE_DEVICE_TABLE()Fabio Estevam2022-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Pass MODULE_DEVICE_TABLE() so that module autoloading can work. This also aligns with the other i.MX8 pinctrl drivers. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220712115154.2348971-1-festevam@denx.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Add driver for Allwinner D1Samuel Holland2022-07-185-5/+863
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Make some layout parameters dynamicSamuel Holland2022-07-182-18/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. In order to support multiple register layouts, some of the layout parameters need to be set based on the pinctrl variant. This requires passing the pinctrl struct pointer to the register/offset calculation functions. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-6-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Refactor register/offset calculationSamuel Holland2022-07-182-123/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. As a first step to support this, combine the register and offset calculation functions, and refactor the math to depend on one constant for field widths instead of three. This minimizes the code size impact of making some of the factors dynamic. While rewriting these functions, move them to the implementation file, since that is the only file where they are used. And make the comment more generic, without mentioning specific offsets/sizes. The callers are updated to expect a shifted mask, and to use consistent terminology (reg/shift/mask/val). Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-5-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Support the 2.5V I/O bias modeSamuel Holland2022-07-185-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Add I/O bias setting for H6 R-PIOSamuel Holland2022-07-182-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6") Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom-pmic-gpio: add support for PMP8074Robert Marko2022-07-181-0/+2
| | | | | | | | | | | | | | | | PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. Signed-off-by: Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Add pm8226 compatibilityDominik Kobinski2022-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add support for pm8226 SPMI GPIOs. The PMIC features 8 GPIOs, with no holes inbetween. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com> Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: core: Use device_match_of_node() helperAndy Shevchenko2022-07-181-1/+1
| | | | | | | | | | | | | | | | Instead of open coding, use device_match_of_node() helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: remove #ifdef CONFIG_PMClaudiu Beznea2022-07-181-7/+1
| | | | | | | | | | | | | | | | Remove #ifdef CONFIG_PM and use pm_ptr() macro instead. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91-pio4: remove #ifdef CONFIG_PM_SLEEPClaudiu Beznea2022-07-181-6/+1
| | | | | | | | | | | | | | | | Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704101253.808519-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add pinctrl driver for MSM8909Stephan Gerhold2022-07-113-0/+965
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: starfive: Serialize adding groups and functionsJianlong Huang2022-07-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The pinctrl dt_node_to_map method may be called in parallel which leads us to call pinconf_generic_add_group and pinconf_generic_add_function in parallel. This is not supported though and leads to errors, so add a mutex to serialize these calls. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220627085333.1774396-1-emil.renner.berthing@canonical.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'renesas-pinctrl-for-v5.20-tag2' of ↵Linus Walleij2022-07-107-4/+5414
| |\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.20 (take two) - Add support for the RZ/V2M and R-Car V4H SoCs, - Miscellaneous fixes and improvements.
| | * pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBxKuninori Morimoto2022-07-051-28/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0Kuninori Morimoto2022-07-051-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | TSN0 needs MODSEL4 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87letdsj8e.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing ERROROUTC_AKuninori Morimoto2022-07-051-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing ERROROUTC_A settings. Current existing ERROROUTC should be _B, this patch tidies it up. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing PWMKuninori Morimoto2022-07-051-56/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed. This patch adds missing PWM settings, and tidies these up. According to Document, GP3_14 Function4 is PWM2_A, but we can't select it at P1SR3[27:24]. This patch just ignore it for now. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing FlexRayKuninori Morimoto2022-07-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing FlexRay pins. Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B), this patch names them as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing TPU0TOx_AKuninori Morimoto2022-07-051-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing TPU0TOx_A. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing CANFD5_BKuninori Morimoto2022-07-051-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing CANFD5_B. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87sfnlsj9t.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing SCIF1_XKuninori Morimoto2022-07-051-8/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing SCIF1_X. Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing SCIF3Kuninori Morimoto2022-07-051-18/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed. This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing HSCIF1_XKuninori Morimoto2022-07-051-8/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing HSCIF1. Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing HSCIF3_AKuninori Morimoto2022-07-051-8/+48
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing HSCIF3_A. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87y1xdsjar.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_BKuninori Morimoto2022-07-051-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing IRQx_A/IRQx_B, and tidies up existing IRQs. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87zghtsjb4.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_XKuninori Morimoto2022-07-051-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X. Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B), this patch names them as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Tidyup POC1 voltageKuninori Morimoto2022-07-051-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx, GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28. According to the HW team, there are no bits assigned. This patch follows HW team's comment. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Tidy up ioctrl_regsKuninori Morimoto2022-07-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove POC2 which is not documented, and remove TD0SEL3 which is not needed. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/874k01txy9.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Remove unused MOD_SELx definitionsKuninori Morimoto2022-07-051-54/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Current R-Car V4H PFC code has many MOD_SELx definitions with all 0. But these have no meaning. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitionsKuninori Morimoto2022-07-051-45/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Current R-Car V4H PFC code has many IPxSRx definitions with all 0. But these have no meaning. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Remove unused NOGP definitionsKuninori Morimoto2022-07-051-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current R-Car V4H PFC code has many NOGP definitions. But these are not used, and they are different from original usage. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Fixup MODSEL8Kuninori Morimoto2022-07-051-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is indicating that I2C needs 1. But we should use 0 for all cases in reality. New Datasheet should be updated. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: r8a779g0: Add pins, groups and functionsPhong Hoang2022-07-051-1/+1619
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, MSIOF, PWM, CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: CongDang <cong.dang.xn@renesas.com> Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> [Morimoto: merged above patches into one, cleanup white space, sort modules alphabetically, fixup comments] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87bku9ty0b.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC supportLUU HOAI2022-07-055-0/+2479
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial pinctrl support for the R-Car V4H (R8A779G0) SoC, including bias, drive strength and voltage control. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-25 02:55:07 +0000