summaryrefslogtreecommitdiffstats
path: root/drivers/soc/imx/gpcv2.c
Commit message (Collapse)AuthorAgeFilesLines
* soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/nLi Jun2022-10-291-0/+3
| | | | | | | | | To keep the power domain on if usb remote wakeup is enabled, add the GENPD_FLAG_ACTIVE_WAKEUP for otg1/2 of imx8mm/n. Signed-off-by: Li Jun <jun.li@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Assert reset before ungating clockMarek Vasut2022-08-211-1/+4
| | | | | | | | | | | | | | In case the power domain clock are ungated before the reset is asserted, the system might freeze completely. This is likely due to a device is an undefined state being attached to bus, which sporadically leads to a bus hang. Assert the reset before the clock are enabled to assure the device is in defined state before being attached to bus. Fixes: fe58c887fb8ca ("soc: imx: gpcv2: add support for optional resets") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: print errno for regulator errorsMartin Kepplinger2022-06-191-2/+6
| | | | | | | | Make debugging of power management issues easier by printing the reason why a regulator fails to be enabled or disabled. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add support for i.MX8MP power domainsLucas Stach2022-04-081-1/+386
| | | | | | | | | | | This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add PGC control register indirectionLucas Stach2022-04-081-11/+32
| | | | | | | | | | | The PGC control registers in the shared (not per-PGC) region of the GPC address space have different offsets on i.MX8MP to make space for additional interrupt control registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Fix clock disabling imbalance in error pathLaurent Pinchart2022-02-211-1/+2
| | | | | | | | | | | | | The imx_pgc_power_down() starts by enabling the domain clocks, and thus disables them in the error path. Commit 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") made the clock enable conditional, but forgot to add the same condition to the error path. This can result in a clock enable/disable imbalance. Fix it. Fixes: 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Add dispmix and mipi domains to imx8mnAdam Ford2021-12-171-0/+25
| | | | | | | | | The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabledAdam Ford2021-12-171-0/+1
| | | | | | | | | Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock activeAdam Ford2021-11-231-0/+1
| | | | | | | | | | Enable the vpu-h1 clock when the domain is active because reading or writing to the VPU-H1 IP block cause the system to hang. Fixes: 656ade7aa42a ("soc: imx: gpcv2: keep i.MX8M* bus clocks enabled") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Synchronously suspend MIX domainsMarek Vasut2021-11-211-1/+1
| | | | | | | | | | | | | | | | | | In case the following power domain sequence happens, iMX8M Mini always hangs: gpumix:on -> gpu:on -> gpu:off -> gpu:on This is likely due to another quirk of the GPC block. This situation can be prevented by always synchronously powering off both the domain and MIX domain. Make it so. This turns the aforementioned sequence into: gpumix:on -> gpu:on -> gpu:off -> gpumix:off -> gpumix:on -> gpu:on Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: support system suspend/resumeLucas Stach2021-10-061-0/+31
| | | | | | | | | | | | | | | | | Our usage of runtime PM to control the hierarchy of power domains is slightly unusual and means that powering up a domain may fail in early system resume, as runtime PM is still disallowed at this stage. However the system suspend/resume path takes care of powering down/up the power domains in the order defined by the device parent/child and power-domain provider/consumer hierarachy. So we can just runtime resume all our power-domain devices to allow the power-up to work properly in the resume path. System suspend will still disable all domains as intended. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: keep i.MX8M* bus clocks enabledLucas Stach2021-10-061-0/+6
| | | | | | | | | Annotate the domains with bus clocks to keep those clocks enabled as long as the domain is active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add domain option to keep domain clocks enabledLucas Stach2021-10-061-5/+9
| | | | | | | | | | | | Some of the MIX domains are using clocks to drive the bus bridges. Those must be enabled at all times, as long as the domain is powered up and they don't have any other consumer than the power domain. Add an option to keep the clocks attached to a domain enabled as long as the domain is power up and only disable them after the domain is powered down. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add lockdep annotationLucas Stach2021-10-061-0/+4
| | | | | | | | | | | | | Some of the GPCv2 power domains are nested inside each other without visibility to lockdep at the genpd level, as they are in separate driver instances and don't have a parent/child power-domain relationship. Add a subclass annotation to the nested domains to let lockdep know that it is okay to take the genpd lock in a nested fashion. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"Lucas Stach2021-10-051-2/+2
| | | | | | | | | | | | | | This reverts commit a77ebdd9f553. It turns out that the VPU domain has no different requirements, even though the downstream ATF implementation seems to suggest otherwise. Powering on the domain with the reset asserted works fine. As the changed sequence has caused sporadic issues with the GPU domains, just revert the change to go back to the working sequence. Cc: <stable@vger.kernel.org> # 5.14 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Peng Fan <peng.fan@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: allow to disable individual power domainsLucas Stach2021-10-051-0/+3
| | | | | | | | | | | | | | Some board designs don't supply power to all of the power domains, as they are not used anyways. In that case we must make sure to not touch those power domains at all, as trying to power up a domain that has no power supplied to it will obviously end in a system crash. Allow to disable those domains via the standard DT status property. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-By: Tim Harvey <tharvey@gateworks.com> Tested-By: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domainMarek Vasut2021-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | To bring up the MX8MM GPU domain, it is necessary to configure both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without this configuration, the system might hang on boot when bringing up the GPU power domain. This is sporadically observed on multiple disparate systems. Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are configured when bringing up the GPU domain. This fixes the sporadic hang. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Turn domain->pgc into bitfieldMarek Vasut2021-10-041-34/+38
| | | | | | | | | | | | | | | | | | | | | | | There is currently the MX8MM GPU domain, which is in fact a composite domain for both GPU2D and GPU3D. To correctly configure this domain, it is necessary to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. Turn the domain->pgc from value into bitfield and use for_each_set_bit() to iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL register array. This way it is possible to configure all GPC_PGC_nCTRL registers required in a particular domain. This is a preparatory patch, no functional change. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add support for i.MX8MN power domainsAdam Ford2021-06-121-0/+92
| | | | | | | | | | | This adds support for the power domains founds on i.MX8MN. The Nano has fewer domains than the Mini, and the access to some of these domains is different than that of the Mini, the Mini power domains cannot be reused. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: move reset assert after requesting domain power upPeng Fan2021-05-271-2/+2
| | | | | | | | | | | | | | | | The i.MX8MM VPU power up sequence is a bit special, it must follow: 1. request power up 2. reset assert 3. reset deassert This change in this patch will not affect other domains, because the power domain default is in asserted state, unless bootloader deassert the reset. It also applies to GPU power domain. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX power domainsLucas Stach2021-05-271-0/+70
| | | | | | | | | | With the BLK-CTL driver now in place, let's add the missing domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add support for i.MX8MM power domainsLucas Stach2021-05-271-0/+168
| | | | | | | | | | | | This adds support for the power domains found on i.MX8MM. The 2D and 3D GPU domains are abstracted as a single domain in the driver, as they can't be powered up/down individually due to a shared reset. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add support for optional resetsLucas Stach2021-05-231-0/+14
| | | | | | | | | | | | | | | Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: allow domains without power-sequence controlLucas Stach2021-05-231-40/+49
| | | | | | | | | | | | | Some of the PGC domains only control the handshake with the ADB400 and don't have any power sequence controls. Make such domains work by allowing the pxx and map bits to be empty and skip all actions using those controls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add runtime PM support for power-domainsLucas Stach2021-05-231-1/+17
| | | | | | | | | | | This allows to nest domains into other power domains and have the parent domain powered up/down as required by the child domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: wait for ADB400 handshakeLucas Stach2021-05-231-8/+39
| | | | | | | | | | | | | | | | New reference manuals show that there is actually a status bit for the ADB400 handshake. Add a poll loop to wait for the ADB400 to acknowledge our request. [Peng Fan: i.MX8MM has blk ctl module, the handshake can only finish after setting blk ctl. The blk ctl driver will set the bus clk bit and the handshake will finish there. we just add a delay and suppose the handshake will finish after that.] Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: split power up and power down sequence controlLucas Stach2021-05-231-55/+86
| | | | | | | | | | | | | | The current mixed function to control both power up and power down sequences is very hard to follow and already contains some sequence errors like triggering the ADB400 handshake at the wrong time due to this. Split the function into two, which results in slightly more code, but is way easier to get right. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: switch to clk_bulk_* APILucas Stach2021-05-231-48/+12
| | | | | | | | | | | Use clk_bulk API to simplify the code a bit. Also add some error checking to the clk_prepare_enable calls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: move domain mapping to domain driver probeLucas Stach2021-05-231-9/+13
| | | | | | | | | | | | | As long as the power domain driver is active we want power control over the domain (which is what the mapping bit requests), so there is no point in whacking it for every power control action, simply set the bit in driver probe and clear it when the driver is removed. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: move to more ideomatic error handling in probeLucas Stach2021-05-231-4/+9
| | | | | | | | | | | | | Switch to "goto out..." error handling in domain driver probe to avoid repeating all the error paths. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Use dev_err_probe() to simplify error handlingAnson Huang2020-08-221-10/+5
| | | | | | | | | dev_err_probe() can reduce code size, uniform error handling and record the defer probe reason etc., use it to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: include linux/sizes.hLeonard Crestez2020-02-141-0/+1
| | | | | | | | This header is included indirectly on arm/arm64 but not on x86 so CONFIG_COMPILE_TEST breaks. Fix by including <linux/sizes.h> directly. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Print the correct error codeGuido Günther2019-08-241-1/+1
| | | | | | | | The current code prints 'ret' (thus 0) while it should use 'err'. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: use devm_platform_ioremap_resource() to simplify codeAnson Huang2019-04-111-3/+1
| | | | | | | | | | Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Make use of regmap_read_poll_timeout()Andrey Smirnov2019-03-191-25/+14
| | | | | | | | | | | | | | Replace explicit polling loop with a call to regmap_read_poll_timeout() to avoid code repetition. Also fix misspelled "failed" while at it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Chris Healy <cphealy@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: handle reset clocksLucas Stach2019-01-111-1/+59
| | | | | | | | | | Some power domains handled by the GPCv2 driver need to enable the clocks for devies inside the domain, so that the reset propagation and proper power-up sequencing happens. Handle them in the same way as on GPCv1. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: handle additional power-down bits in handshake registerLucas Stach2019-01-111-1/+15
| | | | | | | | | | | | | Some of the i.MX8MQ domains have an additional control bit in the PU handshake (HSK) register. Documentation about this bit is a bit sparse at the moment, but it seems that it controls a power-down request to the AMBA domain bridge (ADB-400) attached to those domains. As the documentation doesn't desribe the usage of this bit yet, handle it in the same way as done in the ATF implementation. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add support for i.MX8MQ SoCLucas Stach2018-12-051-1/+207
| | | | | | | | | | The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: move register access table to domain dataLucas Stach2018-12-051-20/+24
| | | | | | | | The valid register ranges are defined by the implemented power domains, which are different between the individual SoCs where the GPCv2 is used. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: prefix i.MX7 specific definesLucas Stach2018-12-051-28/+28
| | | | | | | So we can add i.MX8M support without introducing name clashes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Switch to SPDX identifierFabio Estevam2018-10-011-7/+1
| | | | | | | | Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: make pgc driver more generic for other i.MX platformsAnson Huang2018-10-011-29/+43
| | | | | | | | | | | | | | i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they can reuse gpcv2 pgc driver for power domain control, this patch renames all functions and structure definitions started with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to pass platform specific power domain data for power domain driver, thus make gpcv2 pgc driver more generic for i.MX platforms. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platformsAnson Huang2018-10-011-10/+10
| | | | | | | | | | gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7 cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53 cores, so let's use A_CORE instread of A7 to avoid confusion. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: correct PGC offsetAnson Huang2018-06-171-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | Correct MIPI/PCIe/USB_HSIC's PGC offset based on design RTL, the values in the Reference Manual (Rev. 1, 01/2018 and the older ones) are incorrect. The correct offset values should be as below: 0x800 ~ 0x83F: PGC for core0 of A7 platform; 0x840 ~ 0x87F: PGC for core1 of A7 platform; 0x880 ~ 0x8BF: PGC for SCU of A7 platform; 0xA00 ~ 0xA3F: PGC for fastmix/megamix; 0xC00 ~ 0xC3F: PGC for MIPI PHY; 0xC40 ~ 0xC7F: PGC for PCIe_PHY; 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY; 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY; 0xD00 ~ 0xD3F: PGC for USB HSIC PHY; Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Do not pass static memory as platform dataAndrey Smirnov2018-04-231-7/+15
| | | | | | | | | | | | | | | | | | | | | Platform device core assumes the ownership of dev.platform_data as well as that it is dynamically allocated and it will try to kfree it as a part of platform_device_release(). Change the code to use platform_device_add_data() n instead of a pointer to a static memory to avoid causing a BUG() when calling platform_device_put(). The problem can be reproduced by artificially enabling the error path of platform_device_add() call (around line 357). Note that this change also allows us to constify imx7_pgc_domains, since we no longer need to be able to modify it. Cc: Stefan Agner <stefan@agner.ch> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: fix regulator deferred probeStefan Agner2017-08-051-7/+8
| | | | | | | | | | | | | | | | | | | | | | If a regulator requests a deferred probe, the power domain gets initialized twice. This leads to a list double add (without list debugging the kernel hangs due to the double add later): WARNING: CPU: 0 PID: 19 at lib/list_debug.c:31 __list_add_valid+0xbc/0xc4 list_add double add: new=c1229754, prev=c12383b4, next=c1229754. Initialize the power domain after we get the regulator. Also do not print an error in case the regulator defers probing. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: Add GPCv2 power gating driverAndrey Smirnov2017-04-071-0/+363
Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are: - PCIE PHY - MIPI PHY - USB HSIC PHY - USB OTG1/2 PHY Support for any other power domain controlled by GPC is not present, and can be added at some later point. Testing of this code was done against a PCIe driver. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-09 17:19:33 +0000