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* Merge tag 'bitmap-5.17-rc1' of git://github.com/norov/linuxLinus Torvalds2022-01-233-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull bitmap updates from Yury Norov: - introduce for_each_set_bitrange() - use find_first_*_bit() instead of find_next_*_bit() where possible - unify for_each_bit() macros * tag 'bitmap-5.17-rc1' of git://github.com/norov/linux: vsprintf: rework bitmap_list_string lib: bitmap: add performance test for bitmap_print_to_pagebuf bitmap: unify find_bit operations mm/percpu: micro-optimize pcpu_is_populated() Replace for_each_*_bit_from() with for_each_*_bit() where appropriate find: micro-optimize for_each_{set,clear}_bit() include/linux: move for_each_bit() macros from bitops.h to find.h cpumask: replace cpumask_next_* with cpumask_first_* where appropriate tools: sync tools/bitmap with mother linux all: replace find_next{,_zero}_bit with find_first{,_zero}_bit where appropriate cpumask: use find_first_and_bit() lib: add find_first_and_bit() arch: remove GENERIC_FIND_FIRST_BIT entirely include: move find.h from asm_generic to linux bitops: move find_bit_*_le functions from le.h to find.h bitops: protect find_first_{,zero}_bit properly
| * cpumask: replace cpumask_next_* with cpumask_first_* where appropriateYury Norov2022-01-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | cpumask_first() is a more effective analogue of 'next' version if n == -1 (which means start == 0). This patch replaces 'next' with 'first' where things look trivial. There's no cpumask_first_zero() function, so create it. Signed-off-by: Yury Norov <yury.norov@gmail.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
| * all: replace find_next{,_zero}_bit with find_first{,_zero}_bit where appropriateYury Norov2022-01-151-2/+2
| | | | | | | | | | | | | | | | | | find_first{,_zero}_bit is a more effective analogue of 'next' version if start == 0. This patch replaces 'next' with 'first' where things look trivial. Signed-off-by: Yury Norov <yury.norov@gmail.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* | riscv: canaan: remove useless select of non-existing config SYSCONLukas Bulwahn2022-01-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The config SYSCON never existed in the kernel repository; so, the select of that config in ./drivers/soc/canaan/Kconfig has no effect. Presumably, this was just some mistake, assuming some symmetry in handling and naming of configs that simply does not exist. Remove this useless select of a non-existing config. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* | Merge tag 'char-misc-5.17-rc1' of ↵Linus Torvalds2022-01-144-7/+658
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the large set of char, misc, and other "small" driver subsystem changes for 5.17-rc1. Lots of different things are in here for char/misc drivers such as: - habanalabs driver updates - mei driver updates - lkdtm driver updates - vmw_vmci driver updates - android binder driver updates - other small char/misc driver updates Also smaller driver subsystems have also been updated, including: - fpga subsystem updates - iio subsystem updates - soundwire subsystem updates - extcon subsystem updates - gnss subsystem updates - phy subsystem updates - coresight subsystem updates - firmware subsystem updates - comedi subsystem updates - mhi subsystem updates - speakup subsystem updates - rapidio subsystem updates - spmi subsystem updates - virtual driver updates - counter subsystem updates Too many individual changes to summarize, the shortlog contains the full details. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (406 commits) counter: 104-quad-8: Fix use-after-free by quad8_irq_handler dt-bindings: mux: Document mux-states property dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC counter: remove old and now unused registration API counter: ti-eqep: Convert to new counter registration counter: stm32-lptimer-cnt: Convert to new counter registration counter: stm32-timer-cnt: Convert to new counter registration counter: microchip-tcb-capture: Convert to new counter registration counter: ftm-quaddec: Convert to new counter registration counter: intel-qep: Convert to new counter registration counter: interrupt-cnt: Convert to new counter registration counter: 104-quad-8: Convert to new counter registration counter: Update documentation for new counter registration functions counter: Provide alternative counter registration functions counter: stm32-timer-cnt: Convert to counter_priv() wrapper counter: stm32-lptimer-cnt: Convert to counter_priv() wrapper counter: ti-eqep: Convert to counter_priv() wrapper counter: ftm-quaddec: Convert to counter_priv() wrapper counter: intel-qep: Convert to counter_priv() wrapper counter: microchip-tcb-capture: Convert to counter_priv() wrapper ...
| * | Merge 5.16-rc8 into char-misc-nextGreg Kroah-Hartman2022-01-034-2/+25
| |\| | | | | | | | | | | | | | | | We need the fixes in here as well for testing. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | driver: soc: xilinx: register for power events in zynqmp power driverAbhyuday Godhasara2021-12-031-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Xilinx Event Management driver, all types of events like power and error gets handled from single place as part of event management driver. So power events(SUSPEND_POWER_REQUEST and SUSPEND_SYSTEM_SHUTDOWN) also gets handled by event management driver instead of zynqmp_power driver. zynqmp-power driver use event management driver and provide callback function for Suspend and shutdown handler, which will be called by event management driver when respective event is arrived. If event management driver is not available than use ipi-mailbox rx channel or IPI interrupt IRQ handler for power events (suspend/shutdown) same as current zynqmp-power driver. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Link: https://lore.kernel.org/r/20211129070216.30253-4-abhyuday.godhasara@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | drivers: soc: xilinx: add xilinx event management driverAbhyuday Godhasara2021-12-033-0/+611
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx event management driver provides an interface to subscribe or unsubscribe for the event/callback supported by firmware. An agent can use this driver to register for Error Event, Device Event and Suspend callback. This driver only allows one agent per event to do registration. Driver will return an error in case of multiple registration for the same event. This driver gets notification from firmware through TF-A as SGI. During initialization, event manager driver register handler for SGI used for notification. It also provides SGI number info to TF-A by using IOCTL_REGISTER_SGI call to TF-A. After receiving notification from firmware, the driver makes an SMC call to TF-A to get IPI data. From the IPI data provided by TF-A, event manager identified the cause of event and forward that event/callback notification to the respective subscribed driver. After this, in case of Error Event, driver performs unregistration as firmware expecting from agent to do re-registration if the agent wants to get notified on the second occurrence of an error event. Add new IOCTL id IOCTL_REGISTER_SGI = 25 which is used to register SGI on TF-A. Older firmware doesn't have all required support for event handling which is required by the event manager driver. So add check for the register notifier version in the event manager driver. Xilinx event management driver provides support to subscribe for multiple error events with the use of Event Mask in a single call of xlnx_register_event(). Agent driver can provide 'Event' parameter value as ORed of multiple event masks to register single callback for multiple events. For example, to register callback for event=0x1 and event=0x2 for the given node, agent can provide event=0x3 (0x1 | 0x2). It is not possible to register multiple events for different nodes in a single registration call. Also provide support to receive multiple error events as in single notification from firmware and then forward it to subscribed drivers via registered callback one by one. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Link: https://lore.kernel.org/r/20211129070216.30253-2-abhyuday.godhasara@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | firmware: xilinx: add macros of node ids for error eventAbhyuday Godhasara2021-11-171-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macros for the Node-Id of Error events. Move supported api callback ids from zynqmp-power to zynqmp-firmware. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Link: https://lore.kernel.org/r/20211026042525.26612-3-abhyuday.godhasara@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | | Merge tag 'sound-5.17-rc1' of ↵Linus Torvalds2022-01-141-4/+11
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "It's a relatively calm development cycle, but still lots of updates in the driver side like Intel SOF. Below are some highlights: ALSA / ASoC core: - A new kselftest for ALSA control API - PCM NO_REWINDS support - Potential race fixes around control removals - Unify x86 SG-buffer memory allocation code - Cleanups and race fixes for ASoC DPCM locking ASoC: - Refinements and cleanups around the delay() APIs - Wider use of dev_err_probe(). - Continuing cleanups and improvements to the SOF code - Support for pin switches in simple-card derived cards - Support for AMD Renoir ACP, Asahi Kasei Microdevices AKM4375, Intel systems using NAU8825 and MAX98390, Mediatek MT8915, nVidia Tegra20 S/PDIF, Qualcomm systems using ALC5682I-VS and Texas Instruments TLV320ADC3xxx HD-audio / USB-audio: - Fix deadlock at HD-audio codec unbinding - Fixes for Tegra194 HD-audio, new HDA support for CS35L41 codec - Quirks for Lenovo and HP machines, Gigabyte mobo, Bose device Misc: - Fix virmidi drain behavior Note that the merge of CS35L41 codec support is still half-baked, and at least one ACPI change is missing. Although this won't hinder the kernel build itself, we're going to catch up before RC1" * tag 'sound-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (415 commits) ALSA: hda: intel-dsp-config: reorder the config table ALSA: hda: intel-dsp-config: add JasperLake support ALSA: hda: cs35l41: fix double free on error in probe() ALSA: hda: Fix dependencies of CS35L41 on SPI/I2C buses ALSA: hda: Fix dependency on ASoC cs35l41 codec ASoC: cs35l41: Add support for hibernate memory retention mode ASoC: cs35l41: Update handling of test key registers ALSA: intel_hdmi: Check for error num after setting mask ASoC: wcd9335: Keep a RX port value for each SLIM RX mux ASoC: amd: acp: acp-mach: Change default RT1019 amp dev id ALSA: virmidi: Remove duplicated code ALSA: seq: virmidi: Add a drain operation ASoC: topology: Fix typo ASoC: fsl_asrc: refine the check of available clock divider ASoC: Intel: bytcr_rt5640: Add support for external GPIO jack-detect ASoC: Intel: bytcr_rt5640: Support retrieving the codec IRQ from the AMCR0F28 ACPI dev ASoC: rt5640: Add support for boards with an external jack-detect GPIO ASoC: rt5640: Allow snd_soc_component_set_jack() to override the codec IRQ ASoC: rt5640: Change jack_work to a delayed_work ASoC: rt5640: Fix possible NULL pointer deref on resume ...
| * | | ASoC: mediatek: Check for error clk pointerJiasheng Jiang2021-12-241-4/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Yes, you are right and now the return code depending on the init_clks(). Fixes: 6078c651947a ("soc: mediatek: Refine scpsys to support multiple platform") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Link: https://lore.kernel.org/r/20211222015157.1025853-1-jiasheng@iscas.ac.cn Signed-off-by: Mark Brown <broonie@kernel.org>
* | | Merge tag 'irq-msi-2022-01-13' of ↵Linus Torvalds2022-01-133-71/+37
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull MSI irq updates from Thomas Gleixner: "Rework of the MSI interrupt infrastructure. This is a treewide cleanup and consolidation of MSI interrupt handling in preparation for further changes in this area which are necessary to: - address existing shortcomings in the VFIO area - support the upcoming Interrupt Message Store functionality which decouples the message store from the PCI config/MMIO space" * tag 'irq-msi-2022-01-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (94 commits) genirq/msi: Populate sysfs entry only once PCI/MSI: Unbreak pci_irq_get_affinity() genirq/msi: Convert storage to xarray genirq/msi: Simplify sysfs handling genirq/msi: Add abuse prevention comment to msi header genirq/msi: Mop up old interfaces genirq/msi: Convert to new functions genirq/msi: Make interrupt allocation less convoluted platform-msi: Simplify platform device MSI code platform-msi: Let core code handle MSI descriptors bus: fsl-mc-msi: Simplify MSI descriptor handling soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs() soc: ti: ti_sci_inta_msi: Rework MSI descriptor allocation NTB/msi: Convert to msi_on_each_desc() PCI: hv: Rework MSI handling powerpc/mpic_u3msi: Use msi_for_each-desc() powerpc/fsl_msi: Use msi_for_each_desc() powerpc/pasemi/msi: Convert to msi_on_each_dec() powerpc/cell/axon_msi: Convert to msi_on_each_desc() powerpc/4xx/hsta: Rework MSI handling ...
| * | | soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs()Thomas Gleixner2021-12-161-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function has no users and is pointless now that the core frees the MSI descriptors, which means potential users can just use msi_domain_free_irqs(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20211206210748.793119155@linutronix.de
| * | | soc: ti: ti_sci_inta_msi: Rework MSI descriptor allocationThomas Gleixner2021-12-161-46/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Protect the allocation properly and use the core allocation and free mechanism. No functional change intended. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20211206210748.737904583@linutronix.de
| * | | soc: ti: ti_sci_inta_msi: Get rid of ti_sci_inta_msi_get_virq()Thomas Gleixner2021-12-162-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just use the core function msi_get_virq(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20211210221815.269468319@linutronix.de
| * | | bus: fsl-mc: fsl-mc-allocator: Rework MSI handlingThomas Gleixner2021-12-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Storing a pointer to the MSI descriptor just to track the Linux interrupt number is daft. Just store the interrupt number and be done with it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20211210221815.207838579@linutronix.de
| * | | soc: ti: ti_sci_inta_msi: Use msi_desc::msi_indexThomas Gleixner2021-12-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the common msi_index member and get rid of the pointless wrapper struct. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20211210221814.540704224@linutronix.de
| * | | soc: ti: ti_sci_inta_msi: Allocate MSI device data on first useThomas Gleixner2021-12-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate the MSI device data on first invocation of the allocation function. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20211210221813.928842960@linutronix.de
| * | | device: Move MSI related data into a structThomas Gleixner2021-12-162-3/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only unconditional part of MSI data in struct device is the irqdomain pointer. Everything else can be allocated on demand. Create a data structure and move the irqdomain pointer into it. The other MSI specific parts are going to be removed from struct device in later steps. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211210221813.617178827@linutronix.de
* | | Merge tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2022-01-101-1/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC devicetree updates from Arnd Bergmann: "As usual, this is the bulk of the updates for the SoC tree, adding more devices to existing files, addressing issues from ever improving automated checking, and fixing minor issues. The most interesting bits as usual are the new platforms. All the newly supported SoCs belong into existing families this time: - Qualcomm gets support for two newly announced platforms, both of which can now work in production environments: the SDX65 5G modem that can run a minimal Linux on its Cortex-A7 core, and the Snapdragon 8 Gen 1, their latest high-end phone SoC. - Renesas adds support for R-Car S4-8, the most recent automotive Server/Communication SoC. - TI adds support for J721s2, a new automotive SoC in the K3 family. - Mediatek MT7986a/b is a SoC used in Wifi routers, the latest generation following their popular MT76xx series. Only basic support is added for now. - NXP i.MX8 ULP8 is a new low-power variant of the widespread i.MX8 series. - TI SPEAr320s is a minor variant of the old SPEAr320 SoC that we have supported for a long time. New boards with the existing SoCs include - Aspeed AST2500/AST2600 BMCs in TYAN, Facebook and Yadro servers - AT91/SAMA5 based evaluation board - NXP gains twenty new development and industrial boards for their i.MX and Layerscape SoCs - Intel IXP4xx now supports the final two machines in device tree that were previously only supported in old style board files. - Mediatek MT6589 is used in the Fairphone FP1 phone from 2013, while MT8183 is used in the Acer Chromebook 314. - Qualcomm gains support for the reference machines using the two new SoCs, plus a number of Chromebook variants and phones based on the Snapdragon 7c, 845 and 888 SoCs, including various Sony Xperia devices and the Microsoft Surface Duo 2. - ST STM32 now supports the Engicam i.Core STM32MP1 carrier board. - Tegra now boots various older Android devices based on 32-bit chips out of the box, including a number of ASUS Transformer tablets. There is also a new Jetson AGX Orin developer kit. - Apple support adds the missing device trees for all the remaining M1 Macbook and iMac variants, though not yet the M1 Pro/Max versions. - Allwinner now supports another version of the Tanix TX6 set-top box based on the H6 SoC. - Broadcom gains support for the Netgear RAXE500 Wireless router based on BCM4908" * tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (574 commits) Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX arm64: dts: qcom: sm8450-qrd: Enable USB nodes arm64: dts: qcom: sm8450: Add usb nodes ARM: dts: aspeed: add LCLK setting into LPC KCS nodes dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property ARM: dts: aspeed: add LCLK setting into LPC IBT node ARM: dts: aspeed: p10: Add TPM device ARM: dts: aspeed: p10: Enable USB host ports ARM: dts: aspeed: Add TYAN S8036 BMC machine ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config ARM: dts: aspeed: Adding Facebook Bletchley BMC ARM: dts: aspeed: g220a: Enable secondary flash ARM: dts: Add openbmc-flash-layout-64-alt.dtsi ARM: dts: aspeed: Add secure boot controller node dt-bindings: aspeed: Add Secure Boot Controller bindings ARM: dts: Remove "spidev" nodes dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 dt-bindings: arm: samsung: Document E850-96 board binding dt-bindings: Add vendor prefix for WinLink ...
| * | | soc: bcm: brcmstb: Add of_node_put() in pm-mipsWan Jiabing2021-11-151-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following coccicheck warning: ./drivers/soc/bcm/brcmstb/pm/pm-mips.c:404:1-23: WARNING: Function for_each_matching_node should have of_node_put() before goto or break Early exits from for_each_matching_node should decrement the node reference counter. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | | Merge tag 'drivers-5.17' of ↵Linus Torvalds2022-01-1042-663/+2054
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are cleanups and minor bugfixes across several SoC specific drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone, Renesas, ZynqMP Noteworthy new features are: - The op-tee firmware driver gains support for asynchronous notifications from secure-world firmware. - Qualcomm platforms gain support for new SoC types in various drivers: power domain, cache controller, RPM sleep, soc-info - Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as well as a new USIv2 driver that handles various types of serial communiction (uart, i2c, spi) - Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers, as well as memory controller support for RZ/G2L (R9A07G044). - Apple M1 gains support for the PMGR power management driver" * tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ...
| * | Merge tag 'qcom-drivers-for-5.17' of ↵Arnd Bergmann2021-12-2110-141/+281
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.17 This introduces RPM power-domain support for the SM8450, SM6125 and QCM2290 platforms. It them clean up the platform-based naming of the resources definitions throughout the RPMh PD driver. The last-level cache controller driver gains SM8350 support. The RPM sleep stats driver gains support for several older systems that had a slightly different memory layout for this information. The socinfo gains SM8450, SM6350 and SM7227 definitions. In addition to the DeviceTree binding updates related to these changes new compatibles was added to describe the SM8450 and the Kryo 780 CPU. Lastly a few typo and style fixes are introduced. * tag 'qcom-drivers-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ... Link: https://lore.kernel.org/r/20211221040452.3620633-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | soc: qcom: rpmh-rsc: Fix typo in a commentJason Wang2021-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The double `for' in the comment in line 694 is repeated. Remove one of them from the comment. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211211090626.248801-1-wangborong@cdjrlc.com
| | * | soc: qcom: socinfo: Add SM6350 and SM7225Luca Weiss2021-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both SoCs are known as 'lagoon' downstream. Add their ids to the socinfo driver. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213081111.20217-1-luca.weiss@fairphone.com
| | * | soc: qcom: rpmhpd: Sort power-domain definitions and listsRajendra Nayak2021-12-201-60/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort all power-domain defines and the SoC specific lists in alphabetical order for better readability. No functional changes. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-5-git-send-email-quic_rjendra@quicinc.com
| | * | soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280Rajendra Nayak2021-12-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The requirement to specify the active + sleep and active-only MX power-domains as the parents of the corresponding CX power domains is not applicable on sc7280. Fix it by using the cx/cx_ao structs for sc7280 instead of the _w_mx_parent ones. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-4-git-send-email-quic_rjendra@quicinc.com
| | * | soc: qcom: rpmhpd: Rename rpmhpd struct namesRajendra Nayak2021-12-201-170/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rpmhpd structs were named with a SoC-name prefix, but then they got reused across multiple SoC families making things confusing. Rename all the struct names to remove SoC-name prefixes. While we do this we end up with some power-domains without parents, and some with and at times different parents across SoCs. use a _w_<parent-name>_parent suffix for such cases. No functional change as part of this patch. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-3-git-send-email-quic_rjendra@quicinc.com
| | * | soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_aoRajendra Nayak2021-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sm8450_cx and sm8450_cx_ao should be peers of each other, add the missing .peer entry for sm8450_cx_ao Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-2-git-send-email-quic_rjendra@quicinc.com
| | * | soc: qcom: socinfo: add SM8450 IDDmitry Baryshkov2021-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ID for the Qualcomm SM8450 SoC. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-8-vkoul@kernel.org
| | * | soc: qcom: rpmhpd: Add SM8450 power domainsDmitry Baryshkov2021-12-201-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the power domains exposed by RPMH in the Qualcomm SM8450 platform. Unlike previous generations CX domain is not a child of MX domain. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-7-vkoul@kernel.org
| | * | soc: qcom: smem: Update max processor countDmitry Baryshkov2021-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update max processor count to reflect the number of co-processors on SM8450 SoCs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-5-vkoul@kernel.org
| | * | soc: qcom: rpmpd: Add support for sm6125Martin Botka2021-12-201-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add RPM power domains located in Qualcomm SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211130212332.25401-2-martin.botka@somainline.org
| | * | soc: qcom: aoss: constify static struct thermal_cooling_device_opsRikard Falkeborn2021-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only usage of qmp_cooling_device_ops is to pass its address to devm_thermal_of_cooling_device_register() which takes a pointer to const struct thermal_cooling_device_ops as argument. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211128210317.25504-1-rikard.falkeborn@gmail.com
| | * | PM: AVS: qcom-cpr: Use div64_ul instead of do_divChangcheng Deng2021-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211125014311.45942-1-deng.changcheng@zte.com.cn
| | * | soc: qcom: llcc: Add configuration data for SM8350Konrad Dybcio2021-12-201-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LLCC configuration data for SM8350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org
| | * | soc: qcom: stats: Add fixed sleep stats offset for older RPM firmwaresStephan Gerhold2021-12-201-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all RPM firmware versions have the dynamic sleep stats offset available. Most older versions use a fixed offset of 0xdba0. Add support for this using new SoC-specific compatibles for APQ8084, MSM8226, MSM8916 and MSM8974. Even older SoCs seem to use a different offset and stats format. If needed those could be supported in the future by adding separate compatibles for those with a different stats_config. Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211119213953.31970-3-stephan@gerhold.net
| | * | soc: qcom: rpmpd: Add QCM2290 supportShawn Guo2021-11-181-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QCM2290 has the same RPM power domains as SM6115. Add QCM2290 support by reusing SM6115 power domains. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211108134442.30051-4-shawn.guo@linaro.org
| | * | soc: qcom: rpmpd: Drop unused res_name from struct rpmpdShawn Guo2021-11-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The res_name field in struct rpmpd is unused. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211108134442.30051-2-shawn.guo@linaro.org
| | * | soc: qcom: qmi: Fix a typo in a commentJason Wang2021-11-181-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | The double word `client' in a comment is repeated, thus one of them should be removed. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211113055358.206533-1-wangborong@cdjrlc.com
| * | Merge tag 'samsung-drivers-5.17' of ↵Arnd Bergmann2021-12-205-0/+306
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung SoC drivers changes for v5.17 1. Exynos ChipID: add Exynos7885 support. 2. Exynos PMU: add Exynos850 support. 3. Minor bindings cleanup. 4. Add Exynos USIv2 (Universal Serial Interface) driver. The USI block is a shared IP block between I2C, UART/serial and SPI. Basically one has to choose which feature the USI block will support and later the regular I2C/serial/SPI driver will bind and work. This merges also one commit with dt-binding headers from my dts64 pull request. Together with a future serial driver change, this will break the ABI. Affected: Serial on ExynosAutov9 SADK and out-of-tree ExynosAutov9 boards Why: To properly and efficiently support the USI with new hierarchy of USI-{serial,SPI,I2C} devicetree nodes. Rationale: Recently added serial and USI support was short-sighted and did not allow to smooth support of other features (SPI and I2C). Adding support for USI-SPI and USI-I2C would effect in code duplication. Adding support for different USI versions (currently supported is USIv2 but support for v1 is planned) would cause even more code duplication and create a solution difficult to maintain. Since USI-serial and ExynosAutov9 have been added recently, are considered fresh development features and there are no supported products using them, the code/solution is being refactored in non-backwards compatible way. The compatibility is not broken yet. It will be when serial driver changes are accepted. The ABI break was discussed with only known users of ExynosAutov9 and received their permission. * tag 'samsung-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: soc: samsung: keep SoC driver bindings together soc: samsung: Add USI driver dt-bindings: soc: samsung: Add Exynos USI bindings soc: samsung: exynos-pmu: Add Exynos850 support dt-bindings: samsung: pmu: Document Exynos850 soc: samsung: exynos-chipid: add Exynos7885 SoC support soc: samsung: exynos-chipid: describe which SoCs go with compatibles Link: https://lore.kernel.org/r/20211220115405.30434-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | soc: samsung: Add USI driverSam Protsenko2021-12-183-0/+301
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204195757.8600-3-semen.protsenko@linaro.org Tested-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
| | * | soc: samsung: exynos-pmu: Add Exynos850 supportSam Protsenko2021-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos850 SoC can reuse PMU driver functionality. Add corresponding compatible string. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211028144313.9444-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
| | * | soc: samsung: exynos-chipid: add Exynos7885 SoC supportDavid Virag2021-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos 7885 has product ID "0xE7885000". Add this ID to the IDs with the name. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20211101004853.55810-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
| | * | soc: samsung: exynos-chipid: describe which SoCs go with compatiblesKrzysztof Kozlowski2021-11-151-0/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos ChipID driver, like most of the Exynos drivers, uses one compatible for entire family of compatible devices using one devicetree "compatible". The compatibility is here described by programming interface (register layout), not by actual values, so the product ID register on one family of devices has different values for different SoCs. Describe which SoC goes with which compatible for documentation purposes, if the DTS is not available in mainline. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211031205212.59505-1-krzysztof.kozlowski@canonical.com
| * | Merge tag 'imx-drivers-5.17' of ↵Arnd Bergmann2021-12-202-2/+104
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.17: - A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add i.MX8MN display related domain support. - Add optional continuous burst clock support for imx-weim bus driver. - Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and MIX domain. * tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled bus: imx-weim: optionally enable continuous burst clock soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active soc: imx: gpcv2: Synchronously suspend MIX domains Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrlAdam Ford2021-12-171-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the description for the i.MX8MN disp blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | soc: imx: gpcv2: Add dispmix and mipi domains to imx8mnAdam Ford2021-12-171-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabledAdam Ford2021-12-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock activeAdam Ford2021-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the vpu-h1 clock when the domain is active because reading or writing to the VPU-H1 IP block cause the system to hang. Fixes: 656ade7aa42a ("soc: imx: gpcv2: keep i.MX8M* bus clocks enabled") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-17 07:28:06 +0000