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* Add cs42l43 PC focused SoundWire CODECMark Brown2023-08-181-0/+7
|\ | | | | | | | | | | | | Merge series from Charles Keepax <ckeepax@opensource.cirrus.com>: This patch chain adds support for the Cirrus Logic cs42l43 PC focused SoundWire CODEC.
| * spi: cs42l43: Add SPI controller supportLucas Tanure2023-08-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface (Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed for portable applications. It provides a high dynamic range, stereo DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. The SPI component incorporates a SPI controller interface for communication with other peripheral components. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230804104602.395892-6-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: loongson: add bus driver for the loongson spi controllerYinbo Zhu2023-07-311-0/+26
|/ | | | | | | | | | | | | This bus driver supports the Loongson SPI hardware controller in the Loongson platforms and supports the use DTS and PCI framework to register SPI device resources. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Mark Brown <broonie@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230613075834.5219-3-zhuyinbo@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: rzv2m-csi: Fix SoC product nameGeert Uytterhoeven2023-07-031-1/+1
| | | | | | | | | The SoC product name is "RZ/V2M". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/89e9870a2c510387e4d7a863025f4d3639d4a261.1688375020.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add support for Renesas CSIFabrizio Castro2023-06-231-0/+6
| | | | | | | | | | | The RZ/V2M SoC comes with the Clocked Serial Interface (CSI) IP, which is a master/slave SPI controller. This commit adds a driver to support CSI master mode. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-4-fabrizio.castro.jz@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: introduction of stm32h7 SPI device mode supportValentin Caron2023-06-151-0/+1
| | | | | | | | | | | Add support for stm32h7 to use SPI controller in device role. In such case, the spi instance should have the spi-slave property defined. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20230615075815.310261-5-valentin.caron@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: add support for Amlogic A1 SPI Flash ControllerMartin Kurbanov2023-04-111-0/+7
| | | | | | | | | | This is a driver for the Amlogic SPI flash controller support on A113L SoC. Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230403183217.13280-3-mmkurbanov@sberdevices.ru Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: nxp-flexspi: Add i.MX platform dependencyAlexander Stein2023-03-131-1/+1
| | | | | | | | | | This driver also supports various i.MX8 platforms. Add ARCH_MXC for selecting this driver without Layerscape support. Fixes: c6b15b2437a10 ("spi: nxp-flexspi: Fix ARCH_LAYERSCAPE dependency") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20230313083621.154729-1-alexander.stein@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: fsi: restore CONFIG_FSI dependencyArnd Bergmann2023-03-111-1/+1
| | | | | | | | | | | | | | | | | The assumption that the build dependency was not necessary turned out to be wrong, as building SPI_FSI without FSI results in a link failure: aarch64-linux-ld: drivers/spi/spi-fsi.o: in function `fsi_spi_check_status': spi-fsi.c:(.text+0x54): undefined reference to `fsi_device_read' aarch64-linux-ld: drivers/spi/spi-fsi.o: in function `fsi_spi_read_reg': spi-fsi.c:(.text+0x120): undefined reference to `fsi_device_write' aarch64-linux-ld: spi-fsi.c:(.text+0x170): undefined reference to `fsi_device_read' Fixes: f916c7080d28 ("spi: fsi: Make available for build test") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230310140605.569363-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* Add Quad SPI driver for StarFive JH7110 SoCMark Brown2023-03-061-1/+1
|\ | | | | | | | | | | | | | | | | | | Merge series from William Qiu <william.qiu@starfivetech.com>: This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board.The first patch constrain minItems/maxItems of resets for JH7110 QSPI and Patch 2 adds support for StarFive JH7110 QSPI.
| * spi: cadence-quadspi: Add support for StarFive JH7110 QSPIWilliam Qiu2023-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add QSPI reset operation in device probe and add RISCV support to QUAD SPI Kconfig. Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230302105221.197421-3-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: qcom-qspi: Make available for build testMark Brown2023-03-051-1/+1
| | | | | | | | | | | | | | | | | | There is no build time dependency on the Qualcomm platform support so add an || COMPILE_TEST so we've got better build coverage of the driver. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-spi-arch-deps-v1-6-83d1566474cf@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: fsi: Make available for build testMark Brown2023-03-051-1/+1
| | | | | | | | | | | | | | | | | | There is no build time dependency on the platform support so add an || COMPILE_TEST so we've got better build coverage of the driver. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-spi-arch-deps-v1-5-83d1566474cf@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: davinci: Make available for build testMark Brown2023-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | There is no build time dependency on the DaVicni or Keystone architecture support so add an || COMPILE_TEST so we've got better build coverage of the driver. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-spi-arch-deps-v1-4-83d1566474cf@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: nxp-flexspi: Fix ARCH_LAYERSCAPE dependencyMark Brown2023-03-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Currently the NXP Flex SPI driver has a dependency on ARCH_LAYERSCAPE || HAS_IOMEM which means that the dependency is almost always true and the driver available. Really these should be two separate dependencies, with an || COMPILE_TEST dependency for the architecture to ensure build coverage is maintained. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-spi-arch-deps-v1-3-83d1566474cf@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: rockchip: Add architecture dependencyMark Brown2023-03-051-0/+1
|/ | | | | | | | | | If base support for Rockchip SoCs has been disabled then the SPI driver won't be terribly useful, add a dependency on ARCH_ROCKCHIP || COMPILE_TEST to avoid it appearing when not needed. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230221-spi-arch-deps-v1-2-83d1566474cf@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'spi-v6.3' of ↵Linus Torvalds2023-02-221-16/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "This has been a fairly quiet release for SPI, though it is likely that the next release will have some big changes as there's some preparatory work for multiple chip select support gone in - the rest of the code is on the list but will need to be rebased onto -rc1. Otherwise there's a couple of new tunables for chip select timings, some new devices and smaller device specific updates and fixes. - Support for configuring the hold and minimum inactive times for chip selects. - Beginnings of support for supporting devices which have multiple chip selects on a single device. - Support for newer Broadcom HSSPI and Intel controllers, Silicon Labs EM3581 and SI3210" * tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits) spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains spi: spidev: drop the incorrect notice from Kconfig spi: bcm63xx-hsspi: fix error code in probe spi: bcmbca-hsspi: Fix error code in probe() function spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one() spi: intel: Check number of chip selects after reading the descriptor spi: xilinx: add force_irq for QSPI mode spi: spi-st-ssc: convert to DT schema spi: Reorder fields in 'struct spi_transfer' spi: cadence-quadspi: use STIG mode for small reads spi: cadence-quadspi: setup ADDR Bits in cmd reads spi: cadence-quadspi: Add flag for direct mode writes spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers spi: bcmbca-hsspi: Add driver for newer HSSPI controller spi: bcm63xx-hsspi: Disable spi mem dual io read op support spi: spi-mem: Allow controller supporting mem_ops without exec_op spi: bcm63xx-hsspi: Add prepend mode support ...
| * spi: spidev: drop the incorrect notice from KconfigBartosz Golaszewski2023-02-161-3/+0
| | | | | | | | | | | | | | | | | | The spidev interface has been de-facto stable for many years. This notice has been unchanged since 2007 and is incorrect so remove it. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230216123014.110541-1-brgl@bgdev.pl Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang2023-02-101-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: intel: Update help text of PCI and Platform driversMauro Lima2023-02-101-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern intel hardware uses controllers that work in hardware sequencing mode. In this mode, the controller exposes a subset of operations, like read, write and erase, making it easier and less error-prone for use. On the other hand, most of the controllers handled by the platform driver use software sequencing that exposes the entire set of operations i.e. exposes the low level SPI-NOR opcodes to the software for use. Update PCI and Platform help text with this information. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230210164158.211065-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: intel: Remove DANGEROUS tag from pci driverMauro Lima2023-02-071-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Modern CPUs exposes this controller as PCI device that only uses hardware sequencing capabilities which is safer than software sequencing. Leave the platform driver as *DANGEROUS* and update help text since most of these controllers are using software sequencing. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230206183143.75274-2-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: dw_bt1: fix MUX_MMIO dependenciesArnd Bergmann2023-01-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Selecting a symbol with additional dependencies requires adding the same dependency here: WARNING: unmet direct dependencies detected for MUX_MMIO Depends on [n]: MULTIPLEXER [=y] && OF [=n] Selected by [y]: - SPI_DW_BT1 [=y] && SPI [=y] && SPI_MASTER [=y] && SPI_DESIGNWARE [=y] && (MIPS_BAIKAL_T1 || COMPILE_TEST [=y]) Drop the 'select' here to avoid the problem. Anyone using the dw-bt1 SPI driver should make sure they include the mux driver as well now. Fixes: 7218838109fe ("spi: dw-bt1: Fix undefined devm_mux_control_get symbol") Fixes: abf00907538e ("spi: dw: Add Baikal-T1 SPI Controller glue driver") Link: https://lore.kernel.org/all/20221218192523.c6vnfo26ua6xqf26@mobilestation/ Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230130140156.3620863-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Kconfig: fix a spelling mistake & hyphenationRandy Dunlap2023-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Correct a spelling mistake (reported by codespell). Also hyphenate "8-bit". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Link: https://lore.kernel.org/r/20230124233502.23330-1-rdunlap@infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: remove s3c24xx driverArnd Bergmann2023-01-161-18/+0
| | | | | | | | | | | | | | | | The s3c24xx platform was removed,s o there are no remaining users for its spi driver. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | spi: remove omap 100K driverArnd Bergmann2023-01-121-6/+0
|/ | | | | | | | | | | | | | The OMAP7xx/OMAP8xx support was removed since all of its boards have no remaining users. Remove its spi driver as well. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Janusz Krzysztofik <jmkrzyszt@gmail.com> Cc: linux-omap@vger.kernel.org Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Fabrice Crohas <fcrohas@gmail.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Nuvoton WPCM450 FIU SPI flash controllerMark Brown2022-11-251-0/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Jonathan Neuschäfer <j.neuschaefer@gmx.net>: This patchset adds DT bindings and a driver for the Flash Interface Unit (FIU), the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The existing NPCM7xx FIU driver is sufficitently incompatible with the WPCM450 FIU that I decided to write a new driver.
| * spi: wpcm-fiu: Add driver for Nuvoton WPCM450 Flash Interface Unit (FIU)Jonathan Neuschäfer2022-11-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221124191400.287918-3-j.neuschaefer@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: cadence: Drop obsolete dependency on COMPILE_TESTJean Delvare2022-11-251-1/+1
|/ | | | | | | | | | | Since commit 0166dc11be91 ("of: make CONFIG_OF user selectable"), it is possible to test-build any driver which depends on OF on any architecture by explicitly selecting OF. Therefore depending on COMPILE_TEST as an alternative is no longer needed. Signed-off-by: Jean Delvare <jdelvare@suse.de> Link: https://lore.kernel.org/r/20221125083114.67e7f83c@endymion.delvare Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add Socionext F_OSPI SPI flash controller driverKunihiko Hayashi2022-11-241-0/+9
| | | | | | | | | | | | | Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI Flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221124003351.7792-3-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switchTharun Kumar P2022-10-171-0/+9
| | | | | | | | | | | | Microchip pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. SPI is one of the functions in the multi-function endpoint. This function has 2 SPI masters, operates at a maximum frequency of 30 MHz and supports 7 client devices per master. This patch adds complete functionality to the SPI function except for suspend and resume. Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Link: https://lore.kernel.org/r/20221006050514.115564-2-tharunkumar.pasumarthi@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: microchip-core-qspi: Add support for microchip fpga qspi controllersNaga Sureshkumar Relli2022-08-151-0/+9
| | | | | | | | | | Add a driver for Microchip FPGA QSPI controllers. This driver also supports "hard" QSPI controllers on Polarfire SoC. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220808064603.1174906-4-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'spi-v5.20' of ↵Linus Torvalds2022-08-021-0/+16
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The big update this time around is some excellent work from David Jander who went through the fast path and really eliminated overheads, meaning that we are seeing a huge reduction in the time spent between transfers for single threaded clients. Benchmarking has been coming out at about a halving of overhead which is clearly visible in system level usage that stresses SPI like some CAN and IIO applications, especially with small transfers. Thanks to David for taking the time to drill down into this and push the work upstream. Otherwise there's been a bunch of new device support and the usual updates. - Optimisation of the fast path, particularly around the number and types of locking operations, from David Jander. - Support for Arbel NPCM845, HP GXP, Intel Meteor Lake and Thunder Bay, MediaTek MT8188 and MT8365, Microchip FPGAs, nVidia Tegra 241 and Samsung Exynos Auto v9 and 4210" * tag 'spi-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (97 commits) MAINTAINERS: add spi support to GXP spi: dt-bindings: add documentation for hpe,gxp-spifi spi: spi-gxp: Add support for HPE GXP SoCs spi: a3700: support BE for AC5 SPI driver spi/panel: dt-bindings: drop CPHA and CPOL from common properties spi: bcm2835: enable shared interrupt support spi: dt-bindings: spi-controller: correct example indentation spi: dt-bindings: qcom,spi-geni-qcom: allow three interconnects spi: npcm-fiu: Add NPCM8XX support dt-binding: spi: Add npcm845 compatible to npcm-fiu document spi: npcm-fiu: Modify direct read dummy configuration spi: atmel: remove #ifdef CONFIG_{PM, SLEEP} spi: dt-bindings: Add compatible for MediaTek MT8188 spi: dt-bindings: mediatek,spi-mtk-nor: Update bindings for nor flash spi: dt-bindings: atmel,at91rm9200-spi: convert to json-schema spi: tegra20-slink: fix UAF in tegra_slink_remove() spi: Fix simplification of devm_spi_register_controller spi: microchip-core: switch to use dev_err_probe() spi: microchip-core: switch to use devm_spi_alloc_master() spi: microchip-core: fix UAF in mchp_corespi_remove() ...
| * spi: spi-gxp: Add support for HPE GXP SoCsNick Hawkins2022-07-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: add support for microchip fpga spi controllersConor Dooley2022-06-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | Add a driver for Microchip FPGA SPI controllers, specifically supporting the "hard" controllers on PolarFire SoC. Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220607073833.2331539-2-conor.dooley@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm63xx-hsspi: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCAWilliam Zhang2022-07-111-1/+1
|/ | | | | | | | | | Prepare for the BCM63138 ARCH_BCM_63XX migration to ARCH_BCMBCA. Make SPI_BCM63XX_HSSPI depending on ARCH_BCMBCA. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'arm-multiplatform-5.19-1' of ↵Linus Torvalds2022-05-261-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARMv4T/v5 multiplatform support from Arnd Bergmann: "This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these" * tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits) ARM: ixp4xx: Consolidate Kconfig fixing issue ARM: versatile: Add missing of_node_put in dcscb_init ARM: config: Refresh IXP4xx config after multiplatform ARM: omap1: add back omap_set_dma_priority() stub ARM: omap: fix missing declaration warnings ARM: omap: fix address space warnings from sparse ARM: spear: remove include/mach/ subdirectory ARM: davinci: remove include/mach/ subdirectory ARM: omap2: remove include/mach/ subdirectory integrator: remove empty ap_init_early() ARM: s3c: fix include path MAINTAINERS: omap1: Add Janusz as an additional maintainer ARM: omap1: htc_herald: fix typos in comments ARM: OMAP1: fix typos in comments ARM: OMAP1: clock: Remove noop code ARM: OMAP1: clock: Remove unused code ARM: OMAP1: clock: Fix UART rate reporting algorithm ARM: OMAP1: clock: Fix early UART rate issues ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF ARM: omap1: fix build with no SoC selected ...
| * ARM: omap1: move perseus spi pinconf to board fileArnd Bergmann2022-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver has always had a FIXME about this, and it seems like this trivial code move avoids a mach header inclusion, so just do it. With that out of the way, and the header file inclusions changed to global files, the driver can also be compile-tested on other platforms. Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | spi: spi-mem: Convert Aspeed SMC driver to spi-memCédric Le Goater2022-05-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This SPI driver adds support for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface. * AST2600 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . Only supports SPI type flash memory . different segment register interface . single, dual and quad mode. * AST2600 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . different segment register interface . single, dual and quad mode. * AST2500 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver . single, dual mode. * AST2500 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . single, dual mode. * AST2400 New Static Memory Controller (also referred as FMC) . BMC firmware . New register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. . single, dual and quad mode. Each controller has a memory range on which flash devices contents are mapped. Each device is assigned a window that can be changed at bootime with the Segment Address Registers. Each SPI flash device can then be accessed in two modes: Command and User. When in User mode, SPI transfers are initiated with accesses to the memory segment of a device. When in Command mode, memory operations on the memory segment of a device generate SPI commands automatically using a Control Register for the settings. This initial patch adds support for User mode. Command mode needs a little more work to check that the memory window on the AHB bus fits the device size. It will come later when support for direct mapping is added. Single and dual mode RX transfers are supported. Other types than SPI are not supported. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-imx: replace struct spi_imx_data::bitbang by pointer to struct ↵Marc Kleine-Budde2022-05-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_controller There's no need to embed the struct spi_bitbang into our private data (struct spi_imx_data), the spi core is flexible enough, so that we only need a pointer to the allocated struct spi_controller. This is also a preparation patch to add PIO based polling support to the driver. Co-developed-by: David Jander <david@protonic.nl> Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220502175457.1977983-8-mkl@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: add driver for MTK SPI NAND Flash InterfaceChuanhong Guo2022-04-271-0/+10
| | | | | | | | | | | | | | | | | | | | This driver implements support for the SPI-NAND mode of MTK NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Tested-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: ingenic: Add support for new Ingenic SoCs.周琰杰 (Zhou Yanjie)2022-04-251-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4775-spi" compatible string in the driver. This will permit to support the JZ4775 by having: compatible = "ingenic,jz4775-spi"; Instead of doing: compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi"; 2.Add support for probing the spi-ingenic driver on the X1000 SoC from Ingenic. From the X1000 SoC onwards, the maximum frequency allowed by the SSI module of Ingenic SoCs has been changed from 54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info" to set different maximum frequency values. 3.Add support for probing the spi-ingenic driver on the X2000 SoC from Ingenic. The X2000 SoC has only one native chip select line, so "max_native_cs" is introduced in "jz_soc_info" to set different maximum number of native chip select lines. 4.Because of the introduction of support for the X-series SoCs, the current driver is not only applicable to the JZ-series SoCs, so the description texts has been modified to avoid misunderstanding. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'mtd/changes-for-5.18' of ↵Linus Torvalds2022-03-251-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "There has been a lot of activity in the MTD subsystem recently, with a number of SPI-NOR cleanups as well as the introduction of ECC engines that can be used by SPI controllers (hence a few SPI patches in here). Core MTD changes: - Replace the expert mode symbols with a single helper - Fix misuses of of_match_ptr() - Remove partid and partname debugfs files - tests: Fix eraseblock read speed miscalculation for lower partition sizes - TRX parser: Allow to use on MediaTek MIPS SoCs MTD driver changes: - spear_smi: use GFP_KERNEL - mchp48l640: Add SPI ID table - mchp23k256: Add SPI ID table - blkdevs: Avoid soft lockups with some mtd/spi devices - aspeed-smc: Improve probe resilience Hyperbus changes: - HBMC_AM654 should depend on ARCH_K3 NAND core changes: - ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: - Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode - Make two read-only arrays static const - Fix compile test issue Raw NAND core changes: - Fix misuses of of_match_node() - Rework of_get_nand_bus_width() - Remove of_get_nand_on_flash_bbt() wrapper - Protect access to rawnand devices while in suspend - bindings: Document the wp-gpios property Rax NAND controller driver changes: - atmel: Fix refcount issue in atmel_nand_controller_init - nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc - rockchip: Fix platform_get_irq.cocci warning - stm32_fmc2: Add NAND Write Protect support - pl353: Set the nand chip node as the flash node - brcmnand: Fix sparse warnings in bcma_nand - omap_elm: Remove redundant variable 'errors' - gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting - brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: - Check for error irq SPI-NAND core changes: - Delay a little bit the dirmap creation - Create direct mapping descriptors for ECC operations SPI-NAND driver changes: - macronix: Use random program load SPI NOR core changes: - Move vendor specific code out of the core into vendor drivers. - Unify all function and object names in the vendor modules. - Make setup() callback optional to improve readability. - Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. SPI changes: - Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations - spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure Binding changes: - Dropped mtd/cortina,gemini-flash.txt - Convert BCM47xx partitions to json-schema - Vendor prefixes: Clarify Macronix prefix - SPI NAND: Convert spi-nand description file to yaml - Raw NAND chip: Create a NAND chip description - Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description - Describe Macronix NAND ECC engine - Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory" * tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits) mtd: nand: ecc: mxic: Fix compile test issue mtd: nand: mxic-ecc: make two read-only arrays static const mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3 mtd: core: Remove partid and partname debugfs files dt-bindings: mtd: partitions: convert BCM47xx to the json-schema mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init mtd: rawnand: rockchip: fix platform_get_irq.cocci warning mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set mtd: spi-nor: renumber flags mtd: spi-nor: slightly change code style in spi_nor_sr_ready() mtd: spi-nor: spansion: rename vendor specific functions and defines mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag mtd: spi-nor: move all spansion specifics into spansion.c mtd: spi-nor: spansion: slightly rework control flow in late_init() mtd: spi-nor: micron-st: rename vendor specific functions and defines mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag mtd: spi-nor: move all micron-st specifics into micron-st.c mtd: spi-nor: xilinx: correct the debug message mtd: spi-nor: xilinx: rename vendor specific functions and defines ...
| * spi: mxic: Add support for pipelined ECC operationsMiquel Raynal2022-02-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPI-NAND chips do not have a proper on-die ECC engine providing error correction/detection. This is particularly an issue on embedded devices with limited resources because all the computations must happen in software, unless an external hardware engine is provided. These external engines are new and can be of two categories: external or pipelined. Macronix is providing both, the former being already supported. The second, however, is very SoC implementation dependent and must be instantiated by the SPI host controller directly. An entire subsystem has been contributed to support these engines which makes the insertion into another subsystem such as SPI quite straightforward without the need for a lot of specific functions. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/linux-mtd/20220202144536.393792-1-miquel.raynal@bootlin.com
* | mtd: spi-nor / spi / MFD: Convert intel-spi to SPI MEMMark Brown2022-02-151-0/+39
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Mika Westerberg <mika.westerberg@linux.intel.com>: Based on discussion on the patch I sent some time ago here: http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html it turns out that the preferred way to deal with the SPI flash controller drivers is through SPI MEM which is part of Linux SPI subsystem. This series does that for the intel-spi driver. This also renames the driver to follow the convention used in the SPI subsystem. The first patch improves the write protection handling to be slightly more safer. The following two patches do the conversion itself. Note the Intel SPI flash controller only allows commands such as read, write and so on and it internally uses whatever addressing etc. it figured from the SFDP on the flash device. base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
| * | mtd: spi-nor: intel-spi: Convert to SPI MEMMika Westerberg2022-02-141-0/+39
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The preferred way to implement SPI-NOR controller drivers is through SPI subsubsystem utilizing the SPI MEM core functions. This converts the Intel SPI flash controller driver over the SPI MEM by moving the driver from SPI-NOR subsystem to SPI subsystem and in one go make it use the SPI MEM functions. The driver name will be changed from intel-spi to spi-intel to match the convention used in the SPI subsystem. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220209122706.42439-3-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* / spi: Add spi driver for Sunplus SP7021Li-hao Kuo2022-01-251-0/+11
|/ | | | | | | | Add spi driver for Sunplus SP7021. Signed-off-by: Li-hao Kuo <lhjeff911@gmail.com> Link: https://lore.kernel.org/r/37998e515d561e762ee30d0ac4fca25a948e0c5c.1642494310.git.lhjeff911@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: xlp: Remove Netlogic XLP variantsRob Herring2021-11-151-6/+5
| | | | | | | | | | | | | | Netlogic XLP was removed in commit 95b8a5e0111a ("MIPS: Remove NETLOGIC support"). With those gone, the single platform left to support is Cavium ThunderX2. Remove the Netlogic variant and DT support. For simplicity, the existing kconfig name is retained. Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211109161325.2203564-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge series "add support for Cadence's XSPI controller" from Parshuram ↵Mark Brown2021-09-271-0/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thombare <pthombar@cadence.com>: This patch series adds support for Cadence's XSPI controller. It supports 3 work modes. 1. ACMD (auto command) work mode ACMD name is because it uses auto command engine in the controller. It further has 2 modes PIO and CDMA (command DMA). The CDMA work mode is dedicated for high-performance application where very low software overhead is required. In this mode the Command Engine is programmed by the series of linked descriptors stored in system memory. These descriptors provide commands to execute and store status information for finished commands. The PIO mode work mode is dedicated for single operation where constructing a linked list of descriptors would require too much effort. 2. STIG (Software Triggered Instruction Generator) work mode In STIG mode, controller sends low-level instructions to memory. Each instruction is 128-bit width. There is special instruction DataSequence which carries information about data phase. Driver uses Slave DMA interface to transfer data as only this interface can be used in STIG work mode. 3. Direct work mode This work mode allows sending data without invoking any command through the slave interface. Currently only STIG work mode is enabled, remaining work modes will be added later. Changes since v5: 1. Added adjust_op_size to adjust op size according to sdma size. Changes since v4: 1. Changed reg region names and lengths as suggested by Rob. Changes since v3: 1. Removed ACMD PIO mode. 2. Return IRQ_HANDLED only for handled interrupts. 3. DT binding changes. Changes since v2: 1. Removed extra lock around exec_op. 2. Removed PHY parameters setting from the driver, those will be handled by bootstrap pins available in the controller. Changes since v1: 1. Use ACMD PIO work mode for NOR read, program and erase operations, for everything else use STIG(Software Triggered Instruction Generator) work mode. 2. Changes suggested by Lukas. Parshuram Thombare (2): spi: cadence: add dt-bindings documentation for Cadence XSPI controller spi: cadence: add support for Cadence XSPI controller .../devicetree/bindings/spi/cdns,xspi.yaml | 77 +++ drivers/spi/Kconfig | 12 + drivers/spi/Makefile | 1 + drivers/spi/spi-cadence-xspi.c | 640 +++++++++++++++++++++ 4 files changed, 730 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/cdns,xspi.yaml create mode 100644 drivers/spi/spi-cadence-xspi.c -- 2.7.4
| * spi: cadence: add support for Cadence XSPI controllerParshuram Thombare2021-09-271-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver for Cadence's XSPI controller. It supports 3 work modes. 1. ACMD (auto command) work mode ACMD name is because it uses auto command engine in the controller. It further has 2 modes PIO and CDMA (command DMA). The CDMA work mode is dedicated for high-performance application where very low software overhead is required. In this mode the Command Engine is programmed by the series of linked descriptors stored in system memory. These descriptors provide commands to execute and store status information for finished commands. The PIO mode work mode is dedicated for single operation where constructing a linked list of descriptors would require too much effort. 2. STIG (Software Triggered Instruction Generator) work mode In STIG mode, controller sends low-level instructions to memory. Each instruction is 128-bit width. There is special instruction DataSequence which carries information about data phase. Driver uses Slave DMA interface to transfer data as only this interface can be used in STIG work mode. 3. Direct work mode This work mode allows sending data without invoking any command through the slave interface. Currently only STIG work mode is enabled, remaining work modes will be added later. Signed-off-by: Konrad Kociolek <konrad@cadence.com> Signed-off-by: Jayshri Pawar <jpawar@cadence.com> Signed-off-by: Parshuram Thombare <pthombar@cadence.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/1632038734-23999-1-git-send-email-pthombar@cadence.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: s3c64xx: describe driver in KConfigKrzysztof Kozlowski2021-09-271-2/+3
|/ | | | | | | | | Describe better which driver applies to which SoC, to make configuring kernel for Samsung SoC easier. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210924133114.111777-1-krzysztof.kozlowski@canonical.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-13 01:12:09 +0000