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* spi: bcm2835aux: warn in dmesg that native cs is not really supportedMartin Sperl2019-04-031-0/+33
| | | | | | | | | | | | | | | From personal bad experience (even as the author of the original driver) it shows that native-cs is "somewhat" supported by the spi bus driver when using a buggy device tree. So make sure that the driver is warning in dmesg about this fact that we are running in a not supported mode that may have surprizing limitations. Fixes: 1ea29b39f4c812ec ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: fix driver to not allow 65535 (=-1) cs-gpiosMartin Sperl2019-04-031-1/+12
| | | | | | | | | | | | | | | | | | | | | | | The original driver by default defines num_chipselects as -1. This actually allicates an array of 65535 entries in of_spi_register_master. There is a side-effect for buggy device trees that (contrary to dt-binding documentation) have no cs-gpio defined. This mode was never supported by the driver due to limitations of native cs and additional code complexity and is explicitly not stated to be implemented. To keep backwards compatibility with such buggy DTs we limit the number of chip_selects to 1, as for all practical purposes it is only ever realistic to use a single chip select in native cs mode without negative side-effects. Fixes: 1ea29b39f4c812ec ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: remove dead codeMartin Sperl2019-04-031-3/+0
| | | | | | | | | | Remove dead code that never can get reached, as we limit count to a max of 3. Suggested-by: Hubert Denkmair <h.denkmair@intence.de> Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: fix corruptions for longer spi transfersMartin Sperl2019-04-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On long running tests with a mcp2517fd can controller it showed that on rare occations the data read shows corruptions for longer spi transfers. Example of a 22 byte transfer: expected (as captured on logic analyzer): FF FF 78 00 00 00 08 06 00 00 91 20 77 56 84 85 86 87 88 89 8a 8b read by the driver: FF FF 78 00 00 00 08 06 00 00 91 20 77 56 84 88 89 8a 00 00 8b 9b To fix this use BCM2835_AUX_SPI_STAT_RX_LVL to determine when we may read data from the fifo reliably without any corruption. Surprisingly the only values ever empirically read in BCM2835_AUX_SPI_STAT_RX_LVL are 0x00, 0x10, 0x20 and 0x30. So whenever the mask is not 0 we can read from the fifo in a safe manner. The patch has now been tested intensively and we are no longer able to reproduce the "RX" issue any longer. Fixes: 1ea29b39f4c812ec ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Reported-by: Hubert Denkmair <h.denkmair@intence.de> Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: remove dangerous uncontrolled read of fifoMartin Sperl2019-04-031-7/+0
| | | | | | | | | | | | | | This read of the fifo is a potential candidate for a race condition as the spi transfer is not necessarily finished and so can lead to an early read of the fifo that still misses data. So it has been removed. Fixes: 1ea29b39f4c812ec ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Suggested-by: Hubert Denkmair <h.denkmair@intence.de> Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: unifying code between polling and interrupt driven codeMartin Sperl2019-04-031-33/+18
| | | | | | | | Sharing more code between polling and interrupt-driven mode. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: export spi_mem_default_supports_op()Naga Sureshkumar Relli2019-04-031-2/+2
| | | | | | | | | | | | Export spi_mem_default_supports_op(), so that controller drivers can use this. spi-mem driver already exports this using EXPORT_SYMBOL, but not declared it in spi-mem.h. This patch declares spi_mem_default_supports_op() in spi-mem.h and also removes the static from the function prototype. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-msiof: Use BIT() and GENMASK()Geert Uytterhoeven2019-04-031-87/+87
| | | | | | | | | | | Improve maintainability by converting the register bit, bitmask, and bitfield definitions from hexadecimal constants to constructs using BIT(), GENMASK(), or "val << shift". Suggested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-fsl-spi: automatically adapt bits-per-word in cpu modeRasmus Villemoes2019-04-021-0/+16
| | | | | | | | | | | Taking one interrupt for every byte is rather slow. Since the controller is perfectly capable of transmitting 32 bits at a time, change t->bits_per-word to 32 when the length is divisible by 4 and large enough that the reduced number of interrupts easily compensates for the one or two extra fsl_spi_setup_transfer() calls this causes. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-fsl-spi: allow changing bits_per_word while CS is still activeRasmus Villemoes2019-04-021-5/+6
| | | | | | | | | | | | | | | | | | | | | | Commit c9bfcb315104 (spi_mpc83xx: much improved driver) introduced logic to ensure bits_per_word and speed_hz stay the same for a series of spi_transfers with CS active, arguing that The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. This sounds quite reasonable. So this is a quite naive attempt at relaxing this sanity checking to only ensure that speed_hz is constant - in the faint hope that if we do not causes changes to the clock-related fields of the SPMODE register (DIV16 and PM), those glitches won't appear. The purpose of this change is to allow automatically optimizing large transfers to use 32 bits-per-word; taking one interrupt for every byte is extremely slow. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Unify remaing prints in pxa2xx_spi_transfer_one()Jarkko Nikula2019-04-021-2/+2
| | | | | | | | | | | | | Use SPI device pointer in the remaining two error and warning prints in pxa2xx_spi_transfer_one() instead of platform device of the controller It make prints in the function uniform and more useful especially the error print here as it can reveal the driver that has mapped the DMA itself and attempts to transfer more than the maximum supported DMA transfer length. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Use struct spi_device directly in pxa2xx_spi_transfer_one()Jarkko Nikula2019-04-021-7/+7
| | | | | | | | Pointer to a SPI device is passed to pxa2xx_spi_transfer_one() so there is no need to access it through the current SPI message pointer. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra114: add SPI_LSB_FIRST supportSowjanya Komatineni2019-04-011-1/+6
| | | | | | | | | | | | Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra114: use packed mode for 32 bits per wordSowjanya Komatineni2019-04-011-1/+1
| | | | | | | | Fixes: Use packed mode for 32 bits per word transfers to increase performance as each packet is a full 32-bit word. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-fsl-spi: relax message sanity checking a littleRasmus Villemoes2019-04-011-3/+5
| | | | | | | | | | | | | The comment says that we should not allow changes (to bits_per_word/speed_hz) while CS is active, and indeed the code below does fsl_spi_setup_transfer() when the ->cs_change of the previous spi_transfer was set (and for the very first transfer). So the sanity checking is a bit too strict - we can change it to follow the same logic as is used by the actual transfer loop. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-fsl-spi: remove always-true conditional in fsl_spi_do_one_msgRasmus Villemoes2019-04-011-6/+4
| | | | | | | | __spi_validate() in the generic SPI code sets ->speed_hz and ->bits_per_word to non-zero values, so this condition is always true. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32-qspi: add dma supportLudovic Barre2019-03-261-1/+135
| | | | | | | | | | | This patch adds the dma support for the stm32-qspi hardware. The memory buffer constraints (lowmem, vmalloc, kmap) are taken into account by framework. In read mode, the memory map is preferred vs dma (due to better throughput). If the dma transfer fails the buffer is sent by polling. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32-qspi: add spi_master_put in release functionLudovic Barre2019-03-261-18/+28
| | | | | | | | This patch adds spi_master_put in release function to drop the controller's refcount. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: mt7621: Move SPI driver out of stagingStefan Roese2019-03-253-0/+428
| | | | | | | | | | | | | | | | | | | | | | | | This patch moves the MT7621 SPI driver, which is used on some Ralink / MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to the source code are done in this patch. This driver version was tested successfully on an MT7688 based platform with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so far). This patch also documents the devicetree bindings for the MT7621 SPI device driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: NeilBrown <neil@brown.name> Cc: Sankalp Negi <sankalpnegi2310@gmail.com> Cc: Chuanhong Guo <gch981213@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Armando Miraglia <arma2ff0@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: at91-usart: Remove duplicated checking for spi->bits_per_wordAxel Lin2019-03-251-7/+1
| | | | | | | | This checking is already done in __spi_validate_bits_per_word(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: atmel-quadspi: Make atmel_qspi_get_name staticYueHaibing2019-03-251-1/+1
| | | | | | | | | | Fix sparse warning: drivers/spi/atmel-quadspi.c:369:12: warning: symbol 'atmel_qspi_get_name' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: export tracepoint symbols to modulesArnd Bergmann2019-03-211-0/+2
| | | | | | | | | | | | | | | | The newly added tracepoints in the spi-mxs driver cause a link error when the driver is a loadable module: ERROR: "__tracepoint_spi_transfer_stop" [drivers/spi/spi-mxs.ko] undefined! ERROR: "__tracepoint_spi_transfer_start" [drivers/spi/spi-mxs.ko] undefined! I'm not quite sure where to put the export statements, but directly after the inclusion of the header seems as good as any other place. Fixes: f3fdea3af405 ("spi: mxs: add tracing to custom .transfer_one_message callback") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Debug print DMA burst sizeAndy Shevchenko2019-03-201-0/+3
| | | | | | | | | It's useful during debug to see what DMA burst size is. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Introduce DMA burst size supportAndy Shevchenko2019-03-203-1/+8
| | | | | | | | | | | Some masters may have different DMA burst size than hard coded default. In such case respect the value given by DMA burst size provided via platform data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add support for an optional interface clockPhil Edworthy2019-03-201-0/+12
| | | | | | | | | | | The Synopsys SSI Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: mxic: simplify getting .driver_dataWolfram Sang2019-03-201-4/+2
| | | | | | | | We should get 'driver_data' from 'struct device' directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: stm32-qspi: stm32_qspi_pm_ops can be statickbuild test robot2019-03-201-1/+1
| | | | | | Fixes: 2e541b64ee52 ("spi: spi-mem: stm32-qspi: add suspend/resume support") Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'v5.1-rc1' into spi-5.2Mark Brown2019-03-191-1/+0
|\ | | | | | | Linux 5.1-rc1
| * Merge tag 'pci-v5.1-changes' of ↵Linus Torvalds2019-03-091-1/+0
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - Use match_string() instead of reimplementing it (Andy Shevchenko) - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada) - Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) - Fix DPC use of uninitialized data (Dongdong Liu) - Probe bridge window attributes only once at enumeration-time to fix device accesses during rescan (Bjorn Helgaas) - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du Changbin) - Use config header type (not class code) identify bridges more reliably (Honghui Zhang) - Work around Intel Denverton incorrect Trace Hub BAR size reporting (Alexander Shishkin) - Reorder pciehp cached state/hardware state updates to avoid missed interrupts (Mika Westerberg) - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann) - Mark expected switch fall-through (Mathieu Malaterre) - Use of_node_name_eq() for node name comparisons (Rob Herring) - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang) - Consolidate Rohm Vendor ID definitions (Andy Shevchenko) - Use u32 (not __u32) for things not exposed to userspace (Logan Gunthorpe) - Fix locking semantics of bus and slot reset interfaces (Alex Williamson) - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang) - Allow portdrv to claim subtractive decode Ports so PCIe services will work for them (Honghui Zhang) - Report PCIe links that become degraded at run-time (Alexandru Gagniuc) - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt hotplug (Mika Westerberg) - Revert runtime PM suspend/resume callbacks that broke PME on network cable plug (Mika Westerberg) - Disable Data Link State Changed interrupts to prevent wakeup immediately after suspend (Mika Westerberg) - Extend altera to support Stratix 10 (Ley Foon Tan) - Allow building altera driver on ARM64 (Ley Foon Tan) - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint maintainer (Lorenzo Pieralisi) - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro) - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) - Configure MPS settings for VMD root ports (Jon Derrick) * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits) PCI: Update PCIEPORTBUS Kconfig help text PCI: Fix "try" semantics of bus and slot reset PCI/LINK: Report degraded links via link bandwidth notification dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 PCI: altera: Enable driver on ARM64 PCI: altera: Add Stratix 10 PCIe support PCI/PME: Fix possible use-after-free on remove PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ...
| | * PCI: Move Rohm Vendor ID to generic listAndy Shevchenko2019-02-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the Rohm Vendor ID to pci_ids.h instead of defining it in several drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* | | spi: pxa2xx-pci: Drop unused header inclusionAndy Shevchenko2019-03-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing in the driver which requires OF specific header to be included. Remove it for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: fsl_lpspi_runtime_resume() can be statickbuild test robot2019-03-191-2/+2
| | | | | | | | | | | | | | | | | | Fixes: 944c01a889d9 ("spi: lpspi: enable runtime pm for lpspi") Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: spi-fsl-spi: support use of the SPISEL_BOOT signal on MPC8309Rasmus Villemoes2019-03-182-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8309 has a dedicated signal, SPISEL_BOOT, usually used as chip select for the flash device from which the bootloader is loaded. It is not an ordinary gpio, but is simply controlled via the SPI_CS register in the system configuration. To allow accessing such a spi slave, we need to teach fsl_spi_cs_control() how to control the SPISEL_BOOT signal. To distinguish the gpio-controlled slaves, continue to have those use chip_select values of 0..ngpios-1, and use chip_select == ngpios for the boot flash. I'm not too happy with all the ifdeffery, but it seems to be necessary for guarding the sysdev/fsl_soc.h and use of get_immrbase() (spi-fsl-lib.c already contains similar ifdeffery). Googling suggests that the MPC8306 is similar, with the SPI_CS register at the same offset. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: orion: Support spi_xfer->word_delay_usecsJan Kundrát2019-03-181-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: spidev: Enable control of inter-word delaysJan Kundrát2019-03-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b7bb367afa4b added support for inserting delays in between individual words within a single SPI transaction. This makes it accessible from userspace. WARNING: This delay is silently ignored unless the SPI controller implements extra support for it. This is similar to how the in-kernel users handle the other existing property, spi_transfer->word_delay. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: Code cleanupClark Wang2019-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Delete the extra space. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: Add the missing NULL checkClark Wang2019-03-181-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The spi_transfer *t will be used in one transfer whatever. If t is NULL, there has no need to try sending data, so add an error return here. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Acked-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: add dma mode supportClark Wang2019-03-181-11/+301
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dma mode support for LPSPI. Any frame longer than half txfifosize will be sent by dma mode. For now, there are some limits: 1. The maximum transfer speed in master mode depends on the slave device, at least 40MHz(tested by spi-nor on 8qm-lpddr4-arm2 base board); 2. The maximum transfer speed in slave mode is 15MHz(imx7ulp), 22MHz(8qm/qxp). In order to reach the maximum speed which is mentioned in datasheet, the load of connect wires between master and slave should be less than 15pF. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Acked-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: use the core way to implement cs-gpio functionClark Wang2019-03-181-35/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the default implementation of transfer_one_msg/chipselect/setup functions in spi core to implement cs-gpio control. Use fsl_lpspi_prepare_message to init the cs_gpio pin. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Acked-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: add the error info of transfer speed settingClark Wang2019-03-181-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a error info when set a speed which greater than half of per-clk of spi module. The minimum SCK period is 2 cycles(CCR[SCKDIV]). So the maximum transfer speed is half of spi per-clk. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: enable runtime pm for lpspiHan Xu2019-03-181-25/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the runtime power management for lpspi module. Do some adaptation work from kernel 4.9 to 4.14. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: lpspi: Add i.MX8 boards support for lpspiClark Wang2019-03-181-11/+41
| | | | | | | | | | | | | | | | | | | | | Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: spi-mem: stm32-qspi: add suspend/resume supportLudovic Barre2019-03-151-4/+35
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | Merge branch 'spi-5.1' into spi-5.2 for stm32Mark Brown2019-03-154-30/+26
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| * | | spi: spi-mem: stm32-qspi: avoid memory corruption at low frequencyLudovic Barre2019-03-151-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: rspi: Fix sequencer reset during initializationGeert Uytterhoeven2019-03-151-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the sequencer is reset after each SPI message since commit 880c6d114fd79a69 ("spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI"), it was never reset for the first message, thus relying on reset state or bootloader settings. Fix this by initializing it explicitly during configuration. Fixes: 0b2182ddac4b8837 ("spi: add support for Renesas RSPI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: rspi: Fix register initialization while runtime-suspendedGeert Uytterhoeven2019-03-151-23/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Renesas RSPI/QSPI driver performs SPI controller register initialization in its spi_operations.setup() callback, without calling pm_runtime_get_sync() first, which may cause spurious failures. So far this went unnoticed, as this SPI controller is typically used with a single SPI NOR FLASH containing the boot loader: 1. If the device's module clock is still enabled (left enabled by the bootloader, and not yet disabled by the clk_disable_unused() late initcall), register initialization succeeds, 2. If the device's module clock is disabled, register writes don't seem to cause lock-ups or crashes. Data received in the first SPI message may be corrupted, though. Subsequent SPI messages seem to be OK. E.g. on r8a7791/koelsch, one bit is lost while receiving the 6th byte of the JEDEC ID for the s25fl512s FLASH, corrupting that byte and all later bytes. But until commit a2126b0a010905e5 ("mtd: spi-nor: refine Spansion S25FL512S ID"), the 6th byte was not considered for FLASH identification. Fix this by moving all initialization from the .setup() to the .prepare_message() callback. The latter is always called after the device has been runtime-resumed by the SPI core. This also makes the driver follow the rule that .setup() must not change global driver state or register values, as that might break a transfer in progress. Fixes: 490c97747d5dc77d ("spi: rspi: Add runtime PM support, using spi core auto_runtime_pm") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: imx: stop buffer overflow in RX FIFO flushTrent Piepho2019-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 71abd29057cb ("spi: imx: Add support for SPI Slave mode") added an RX FIFO flush before start of a transfer. In slave mode, the master may have sent more data than expected and this data will still be in the RX FIFO at the start of the next transfer, and so needs to be flushed. However, the code to do the flush was accidentally saving this data into the previous transfer's RX buffer, clobbering the contents of whatever followed that buffer. Change it to empty the FIFO and throw away the data. Every one of the RX functions for the different eCSPI versions and modes reads the RX FIFO data using the same readl() call, so just use that, rather than using the spi_imx->rx function pointer and making sure all the different rx functions have a working "throw away" mode. There is another issue, which affects master mode when switching from DMA to PIO. There can be extra data in the RX FIFO which triggers this flush code, causing memory corruption in the same manner. I don't know why this data is unexpectedly in the FIFO. It's likely there is a different bug or erratum responsible for that. But regardless of that, I think this is proper fix the for bug at hand here. Fixes: 71abd29057cb ("spi: imx: Add support for SPI Slave mode") Cc: Jiada Wang <jiada_wang@mentor.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: Fix zero length xfer bugChris Lesiak2019-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a bug for messages containing both zero length and unidirectional xfers. The function spi_map_msg will allocate dummy tx and/or rx buffers for use with unidirectional transfers when the hardware can only do a bidirectional transfer. That dummy buffer will be used in place of a NULL buffer even when the xfer length is 0. Then in the function __spi_map_msg, if he hardware can dma, the zero length xfer will have spi_map_buf called on the dummy buffer. Eventually, __sg_alloc_table is called and returns -EINVAL because nents == 0. This fix prevents the error by not using the dummy buffer when the xfer length is zero. Signed-off-by: Chris Lesiak <chris.lesiak@licor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | | spi: spi-fsl-qspi: use devm_spi_register_controllerVolker Haspel2019-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver does not clearly unregister the spi controller. Therefore calling an unbind and bind again will end up in a Kernel crash. The function devm_spi_register_controller will automatically be unregister the SPI device. Signed-off-by: Volker Haspel <volker.haspel@linutronix.de> Signed-off-by: John Ogness <john.ogness@linutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 18:37:59 +0000